3f9a77bd10
Originally, the VAX allowed immediate operands (8F) to be used without restrictions in address mode instructions, either standalone or indexed. Starting with MicroVAX II, immediate indexed became reserved. This remained true for all subsequent chip implementations. The SRM was ECOed in March, 1985 to make immediate indexed unpredictable. In MicroVAX II, immediate g-floating operands didn't work correctly. The problem was found a couple of months after tape-out. While the index flows could be fixed, and were fixed according to the microcode revision history: ; 7-May-84 [RMS] Fixed FD problem in index flows (JLR) the problem in indexed immediate could only be fixed by a significant hardware change in an area that was already packed full. The VAX Architecture Team, which had always been very sympathetic to the VAX chip efforts, proposed a much simpler solution: make immediate indexed unpredictable. It was useless, in any case. I'm rather surprised that this wasn't flagged by the 780 diagnostics. Maybe it was never tested. It was tested in HCORE (the original MicroVAX I core diagnostic that is failing), but I removed it subsequently: ; 8-may-85 rms removed indexed immediate tests Bottom line - the simulator is right for the chip VAXes (including, I think, V11) and wrong for MicroVAX I and probably the 8600, 780, 750, and 730. # Conflicts: # VAX/vax_cpu.c
75 lines
3.8 KiB
Text
75 lines
3.8 KiB
Text
Bugs Found And Fixed During Simulator Debug
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1. RP: drive clear does not clear RPDA.
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2. TU: default formatter must be TM03.
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3. SBI: drive 'letter' is actually a 1-based number.
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4. MBA: drive register reads return SR<31:16> as high word.
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5. UBA: DMA addresses must be masked to Unibus width (18b).
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6. HK: thread used multiple times if SEEK is followed by NOP or DCLR.
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7. HK: only DCLR clears ATA.
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8. MEM: MS780E size declaration off-by-1.
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9. MEM: MS780E array start off by >> 4.
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10. MEM: CSR-C register write logic incorrect.
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11. CIS: CMPP3/CMPP4 using wrong arguments to ReadDstr.
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12. CPU, OCTA: CVTfi with integer overflow not setting trap if PSW<iv> = 1.
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13. STDDEV: read of ICR was missing the call parameter.
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14. ACBD/G: testing wrong operand register to get limit sign.
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15. CPU: faults not clearing PSL<tp>.
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16. ADAWI: register mode implemented incorrectly.
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17. MOVTC: condition codes not preserved through page fault.
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18. MOVTUC: condition codes not preserved through page fault.
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19. MOVTUC: escape tested against untranslated rather than translated character.
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20. CVTPT: condition code and decimal overflow calculation incorrect.
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21. CVTPS: condition code and decimal overflow calculation incorrect.
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22. CVTPL: if destination is register, result is stored after register updates.
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23. CVTPL: integer overflow set <C> rather than <V>.
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24. all decimal string: 11/780 does not validate characters in decimal strings.
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25. EDITPC: condition codes not preserved through page fault.
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26. EDITPC EO$INSERT: inserts sign instead of fill.
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27. EDITPC EO$BLANK_ZERO: address off by one.
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28. EDITPC EO$BLANK_ZERO: not testing for <C> set.
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29. EDITPC EO$LOAD_PLUS: not skipping character if test fails.
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30. EDITPC EO$LOAD_MINUS: not skipping character if test fails.
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31. Compatibility mode: SXT not implemented.
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32. Compatibility mode: XOR operands fetched in wrong order.
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33. MNEGH: condition codes set from original sign.
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34. MNEGH: <C> not cleared.
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35. H_floating quad precision integer routines (add, inc, neg): carry propagation incorrect.
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36. H_floating packup routines: test for zero used exponent not fraction.
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37. MULH: carries out of floating accumulator lost.
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38. DIVH: stores wrong operand as result.
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39. POLYF/D/G: truncation after add not needed.
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40. POLYF/D/G: early SRM requires truncation to 31b/63b, not 32b/64b.
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41. POLYF/D/G/H: exits too early if argument is zero.
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42. POLYD/G/H: calculates address of residual pointer result incorrectly.
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43. POLYD/G: performs single precision rather than double precision multiply.
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44. POLYH: fails to truncate intermediate result from 128b to 127b.
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45. POLYF/D/G/H: internal add routine must test fraction rather than exponent to
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detect zero, POLYx can create "denormalized" intermediate result.
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46. EMODH: concatenate 16b of extension operand instead of 15b.
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47. Specifier flows: modify flows testing for read access rather than write access.
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48. Quad/octa writes: wrong address reported on faulting cross-page writes.
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49. Memory management: 11/780 implements access control test on first level PTE's.
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50. LDPCTX: 11/780 implements mbz tests on PCB fields.
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51. LDPCTX/MTPR: 11/780 validity checks PCBB, SCBB, SBR, SLR, P0BR, P0LR, P1BR, P1LR.
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52. TMR: tmr_inc not updated in standard (100Hz) mode.
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53. MTPR SBR/PCBB/SCBB: 11/780 only checks that bits<1:0> == 0.
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54. MTPR xLR: 11/780 excludes bits<31:24> from mbz test.
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55. MTPR PxBR: 11/780 only checks bits<31,1:0> == 1,00.
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56. EMODx: integer overflow case requiring left shift returns wrong result.
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57. BPT, XFC: not clearing PSL<tp> before taking exception.
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58. POLYx: add step <does> require truncation (proved by AXE tests).
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59. Unaligned references to IO space: incorrect on CVAX.
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60. REI to compatibility mode: PSL<dv,fu,iv> were not checked for mbz.
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61. Indexed immediate not does fault.
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