f028802bff
- MicroVAX 2000 & VAXstation 2000 - MicroVAX 3100 M10/M20 - MicroVAX 3100 M10e/M20e - InfoServer 100 - InfoServer 150 VXT - VAXstation 3100 M30 - VAXstation 3100 M38 - VAXstation 3100 M76 - VAXstation 4000 VLC - VAXstation 4000 M60 - MicroVAX 3100 M80 - InfoServer 1000
179 lines
9.6 KiB
C
179 lines
9.6 KiB
C
/* vax_xs.h: LANCE ethernet simulator
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Copyright (c) 2019, Matt Burke
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This module is partly based on the DEUNA simulator, Copyright (c) 2003-2011, David T. Hittner
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name(s) of the author(s) shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from the author(s).
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xs LANCE Ethernet Controller
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*/
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#include "vax_defs.h"
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#include "sim_ether.h"
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#define XS_QUE_MAX 500 /* message queue array */
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#define XS_FILTER_MAX 11 /* mac + 10 multicast addrs */
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struct xs_setup {
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int32 promiscuous; /* promiscuous mode enabled */
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int32 multicast; /* enable all multicast addresses */
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uint32 mult0;
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uint32 mult1;
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int32 mac_count; /* number of multicast mac addresses */
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ETH_MAC macs[XS_FILTER_MAX]; /* MAC addresses to respond to */
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};
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struct xs_device {
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/*+ initialized values - DO NOT MOVE */
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ETH_PCALLBACK rcallback; /* read callback routine */
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ETH_PCALLBACK wcallback; /* write callback routine */
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/*- initialized values - DO NOT MOVE */
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/* I/O register storage */
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uint32 irq; /* interrupt request flag */
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ETH_MAC mac; /* MAC address */
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ETH_DEV* etherface; /* buffers, etc. */
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ETH_PACK read_buffer;
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ETH_PACK write_buffer;
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ETH_QUE ReadQ;
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struct xs_setup setup;
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uint16 csr0; /* LANCE registers */
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uint16 csr1;
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uint16 csr2;
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uint16 csr3;
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uint16 rptr; /* register pointer */
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uint16 mode; /* mode register */
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uint32 inbb; /* initialisation block base */
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uint32 tdrb; /* transmit desc ring base */
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uint32 telen; /* transmit desc ring entry len */
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uint32 trlen; /* transmit desc ring length */
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uint32 txnext; /* transmit buffer pointer */
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uint32 rdrb; /* receive desc ring base */
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uint32 relen; /* receive desc ring entry len */
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uint32 rrlen; /* receive desc ring length */
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uint32 rxnext; /* receive buffer pointer */
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uint16 rxhdr[4]; /* content of RX ring entry, during wait */
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uint16 txhdr[4]; /* content of TX ring entry, during xmit */
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};
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struct xs_controller {
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DEVICE* dev; /* device block */
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UNIT* unit; /* unit block */
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DIB* dib; /* device interface block */
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struct xs_device* var; /* controller-specific variables */
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};
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typedef struct xs_controller CTLR;
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/* CSR definitions */
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#define CSR0_ESUM 0x8000 /* <15> error summary */
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#define CSR0_BABL 0x4000 /* <14> transmitter timeout */
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#define CSR0_CERR 0x2000 /* <13> collision error */
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#define CSR0_MISS 0x1000 /* <12> missed packet */
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#define CSR0_MERR 0x0800 /* <11> memory error */
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#define CSR0_RINT 0x0400 /* <10> receive interrupt */
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#define CSR0_TINT 0x0200 /* <09> transmit interrupt */
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#define CSR0_IDON 0x0100 /* <08> initialisation done */
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#define CSR0_INTR 0x0080 /* <07> interrupt reqest */
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#define CSR0_RXON 0x0020 /* <05> receiver on */
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#define CSR0_TXON 0x0010 /* <04> transmitter on */
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#define CSR0_TDMD 0x0008 /* <03> transmitter demand */
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#define CSR0_STOP 0x0004 /* <02> stop */
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#define CSR0_STRT 0x0002 /* <01> start */
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#define CSR0_INIT 0x0001 /* <00> initialise */
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#define CSR0_RW (CSR_IE)
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#define CSR0_W1C (CSR0_IDON | CSR0_TINT | CSR0_RINT | \
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CSR0_MERR | CSR0_MISS | CSR0_CERR | \
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CSR0_BABL)
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#define CSR0_ERR (CSR0_BABL | CSR0_CERR | CSR0_MISS | \
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CSR0_MERR)
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/* Mode definitions */
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#define MODE_PROM 0x8000 /* <15> Promiscuous Mode */
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#define MODE_INTL 0x0040 /* <06> Internal Loopback */
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#define MODE_DRTY 0x0020 /* <05> Disable Retry */
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#define MODE_COLL 0x0010 /* <04> Force Collision */
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#define MODE_DTCR 0x0008 /* <03> Disable Transmit CRC */
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#define MODE_LOOP 0x0004 /* <02> Loopback */
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#define MODE_DTX 0x0002 /* <01> Disable Transmitter */
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#define MODE_DRX 0x0001 /* <00> Disable Receiver */
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/* Transmitter Ring definitions */
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#define TXR_OWN 0x8000 /* <15> we own it (1) */
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#define TXR_ERRS 0x4000 /* <14> error summary */
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#define TXR_MORE 0x1000 /* <12> Mult Retries Needed */
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#define TXR_ONE 0x0800 /* <11> One Collision */
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#define TXR_DEF 0x0400 /* <10> Deferred */
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#define TXR_STF 0x0200 /* <09> Start Of Frame */
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#define TXR_ENF 0x0100 /* <08> End Of Frame */
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#define TXR_HADR 0x00FF /* <7:0> High order buffer address */
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#define TXR_BUFL 0x8000 /* <15> Buffer Length Error */
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#define TXR_UFLO 0x4000 /* <14> Underflow Error */
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#define TXR_LCOL 0x1000 /* <12> Late Collision */
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#define TXR_LCAR 0x0800 /* <11> Lost Carrier */
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#define TXR_RTRY 0x0400 /* <10> Retry Failure (16x) */
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#define TXR_TDR 0x01FF /* <9:0> TDR value if RTRY=1 */
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/* Receiver Ring definitions */
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#define RXR_OWN 0x8000 /* <15> we own it (1) */
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#define RXR_ERRS 0x4000 /* <14> Error Summary */
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#define RXR_FRAM 0x2000 /* <13> Frame Error */
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#define RXR_OFLO 0x1000 /* <12> Message Overflow */
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#define RXR_CRC 0x0800 /* <11> CRC Check Error */
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#define RXR_BUFL 0x0400 /* <10> Buffer Length error */
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#define RXR_STF 0x0200 /* <09> Start Of Frame */
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#define RXR_ENF 0x0100 /* <08> End Of Frame */
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#define RXR_HADR 0x00FF /* <7:0> High order buffer address */
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#define RXR_MLEN 0x0FFF /* <11:0> Message Length */
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BITFIELD xs_tdes_w1[] = {
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BITNCF(8), BIT(ENP), BIT(STP), BIT(DEF), BIT(ONE), BIT(MORE), BIT(FCS), BIT(ERR), BIT(OWN),
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ENDBITS
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};
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BITFIELD xs_tdes_w2[] = {
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BITFFMT(mlen,12,"0x%X"),
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ENDBITS
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};
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BITFIELD xs_rdes_w1[] = {
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BITNCF(8), BIT(ENP), BIT(STP), BIT(BUFL), BIT(CRC), BIT(OFLO), BIT(FRAM), BIT(ERRS), BIT(OWN),
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ENDBITS
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};
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BITFIELD xs_rdes_w2[] = {
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BITFFMT(blen,12,"0x%X"),
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ENDBITS
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};
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BITFIELD xs_rdes_w3[] = {
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BITFFMT(mlen,12,"0x%X"),
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ENDBITS
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};
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/* Debug definitions */
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#define DBG_TRC 0x0001
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#define DBG_REG 0x0002
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#define DBG_PCK 0x0004
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#define DBG_DAT 0x0008
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#define DBG_ETH 0x0010
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