bad1e0e565
* IMLAC: Type consistency warnings. * Remove unintentional changes * Remove extra braces * CUR_AC -> AC (revert)
508 lines
11 KiB
C
508 lines
11 KiB
C
/* imlac_dp.c: Imlac display processor
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Copyright (c) 2020, Lars Brinkhoff
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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LARS BRINKHOFF BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Lars Brinkhoff shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Lars Brinkhoff.
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*/
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#include "imlac_defs.h"
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/* Debug */
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#define DBG 0001
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static t_addr DPC;
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static t_addr DT[8];
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static uint16 SP = 0;
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static uint16 ON = 0;
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static uint16 HALT = 0;
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static uint16 MODE = 0;
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static uint16 XA, YA;
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static uint16 SCALE = 2;
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static uint16 BLOCK = 0;
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static uint16 MIT8K;
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static uint16 SGR;
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static uint16 SYNC = 1;
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/* Function declaration. */
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static uint16 dp_iot (uint16, uint16);
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static t_stat dp_svc (UNIT *uptr);
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static t_stat dp_reset(DEVICE *dptr);
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static uint16 sync_iot (uint16, uint16);
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static t_stat sync_svc (UNIT *uptr);
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static IMDEV dp_imdev = {
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3,
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{ { 0000, dp_iot, { NULL, NULL, NULL, "DLA" } },
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{ 0001, dp_iot, { NULL, "CTB", "DOF", NULL } },
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{ 0030, dp_iot, { NULL, NULL, NULL, "DCF" } } }
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};
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static UNIT dp_unit = {
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UDATA (&dp_svc, UNIT_IDLE, 0)
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};
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static REG dp_reg[] = {
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{ ORDATAD (DPC, DPC, 16, "Display program counter") },
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{ ORDATAD (ON, ON, 1, "Display on") },
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{ ORDATAD (HALT, HALT, 1, "Display halted") },
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{ ORDATAD (MODE, MODE, 1, "Display mode") },
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{ BRDATAD (DT, DT, 8, 16, 8, "Return address stack") },
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{ ORDATAD (SP, SP, 3, "Stack pointer") },
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{ ORDATAD (XA, XA, 11, "X accumulator") },
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{ ORDATAD (YA, YA, 11, "Y accumulator") },
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{ ORDATAD (SCALE, SCALE, 3, "Scale") },
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{ ORDATAD (BLOCK, BLOCK, 3, "Block") },
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{ ORDATAD (MIT8K, MIT8K, 1, "MIT 8K addressing") },
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{ ORDATAD (SGR, SGR, 1, "Suppressed grid mode") },
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{ NULL }
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};
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static DEBTAB dp_deb[] = {
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{ "DBG", DBG },
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{ NULL, 0 }
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};
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DEVICE dp_dev = {
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"DP", &dp_unit, dp_reg, NULL,
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1, 8, 16, 1, 8, 16,
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NULL, NULL, dp_reset,
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NULL, NULL, NULL, &dp_imdev, DEV_DEBUG, 0, dp_deb,
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NULL, NULL, NULL, NULL, NULL, NULL
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};
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static UNIT sync_unit = {
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UDATA (&sync_svc, UNIT_IDLE, 0)
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};
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static REG sync_reg[] = {
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{ ORDATAD (SYNC, SYNC, 1, "Flag") },
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{ NULL }
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};
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static IMDEV sync_imdev = {
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1,
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{ { 0007, sync_iot, { NULL, "SCF", "IOS", NULL } } }
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};
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static DEBTAB sync_deb[] = {
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{ "DBG", DBG },
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{ NULL, 0 }
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};
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DEVICE sync_dev = {
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"SYNC", &sync_unit, sync_reg, NULL,
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1, 8, 16, 1, 8, 16,
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NULL, NULL, NULL,
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NULL, NULL, NULL,
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&sync_imdev, DEV_DEBUG, 0, sync_deb,
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NULL, NULL, NULL, NULL, NULL, NULL
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};
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void
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dp_on (int flag)
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{
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if (!ON && flag) {
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SP = 0;
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MIT8K = 0;
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sim_activate_abs (&dp_unit, 0);
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sim_debug (DBG, &dp_dev, "Display on\n");
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} else if (ON && !flag) {
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sim_cancel (&dp_unit);
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sim_debug (DBG, &dp_dev, "Display off\n");
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crt_idle ();
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if (SYNC && HALT)
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flag_on (FLAG_SYNC);
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}
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ON = (uint16) flag;
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}
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uint16
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dp_is_on (void)
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{
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return ON;
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}
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static uint16
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dp_iot (uint16 insn, uint16 AC)
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{
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if ((insn & 0771) == 0001) { /* DLZ */
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sim_debug (DBG, &dp_dev, "DPC cleared\n");
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DPC = 0;
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}
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if ((insn & 0772) == 0002) { /* DLA */
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sim_debug (DBG, &dp_dev, "DPC set to %06o\n", AC & memmask);
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DPC = AC & memmask;
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BLOCK = (AC >> 12) & 3;
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}
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if ((insn & 0771) == 0011) { /* CTB */
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;
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}
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if ((insn & 0772) == 0012) { /* DOF */
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dp_on (0);
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}
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if ((insn & 0774) == 0304) { /* DCF */
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HALT = 0;
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}
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return AC;
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}
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static t_stat
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dp_opr(uint16 insn)
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{
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if ((insn & 04000) == 0) {
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sim_debug (DBG, &dp_dev, "DHLT ");
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HALT = 1;
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}
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else if (insn == 04000)
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sim_debug (DBG, &dp_dev, "DNOP");
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dp_on ((insn & 04000) != 0); /* DHLT */
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switch (insn & 00014) {
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case 000:
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if (insn & 1) {
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sim_debug (DBG, &dp_dev, "DADR ");
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MIT8K = !MIT8K;
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}
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break;
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case 004:
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sim_debug (DBG, &dp_dev, "DSTS%o ", insn & 3);
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SCALE = insn & 3;
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if (SCALE == 0)
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SCALE = 1;
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else
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SCALE *= 2;
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break;
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case 010:
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sim_debug (DBG, &dp_dev, "DSTB%o ", insn & 3);
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BLOCK = insn & 3;
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break;
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case 014:
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sim_debug (DBG, &dp_dev, "DSTL%o ", insn & 3);
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/* TODO: Light pen. */
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break;
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}
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if (insn & 00020) { /* DDSP */
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sim_debug (DBG, &dp_dev, "DDSP ");
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crt_point (XA, YA);
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}
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if (insn & 00040) { /* DRJM */
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sim_debug (DBG, &dp_dev, "DRJM ");
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if (SP > 0)
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DPC = DT[--SP];
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else
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sim_debug (DBG, &dp_dev, "stack underflow");
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}
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if (insn & 00100) { /* DDYM */
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sim_debug (DBG, &dp_dev, "DDYM ");
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YA -= 040;
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}
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if (insn & 00200) { /* DDXM */
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sim_debug (DBG, &dp_dev, "DDXM ");
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XA -= 040;
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}
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if (insn & 00400) { /* DIYM */
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sim_debug (DBG, &dp_dev, "DIYM ");
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YA += 040;
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}
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if (insn & 01000) { /* DIXM */
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sim_debug (DBG, &dp_dev, "DIXM ");
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XA += 040;
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}
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if (insn & 02000) { /* DHVC */
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sim_debug (DBG, &dp_dev, "DHVC ");
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crt_hvc ();
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}
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sim_debug (DBG, &dp_dev, "\n");
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return SCPE_OK;
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}
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static void
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jump (uint16 insn)
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{
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DPC = insn & 07777;
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if (MIT8K)
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DPC |= (insn & 0100000) >> 3;
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else
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DPC |= BLOCK << 12;
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}
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static void
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dp_sgr (uint16 insn)
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{
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sim_debug (DBG, &dp_dev, "DSGR %o\n", insn & 7);
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SGR = insn & 1;
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if (insn & 1) {
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sim_debug (DBG, &dp_dev, "Enter SGR mode\n");
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} else {
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sim_debug (DBG, &dp_dev, "Exit SGR mode\n");
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}
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if (insn & 2) {
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sim_debug (DBG, &dp_dev, "SGR: Return\n");
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}
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if (insn & 4) {
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sim_debug (DBG, &dp_dev, "SGR: Beam on\n");
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} else {
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sim_debug (DBG, &dp_dev, "SGR: Beam off\n");
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}
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}
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static void
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dp_opt (uint16 insn)
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{
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switch (insn & 07770) {
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case 07660: /* ASG-1 */
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case 07667:
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break;
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case 07720: /* VIC-1 */
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case 07730:
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break;
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case 07740: /* MCI-1 */
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case 07750:
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break;
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case 07760: /* STI-1 or LPA-1 */
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break;
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case 07770: /* SGR-1 */
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dp_sgr (insn);
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break;
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default:
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sim_debug (DBG, &dp_dev, "Unknown instruction: %06o ", insn);
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break;
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}
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}
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static void
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dp_inc_vector (uint16 byte)
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{
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uint16 x1 = XA, y1 = YA;
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uint16 dx, dy;
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if (byte == 0200) {
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sim_debug (DBG, &dp_dev, "P");
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} else {
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sim_debug (DBG, &dp_dev, "%s", byte & 0100 ? "B" : "D");
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if (byte & 00040)
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sim_debug (DBG, &dp_dev, "M");
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sim_debug (DBG, &dp_dev, "%o", (byte >> 3) & 3);
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if (byte & 00004)
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sim_debug (DBG, &dp_dev, "M");
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sim_debug (DBG, &dp_dev, "%o", byte & 3);
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}
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dx = SCALE * ((byte >> 3) & 3);
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dy = SCALE * (byte & 3);
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if (byte & 040)
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XA -= dx;
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else
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XA += dx;
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if (byte & 4)
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YA -= dy;
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else
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YA += dy;
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if (byte & 0100)
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crt_line (x1, y1, XA, YA);
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}
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static void
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dp_inc_escape (uint16 byte)
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{
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if (byte == 0100)
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sim_debug (DBG, &dp_dev, "T");
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else if (byte == 0140)
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sim_debug (DBG, &dp_dev, "X");
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else if (byte == 0151)
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sim_debug (DBG, &dp_dev, "R");
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else
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sim_debug (DBG, &dp_dev, "%03o", byte);
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if (byte & 0100)
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MODE = 0;
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if (byte & 040) {
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if (SP > 0)
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DPC = DT[--SP];
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else
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sim_debug (DBG, &dp_dev, "stack underflow");
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}
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if (byte & 020)
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XA += 040;
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if (byte & 010)
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XA &= 03740;
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if (byte & 4) /* Enter PPM mode. */
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;
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if (byte & 2)
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YA += 040;
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if (byte & 1)
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YA &= 03740;
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}
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static void
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dp_inc (uint16 byte)
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{
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if (byte & 0200) {
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/* Increment byte. */
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dp_inc_vector (byte);
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} else {
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/* Escape byte. */
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dp_inc_escape (byte);
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}
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}
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static void
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dp_deim (uint16 insn)
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{
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MODE = 1;
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sim_debug (DBG, &dp_dev, "E,");
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dp_inc (insn & 0377);
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sim_debug (DBG, &dp_dev, "\n");
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}
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static void
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dp_dlvh (uint16 insn1, uint16 insn2, uint16 insn3)
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{
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uint16 x1 = XA, y1 = YA;
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uint16 m, n, dx, dy;
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m = insn2 & 07777;
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n = insn3 & 07777;
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if (insn3 & 010000) {
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dx = n;
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dy = m;
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} else {
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dx = m;
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dy = n;
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}
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if (insn3 & 040000)
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XA -= SCALE * dx;
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else
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XA += SCALE * dx;
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if (insn3 & 020000)
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YA -= SCALE * dy;
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else
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YA += SCALE * dy;
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if (insn2 & 020000)
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crt_line (x1, y1, XA, YA);
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}
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static void
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dp_insn (uint16 insn)
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{
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switch ((insn >> 12) & 7) {
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case 0: /* DOPR */
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dp_opr (insn);
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break;
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case 1: /* DLXA */
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sim_debug (DBG, &dp_dev, "DLXA\n");
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XA = (insn & 01777) << 1;
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break;
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case 2: /* DLYA */
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sim_debug (DBG, &dp_dev, "DLYA\n");
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YA = (insn & 01777) << 1;
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break;
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case 3: /* DEIM */
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sim_debug (DBG, &dp_dev, "DEIM ");
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dp_deim (insn);
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break;
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case 4: /* DLVH */
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sim_debug (DBG, &dp_dev, "DLVH\n");
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dp_dlvh (insn, M[DPC], M[DPC+1]);
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DPC += 2;
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break;
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case 5: /* DJMS */
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sim_debug (DBG, &dp_dev, "DJMS\n");
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if (SP < 7)
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DT[SP++] = DPC;
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else
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sim_debug (DBG, &dp_dev, "stack overflow");
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jump (insn);
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break;
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case 6: /* DJMP */
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sim_debug (DBG, &dp_dev, "DJMP\n");
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jump (insn);
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break;
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case 7: /* optional */
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dp_opt (insn);
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break;
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}
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}
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static t_stat
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dp_svc(UNIT * uptr)
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{
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uint16 insn;
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if (sim_brk_summ && sim_brk_test(DPC, SWMASK('D'))) {
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sim_activate_abs (&dp_unit, 0);
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return sim_messagef (SCPE_STOP, "Display processor breakpoint.\n");
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}
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sim_debug (DBG, &dp_dev, "%06o ", DPC);
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insn = M[DPC];
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DPC++;
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if (MODE) {
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sim_debug (DBG, &dp_dev, "INC ");
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dp_inc (insn >> 8);
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if (MODE) {
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sim_debug (DBG, &dp_dev, ",");
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dp_inc (insn & 0377);
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}
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sim_debug (DBG, &dp_dev, "\n");
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} else
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dp_insn (insn);
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if (ON)
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sim_activate_after (&dp_unit, 2);
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return SCPE_OK;
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}
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static t_stat
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dp_reset(DEVICE * uptr)
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{
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sim_activate_abs (&dp_unit, 0);
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return SCPE_OK;
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}
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static t_stat
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sync_svc (UNIT *uptr)
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{
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sim_debug (DBG, &sync_dev, "40 Hz sync\n");
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SYNC = 1;
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if (SYNC && HALT)
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flag_on (FLAG_SYNC);
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sim_cancel (&sync_unit);
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return SCPE_OK;
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}
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static uint16
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sync_iot (uint16 insn, uint16 AC)
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{
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if ((insn & 0771) == 0071) { /* SCF */
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sim_debug (DBG, &sync_dev, "Clear flag\n");
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SYNC = 0;
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flag_off (FLAG_SYNC);
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sim_activate_after (&sync_unit, 25000);
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}
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if ((insn & 0772) == 0072) { /* IOS */
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}
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return AC;
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}
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