decbe5b76b
Project standard source code has tabs converted to spaces and CRLF line endings. Other text files have CRLF line endings.
180 lines
7.9 KiB
C
180 lines
7.9 KiB
C
/*************************************************************************
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* *
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* Copyright (c) 2022 Howard M. Harte. *
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* https://github.com/hharte *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining *
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* a copy of this software and associated documentation files (the *
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* "Software"), to deal in the Software without restriction, including *
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* without limitation the rights to use, copy, modify, merge, publish, *
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* distribute, sublicense, and/or sell copies of the Software, and to *
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* permit persons to whom the Software is furnished to do so, subject to *
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* the following conditions: *
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* *
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* The above copyright notice and this permission notice shall be *
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* included in all copies or substantial portions of the Software. *
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, *
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF *
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON- *
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* INFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE *
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN *
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN *
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE *
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* SOFTWARE. *
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* *
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* Except as contained in this notice, the names of The Authors shall *
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* not be used in advertising or otherwise to promote the sale, use or *
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* other dealings in this Software without prior written authorization *
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* from the Authors. *
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* *
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* Based on s100_64fdc.c *
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* *
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* Module Description: *
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* Tarbell Double-Density Floppy Controller module for SIMH. *
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* This module is a wrapper around the wd179x FDC module. *
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* *
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* Reference: *
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* http://www.bitsavers.org/pdf/tarbell/Tarbell_Double_Density_Floppy_Disk_Interface_Jul81.pdf
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* *
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*************************************************************************/
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#include "altairz80_defs.h"
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#include "sim_defs.h"
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#include "wd179x.h"
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#define DEV_NAME "TDD"
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/* Debug flags */
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#define STATUS_MSG (1 << 0)
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#define DRIVE_MSG (1 << 1)
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#define VERBOSE_MSG (1 << 2)
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#define IRQ_MSG (1 << 3)
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#define TDD_MAX_DRIVES 4
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#define TDD_IO_BASE 0x7C
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#define TDD_IO_SIZE 0x2
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#define TDD_IO_MASK (TDD_IO_SIZE - 1)
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typedef struct {
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PNP_INFO pnp; /* Plug and Play */
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} TDD_INFO;
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extern WD179X_INFO_PUB *wd179x_infop;
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static TDD_INFO tdd_info_data = { { 0x0000, 0, TDD_IO_BASE, TDD_IO_SIZE } };
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extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
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int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
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extern uint32 PCX; /* external view of PC */
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#define TDD_CAPACITY (77*1*26*128) /* Default SSSD 8" (IBM 3740) Disk Capacity */
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static t_stat tdd_reset(DEVICE *tdd_dev);
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static int32 tdd_control(const int32 port, const int32 io, const int32 data);
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static const char* tdd_description(DEVICE *dptr);
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#define TDD_FLAG_EOJ (1 << 7) /* End of Job (INTRQ) */
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static UNIT tdd_unit[] = {
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{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, TDD_CAPACITY) },
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{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, TDD_CAPACITY) },
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{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, TDD_CAPACITY) },
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{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, TDD_CAPACITY) }
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};
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static REG tdd_reg[] = {
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{ NULL }
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};
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#define TDD_NAME "Tarbell Double-Density FDC"
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static const char* tdd_description(DEVICE *dptr) {
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if (dptr == NULL) {
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return NULL;
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}
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return TDD_NAME;
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}
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static MTAB tdd_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE",
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&set_iobase, &show_iobase, NULL, "Sets disk controller I/O base address" },
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{ 0 }
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};
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/* Debug Flags */
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static DEBTAB tdd_dt[] = {
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{ "STATUS", STATUS_MSG, "Status messages" },
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{ "DRIVE", DRIVE_MSG, "Drive messages" },
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{ "VERBOSE", VERBOSE_MSG, "Verbose messages" },
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{ "IRQ", IRQ_MSG, "IRQ messages" },
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{ NULL, 0 }
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};
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DEVICE tdd_dev = {
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DEV_NAME, tdd_unit, tdd_reg, tdd_mod,
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TDD_MAX_DRIVES, 10, 31, 1, TDD_MAX_DRIVES, TDD_MAX_DRIVES,
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NULL, NULL, &tdd_reset,
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NULL, &wd179x_attach, &wd179x_detach,
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&tdd_info_data, (DEV_DISABLE | DEV_DIS | DEV_DEBUG), 0,
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tdd_dt, NULL, NULL, NULL, NULL, NULL, &tdd_description
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};
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/* Reset routine */
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static t_stat tdd_reset(DEVICE *dptr)
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{
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PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;
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if(dptr->flags & DEV_DIS) { /* Disconnect ROM and I/O Ports */
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/* Unmap I/O Ports */
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sim_map_resource(pnp->io_base, 1, RESOURCE_TYPE_IO, &tdd_control, "tdd_control", TRUE);
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} else {
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/* Connect TDD Disk Flags and Control Register */
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if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &tdd_control, "tdd_control", FALSE) != 0) {
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sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
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return SCPE_ARG;
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}
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}
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return SCPE_OK;
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}
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/* Tarbell pp. 12-5 Disk Control/Status */
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static int32 tdd_control(const int32 port, const int32 io, const int32 data)
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{
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int32 result = 0;
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if(io) { /* I/O Write */
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if ((port & TDD_IO_MASK) == 0) {
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wd179x_infop->fdc_head = (data & 0x40) >> 6;
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wd179x_infop->sel_drive = (data & 0x30) >> 4;
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wd179x_infop->ddens = (data & 0x08) >> 3;
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sim_debug(DRIVE_MSG, &tdd_dev, DEV_NAME ": " ADDRESS_FORMAT " WR CTRL(0x%02x) = 0x%02x: Drive: %d, Head: %d, %s-Density.\n",
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PCX, port,
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data & 0xFF,
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wd179x_infop->sel_drive,
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wd179x_infop->fdc_head,
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wd179x_infop->ddens == 1 ? "Double" : "Single");
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} else {
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sim_debug(STATUS_MSG, &tdd_dev, DEV_NAME ": " ADDRESS_FORMAT
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" Write Extended Address, Port 0x%02x=0x%02x\n", PCX, port, data);
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}
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} else { /* I/O Read */
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if ((port & TDD_IO_MASK) == 0) {
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result = (wd179x_infop->intrq) ? 0 : TDD_FLAG_EOJ;
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sim_debug(STATUS_MSG, &tdd_dev, DEV_NAME ": " ADDRESS_FORMAT
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" Read EOJ, Port 0x%02x Result 0x%02x\n", PCX, port, result);
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} else {
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result = (wd179x_infop->drq) ? TDD_FLAG_EOJ : 0;
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sim_debug(STATUS_MSG, &tdd_dev, DEV_NAME ": " ADDRESS_FORMAT
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" Read DRQ, Port 0x%02x Result 0x%02x\n", PCX, port, result);
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}
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}
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return result;
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}
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