276 lines
No EOL
12 KiB
C
276 lines
No EOL
12 KiB
C
/* sigma_io_defs.h: XDS Sigma I/O device simulator definitions
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Copyright (c) 2007-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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*/
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#ifndef SIGMA_IO_DEFS_H_
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#define SIGMA_IO_DEFS_H_ 0
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#include "sim_defs.h" /* simulator defns */
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#include "sigma_defs.h"
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/* Channel constants */
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#define CHAN_N_CHAN 8 /* max # channels */
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#define CHAN_DFLT 4 /* default # chan */
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#define CHAN_N_DEV 32 /* max dev per chan */
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#define CHAN_V_IOPT (DEV_V_UF + 0) /* channel type */
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#define CHAN_MIOP (0 << CHAN_V_IOPT)
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#define CHAN_SIOP (1 << CHAN_V_IOPT)
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/* I/O device definition block */
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typedef struct {
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uint32 dva; /* dev addr (chan+dev) */
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uint32 (*disp)(uint32 op, uint32 dva, uint32 *dvst);
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uint32 dio; /* dev addr (direct IO) */
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uint32 (*dio_disp)(uint32 op, uint32 rn, uint32 dva);
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} dib_t;
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/* Channel data structure */
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typedef struct {
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uint32 clc[CHAN_N_DEV]; /* location counter */
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uint32 ba[CHAN_N_DEV]; /* mem addr */
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uint16 bc[CHAN_N_DEV]; /* byte count */
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uint8 cmd[CHAN_N_DEV]; /* command */
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uint8 cmf[CHAN_N_DEV]; /* command flags */
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uint16 chf[CHAN_N_DEV]; /* channel flags */
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uint8 chi[CHAN_N_DEV]; /* interrupts */
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uint8 chsf[CHAN_N_DEV]; /* simulator flags */
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uint32 (*disp[CHAN_N_DEV])(uint32 op, uint32 dva, uint32 *dvst);
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} chan_t;
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/* Channel command words */
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#define CCW1_V_CMD 24 /* command */
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#define CCW1_M_CMD 0xFF
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#define CCW1_V_BA 0
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#define CCW1_M_BA ((cpu_tab[cpu_model].pamask << 2) | 0x3)
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#define CHBA_MASK (CCW1_M_BA << CCW1_V_BA)
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#define CCW2_V_CMF 24 /* cmd flags */
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#define CCW2_M_CMF 0xFF
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#define CCW2_V_BC 0
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#define CCW2_M_BC 0xFFFF
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#define CHBC_MASK (CCW2_M_BC << CCW2_V_BC)
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#define CCW1_GETCMD(x) (((x) >> CCW1_V_CMD) & CCW1_M_CMD)
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#define CCW1_GETBA(x) (((x) >> CCW1_V_BA) & CCW1_M_BA)
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#define CCW2_GETCMF(x) (((x) >> CCW2_V_CMF) & CCW2_M_CMF)
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#define CCW2_GETBC(x) (((x) >> CCW2_V_BC) & CCW2_M_BC)
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/* Channel commands */
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#define CMD_TIC 0x8 /* transfer */
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/* Channel command flags */
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#define CMF_DCH 0x80 /* data chain */
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#define CMF_IZC 0x40 /* int on zero cnt */
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#define CMF_CCH 0x20 /* command chain */
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#define CMF_ICE 0x10 /* int on chan end */
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#define CMF_HTE 0x08 /* hlt on xmit err */
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#define CMF_IUE 0x04 /* int on uend */
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#define CMF_SIL 0x02 /* suppress lnt err */
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#define CMF_SKP 0x01 /* skip */
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/* Channel flags */
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#define CHF_INP 0x8000 /* int pending */
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#define CHF_UEN 0x0400 /* unusual end */
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#define CHF_LNTE 0x0080 /* length error */
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#define CHF_XMDE 0x0040 /* xmit data error */
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#define CHF_XMME 0x0020 /* xmit mem error */
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#define CHF_XMAE 0x0010 /* xmit addr error */
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#define CHF_IOME 0x0008 /* IOP mem error */
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#define CHF_IOCE 0x0004 /* IOP ctrl error */
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#define CHF_IOHE 0x0002 /* IOP halted */
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#define CHF_ALL (CHF_INP|CHF_UEN|0xFF)
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/* Channel interrupts */
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#define CHI_F_SHF 1 /* flag shift */
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#define CHI_CTL (0x40 << CHI_F_SHF) /* ctl int (fake) */
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#define CHI_ZBC (0x20 << CHI_F_SHF) /* zero by cnt int */
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#define CHI_END (0x10 << CHI_F_SHF) /* channel end int */
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#define CHI_UEN (0x08 << CHI_F_SHF) /* unusual end int */
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#define CHI_FLAGS (CHI_ZBC|CHI_END|CHI_UEN)
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#define CHI_V_UN 0
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#define CHI_M_UN 0xF
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#define CHI_GETUN(x) (((x) >> CHI_V_UN) & CHI_M_UN)
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#define CHI_GETINT(x) (((x) & CHI_FLAGS) >> CHI_F_SHF)
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/* Internal simulator flags */
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#define CHSF_ACT 0x0001 /* channel active */
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#define CHSF_MU 0x0002 /* multi-unit dev */
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/* Dispatch routine status return value */
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#define DVT_V_UN 24 /* unit addr (AIO only) */
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#define DVT_M_UN 0xF
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#define DVT_V_CC 16 /* cond codes */
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#define DVT_M_CC 0xF
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#define DVT_V_DVS 0 /* device status */
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#define DVT_M_DVS 0xFF
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#define DVS_V_DST 5 /* device status */
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#define DVS_M_DST 0x3
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#define DVS_DST (DVS_M_DST << DVS_V_DST)
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#define DVS_DOFFL (0x1 << DVS_V_DST)
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#define DVS_DBUSY (0x3 << DVS_V_DST)
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#define DVS_AUTO 0x10 /* manual/automatic */
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#define DVS_V_CST 1 /* ctrl status */
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#define DVS_M_CST 0x3
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#define DVS_CBUSY (0x3 << DVS_V_CST)
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#define DVS_CST (DVS_M_CST << DVS_V_CST)
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#define DVT_GETUN(x) (((x) >> DVT_V_UN) & DVT_M_UN)
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#define DVT_GETCC(x) (((x) >> DVT_V_CC) & DVT_M_CC)
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#define DVT_GETDVS(x) (((x) >> DVT_V_DVS) & DVT_M_DVS)
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#define DVT_NOST (CC1 << DVT_V_CC) /* no status */
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#define DVT_NODEV ((CC1|CC2) < DVT_V_CC) /* no device */
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/* Read and write direct address format */
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#define DIO_V_MOD 12 /* mode */
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#define DIO_M_MOD 0xF
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#define DIO_V_0FNC 0 /* mode 0 func */
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#define DIO_M_0FNC 0xFFF
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#define DIO_V_1FNC 8 /* mode 1 int func */
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#define DIO_M_1FNC 0x7
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#define DIO_V_1GRP 0 /* int group */
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#define DIO_M_1GRP 0xF
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#define DIO_GETMOD(x) (((x) >> DIO_V_MOD) & DIO_M_MOD)
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#define DIO_GET0FNC(x) (((x) >> DIO_V_0FNC) & DIO_M_0FNC)
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#define DIO_GET1FNC(x) (((x) >> DIO_V_1FNC) & DIO_M_1FNC)
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#define DIO_GET1GRP(x) (((x) >> DIO_V_1GRP) & DIO_M_1GRP)
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#define DIO_N_MOD (DIO_M_MOD + 1) /* # DIO "modes" */
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/* I/O instruction address format */
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#define DVA_V_CHAN 8 /* channel */
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#define DVA_M_CHAN (CHAN_N_CHAN - 1)
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#define DVA_CHAN (DVA_M_CHAN << DVA_V_CHAN)
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#define DVA_V_DEVSU 0 /* dev, 1 unit */
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#define DVA_M_DEVSU 0x7F
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#define DVA_DEVSU (DVA_M_DEVSU << DVA_V_DEVSU)
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#define DVA_MU 0x80 /* multi-unit flg */
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#define DVA_V_DEVMU 4 /* dev, multi */
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#define DVA_M_DEVMU 0x7
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#define DVA_DEVMU (DVA_M_DEVMU << DVA_V_DEVMU)
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#define DVA_V_UNIT 0 /* unit number */
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#define DVA_M_UNIT 0xF
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#define DVA_GETCHAN(x) (((x) >> DVA_V_CHAN) & DVA_M_CHAN)
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#define DVA_GETDEV(x) (((x) & DVA_MU)? \
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(((x) >> DVA_V_DEVMU) & DVA_M_DEVMU): \
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(((x) >> DVA_V_DEVSU) & DVA_M_DEVSU))
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#define DVA_GETUNIT(x) (((x) & DVA_MU)? \
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(((x) >> DVA_V_UNIT) & DVA_M_UNIT): 0)
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/* Default I/O device addresses */
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#define DVA_TT 0x001
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#define DVA_LP 0x002
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#define DVA_CR 0x003
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#define DVA_CP 0x004
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#define DVA_PT 0x005
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#define DVA_MUX 0x006
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#define DIO_MUX 0x003
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#define DVA_MT 0x080
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#define DVA_RAD 0x180
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#define DVA_DK 0x190
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#define DVA_DPA 0x280
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#define DVA_DPB 0x380
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/* Channel routine status codes */
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#define CHS_ERR 0x4000 /* any error */
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#define CHS_INF 0x8000 /* information */
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#define CHS_IFERR(x) (((x) != 0) && ((x) < CHS_INF))
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#define CHS_INACTV (CHS_ERR + 0)
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#define CHS_NXM (CHS_ERR + 1)
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#define CHS_SEQ (CHS_ERR + 2)
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#define CHS_ZBC (CHS_INF + 1) /* zero byte count */
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#define CHS_CCH (CHS_INF + 2) /* command chain */
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/* Boot ROM */
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#define BOOT_SA 0x20
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#define BOOT_LNT 12
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#define BOOT_DEV 0x25
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#define BOOT_PC 0x26
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/* Internal real-time scheduler */
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#define RTC_C1 0
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#define RTC_C2 1
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#define RTC_C3 2
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#define RTC_C4 3
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#define RTC_NUM_CNTRS 4
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#define RTC_TTI (RTC_NUM_CNTRS + 0)
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#define RTC_COC (RTC_NUM_CNTRS + 1)
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#define RTC_ALARM (RTC_NUM_CNTRS + 2)
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#define RTC_NUM_EVNTS (RTC_NUM_CNTRS + 3)
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#define RTC_HZ_OFF 0
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#define RTC_HZ_500 1
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#define RTC_HZ_50 2
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#define RTC_HZ_60 3
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#define RTC_HZ_100 4
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#define RTC_HZ_2 5
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#define RTC_NUM_HZ 6
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/* Function prototypes */
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uint32 chan_get_cmd (uint32 dva, uint32 *cmd);
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uint32 chan_set_chf (uint32 dva, uint32 fl);
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t_bool chan_tst_cmf (uint32 dva, uint32 fl);
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void chan_set_chi (uint32 dva, uint32 fl);
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void chan_set_dvi (uint32 dva);
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int32 chan_clr_chi (uint32 dva);
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int32 chan_chk_chi (uint32 dva);
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uint32 chan_end (uint32 dva);
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uint32 chan_uen (uint32 dva);
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uint32 chan_RdMemB (uint32 dva, uint32 *dat);
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uint32 chan_WrMemB (uint32 dva, uint32 dat);
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uint32 chan_WrMemBR (uint32 dva, uint32 dat);
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uint32 chan_RdMemW (uint32 dva, uint32 *dat);
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uint32 chan_WrMemW (uint32 dva, uint32 dat);
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t_stat chan_reset_dev (uint32 dva);
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void io_sclr_req (uint32 inum, uint32 val);
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void io_sclr_arm (uint32 inum, uint32 val);
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t_stat io_set_dvc (UNIT* uptr, int32 val, CONST char *cptr, void *desc);
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t_stat io_show_dvc (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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t_stat io_set_dva (UNIT* uptr, int32 val, CONST char *cptr, void *desc);
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t_stat io_show_dva (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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t_stat io_show_cst (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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t_stat io_boot (int32 u, DEVICE *dptr);
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/* Internal real-time event scheduler */
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t_stat rtc_set_tps (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat rtc_show_tps (FILE *of, UNIT *uptr, int32 val, CONST void *desc);
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t_stat rtc_register (uint32 tm, uint32 idx, UNIT *uptr);
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#endif |