538 lines
24 KiB
C
538 lines
24 KiB
C
/* pdp11_rx.c: RX11/RX01 floppy disk simulator
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Copyright (c) 1993-2013, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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rx RX11/RX01 floppy disk
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23-Oct-13 RMS Revised for new boot setup routine
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03-Sep-13 RMS Added explicit void * cast
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07-Jul-05 RMS Removed extraneous externs
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12-Oct-02 RMS Added autoconfigure support
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08-Oct-02 RMS Added variable address support to bootstrap
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Added vector change/display support
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Revised state machine based on RX211
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New data structures
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Fixed reset of disabled device
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26-Jan-02 RMS Revised bootstrap to conform to M9312
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06-Jan-02 RMS Revised enable/disable support
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30-Nov-01 RMS Added read only unit, extended SET/SHOW support
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24-Nov-01 RMS Converted FLG to array
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07-Sep-01 RMS Revised device disable and interrupt mechanisms
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17-Jul-01 RMS Fixed warning from VC++ 6.0
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26-Apr-01 RMS Added device enable/disable support
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13-Apr-01 RMS Revised for register arrays
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15-Feb-01 RMS Corrected bootstrap string
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14-Apr-99 RMS Changed t_addr to unsigned
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An RX01 diskette consists of 77 tracks, each with 26 sectors of 128B.
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Tracks are numbered 0-76, sectors 1-26.
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*/
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#include "pdp11_defs.h"
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#define RX_NUMTR 77 /* tracks/disk */
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#define RX_M_TRACK 0377
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#define RX_NUMSC 26 /* sectors/track */
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#define RX_M_SECTOR 0177
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#define RX_NUMBY 128 /* bytes/sector */
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#define RX_SIZE (RX_NUMTR * RX_NUMSC * RX_NUMBY) /* bytes/disk */
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#define RX_NUMDR 2 /* drives/controller */
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#define RX_M_NUMDR 01
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#define UNIT_V_WLK (UNIT_V_UF) /* write locked */
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#define UNIT_WLK (1u << UNIT_V_UF)
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#define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write protect */
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#define IDLE 0 /* idle state */
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#define RWDS 1 /* rw, sect next */
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#define RWDT 2 /* rw, track next */
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#define RWXFR 3 /* rw, transfer */
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#define FILL 4 /* fill buffer */
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#define EMPTY 5 /* empty buffer */
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#define CMD_COMPLETE 6 /* set done next */
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#define INIT_COMPLETE 7 /* init compl next */
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#define RXCS_V_FUNC 1 /* function */
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#define RXCS_M_FUNC 7
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#define RXCS_FILL 0 /* fill buffer */
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#define RXCS_EMPTY 1 /* empty buffer */
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#define RXCS_WRITE 2 /* write sector */
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#define RXCS_READ 3 /* read sector */
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#define RXCS_RXES 5 /* read status */
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#define RXCS_WRDEL 6 /* write del data */
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#define RXCS_ECODE 7 /* read error code */
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#define RXCS_V_DRV 4 /* drive select */
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#define RXCS_V_DONE 5 /* done */
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#define RXCS_V_IE 6 /* intr enable */
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#define RXCS_V_TR 7 /* xfer request */
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#define RXCS_V_INIT 14 /* init */
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#define RXCS_V_ERR 15 /* error */
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#define RXCS_FUNC (RXCS_M_FUNC << RXCS_V_FUNC)
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#define RXCS_DRV (1u << RXCS_V_DRV)
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#define RXCS_DONE (1u << RXCS_V_DONE)
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#define RXCS_IE (1u << RXCS_V_IE)
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#define RXCS_TR (1u << RXCS_V_TR)
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#define RXCS_INIT (1u << RXCS_V_INIT)
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#define RXCS_ERR (1u << RXCS_V_ERR)
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#define RXCS_ROUT (RXCS_ERR+RXCS_TR+RXCS_IE+RXCS_DONE)
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#define RXCS_IMP (RXCS_ROUT+RXCS_DRV+RXCS_FUNC)
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#define RXCS_RW (RXCS_IE) /* read/write */
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#define RXCS_GETFNC(x) (((x) >> RXCS_V_FUNC) & RXCS_M_FUNC)
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#define RXES_CRC 0001 /* CRC error */
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#define RXES_PAR 0002 /* parity error */
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#define RXES_ID 0004 /* init done */
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#define RXES_WLK 0010 /* write protect */
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#define RXES_DD 0100 /* deleted data */
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#define RXES_DRDY 0200 /* drive ready */
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#define TRACK u3 /* current track */
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#define CALC_DA(t,s) (((t) * RX_NUMSC) + ((s) - 1)) * RX_NUMBY
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extern int32 int_req[IPL_HLVL];
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int32 rx_csr = 0; /* control/status */
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int32 rx_dbr = 0; /* data buffer */
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int32 rx_esr = 0; /* error status */
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int32 rx_ecode = 0; /* error code */
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int32 rx_track = 0; /* desired track */
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int32 rx_sector = 0; /* desired sector */
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int32 rx_state = IDLE; /* controller state */
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int32 rx_stopioe = 1; /* stop on error */
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int32 rx_cwait = 100; /* command time */
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int32 rx_swait = 10; /* seek, per track */
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int32 rx_xwait = 1; /* tr set time */
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uint8 rx_buf[RX_NUMBY] = { 0 }; /* sector buffer */
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int32 rx_bptr = 0; /* buffer pointer */
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int32 rx_enb = 1; /* device enable */
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DEVICE rx_dev;
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t_stat rx_rd (int32 *data, int32 PA, int32 access);
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t_stat rx_wr (int32 data, int32 PA, int32 access);
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t_stat rx_svc (UNIT *uptr);
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t_stat rx_reset (DEVICE *dptr);
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t_stat rx_boot (int32 unitno, DEVICE *dptr);
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void rx_done (int32 esr_flags, int32 new_ecode);
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/* RX11 data structures
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rx_dev RX device descriptor
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rx_unit RX unit list
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rx_reg RX register list
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rx_mod RX modifier list
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*/
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#define IOLN_RX 004
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DIB rx_dib = {
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IOBA_AUTO, IOLN_RX, &rx_rd, &rx_wr,
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1, IVCL (RX), VEC_AUTO, { NULL }, IOLN_RX,
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};
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UNIT rx_unit[] = {
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{ UDATA (&rx_svc,
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UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, RX_SIZE) },
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{ UDATA (&rx_svc,
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UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, RX_SIZE) }
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};
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REG rx_reg[] = {
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{ ORDATA (RXCS, rx_csr, 16) },
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{ ORDATA (RXDB, rx_dbr, 8) },
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{ ORDATA (RXES, rx_esr, 8) },
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{ ORDATA (RXERR, rx_ecode, 8) },
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{ ORDATA (RXTA, rx_track, 8) },
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{ ORDATA (RXSA, rx_sector, 8) },
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{ DRDATA (STAPTR, rx_state, 3), REG_RO },
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{ DRDATA (BUFPTR, rx_bptr, 7) },
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{ FLDATA (INT, IREQ (RX), INT_V_RX) },
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{ FLDATA (ERR, rx_csr, RXCS_V_ERR) },
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{ FLDATA (TR, rx_csr, RXCS_V_TR) },
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{ FLDATA (IE, rx_csr, RXCS_V_IE) },
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{ FLDATA (DONE, rx_csr, RXCS_V_DONE) },
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{ DRDATA (CTIME, rx_cwait, 24), PV_LEFT },
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{ DRDATA (STIME, rx_swait, 24), PV_LEFT },
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{ DRDATA (XTIME, rx_xwait, 24), PV_LEFT },
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{ FLDATA (STOP_IOE, rx_stopioe, 0) },
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{ BRDATA (SBUF, rx_buf, 8, 8, RX_NUMBY) },
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{ ORDATA (DEVADDR, rx_dib.ba, 32), REG_HRO },
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{ ORDATA (DEVVEC, rx_dib.vec, 16), REG_HRO },
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{ NULL }
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};
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MTAB rx_mod[] = {
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{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
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{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
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#if defined (VM_PDP11)
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{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 004, "ADDRESS", "ADDRESS",
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&set_addr, &show_addr, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, NULL, "AUTOCONFIGURE",
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&set_addr_flt, NULL, NULL },
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{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "VECTOR", "VECTOR",
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&set_vec, &show_vec, NULL },
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#else
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{ MTAB_XTD|MTAB_VDV, 004, "ADDRESS", "ADDRESS",
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NULL, &show_addr, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
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NULL, &show_vec, NULL },
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#endif
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{ 0 }
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};
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DEVICE rx_dev = {
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"RX", rx_unit, rx_reg, rx_mod,
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RX_NUMDR, 8, 20, 1, 8, 8,
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NULL, NULL, &rx_reset,
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&rx_boot, NULL, NULL,
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&rx_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS
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};
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/* I/O dispatch routine, I/O addresses 17777170 - 17777172
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17777170 floppy CSR
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17777172 floppy data register
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*/
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t_stat rx_rd (int32 *data, int32 PA, int32 access)
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{
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switch ((PA >> 1) & 1) { /* decode PA<1> */
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case 0: /* RXCS */
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rx_csr = rx_csr & RXCS_IMP; /* clear junk */
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*data = rx_csr & RXCS_ROUT;
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break;
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case 1: /* RXDB */
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if ((rx_state == EMPTY) && (rx_csr & RXCS_TR)) {/* empty? */
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sim_activate (&rx_unit[0], rx_xwait);
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rx_csr = rx_csr & ~RXCS_TR; /* clear xfer */
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}
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*data = rx_dbr; /* return data */
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break;
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} /* end switch PA */
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return SCPE_OK;
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}
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t_stat rx_wr (int32 data, int32 PA, int32 access)
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{
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int32 drv;
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switch ((PA >> 1) & 1) { /* decode PA<1> */
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/* Writing RXCS, three cases:
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1. Writing INIT, reset device
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2. Idle and writing new function
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- clear error, done, transfer ready, int req
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- save int enable, function, drive
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- start new function
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3. Otherwise, write IE and update interrupts
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*/
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case 0: /* RXCS */
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rx_csr = rx_csr & RXCS_IMP; /* clear junk */
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if (access == WRITEB) data = (PA & 1)? /* write byte? */
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(rx_csr & 0377) | (data << 8): (rx_csr & ~0377) | data;
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if (data & RXCS_INIT) { /* initialize? */
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rx_reset (&rx_dev); /* reset device */
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return SCPE_OK; /* end if init */
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}
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if ((data & CSR_GO) && (rx_state == IDLE)) { /* new function? */
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rx_csr = data & (RXCS_IE + RXCS_DRV + RXCS_FUNC);
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drv = ((rx_csr & RXCS_DRV)? 1: 0); /* reselect drive */
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rx_bptr = 0; /* clear buf pointer */
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switch (RXCS_GETFNC (data)) { /* case on func */
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case RXCS_FILL:
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rx_state = FILL; /* state = fill */
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rx_csr = rx_csr | RXCS_TR; /* xfer is ready */
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break;
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case RXCS_EMPTY:
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rx_state = EMPTY; /* state = empty */
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sim_activate (&rx_unit[drv], rx_xwait);
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break;
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case RXCS_READ: case RXCS_WRITE: case RXCS_WRDEL:
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rx_state = RWDS; /* state = get sector */
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rx_csr = rx_csr | RXCS_TR; /* xfer is ready */
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rx_esr = rx_esr & RXES_ID; /* clear errors */
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break;
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default:
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rx_state = CMD_COMPLETE; /* state = cmd compl */
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sim_activate (&rx_unit[drv], rx_cwait);
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break;
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} /* end switch func */
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return SCPE_OK;
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} /* end if GO */
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if ((data & RXCS_IE) == 0)
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CLR_INT (RX);
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else if ((rx_csr & (RXCS_DONE + RXCS_IE)) == RXCS_DONE)
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SET_INT (RX);
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rx_csr = (rx_csr & ~RXCS_RW) | (data & RXCS_RW);
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break; /* end case RXCS */
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/* Accessing RXDB, two cases:
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1. Write idle, write
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2. Write not idle and TR set, state dependent
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*/
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case 1: /* RXDB */
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if ((PA & 1) || ((rx_state != IDLE) && ((rx_csr & RXCS_TR) == 0)))
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return SCPE_OK; /* if ~IDLE, need tr */
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rx_dbr = data & 0377; /* save data */
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if ((rx_state != IDLE) && (rx_state != EMPTY)) {
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drv = ((rx_csr & RXCS_DRV)? 1: 0); /* select drive */
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sim_activate (&rx_unit[drv], rx_xwait); /* sched event */
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rx_csr = rx_csr & ~RXCS_TR; /* clear xfer */
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}
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break; /* end case RXDB */
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} /* end switch PA */
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return SCPE_OK;
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}
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/* Unit service; the action to be taken depends on the transfer state:
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IDLE Should never get here
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RWDS Save sector, set TR, set RWDT
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RWDT Save track, set RWXFR
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RWXFR Read/write buffer
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FILL copy ir to rx_buf[rx_bptr], advance ptr
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if rx_bptr > max, finish command, else set tr
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EMPTY if rx_bptr > max, finish command, else
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copy rx_buf[rx_bptr] to ir, advance ptr, set tr
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CMD_COMPLETE copy requested data to ir, finish command
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INIT_COMPLETE read drive 0, track 1, sector 1 to buffer, finish command
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For RWDT and CMD_COMPLETE, the input argument is the selected drive;
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otherwise, it is drive 0.
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*/
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t_stat rx_svc (UNIT *uptr)
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{
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int32 i, func;
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uint32 da;
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int8 *fbuf = (int8 *) uptr->filebuf;
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func = RXCS_GETFNC (rx_csr); /* get function */
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switch (rx_state) { /* case on state */
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case IDLE: /* idle */
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return SCPE_IERR; /* done */
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case EMPTY: /* empty buffer */
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if (rx_bptr >= RX_NUMBY) /* done all? */
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rx_done (0, 0);
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else {
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rx_dbr = rx_buf[rx_bptr]; /* get next */
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rx_bptr = rx_bptr + 1;
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rx_csr = rx_csr | RXCS_TR; /* set xfer */
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}
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break;
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case FILL: /* fill buffer */
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rx_buf[rx_bptr] = (uint8)rx_dbr; /* write next */
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rx_bptr = rx_bptr + 1;
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if (rx_bptr < RX_NUMBY) /* more? set xfer */
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rx_csr = rx_csr | RXCS_TR;
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else rx_done (0, 0); /* else done */
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break;
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case RWDS: /* wait for sector */
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rx_sector = rx_dbr & RX_M_SECTOR; /* save sector */
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rx_csr = rx_csr | RXCS_TR; /* set xfer */
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rx_state = RWDT; /* advance state */
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return SCPE_OK;
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case RWDT: /* wait for track */
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rx_track = rx_dbr & RX_M_TRACK; /* save track */
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rx_state = RWXFR;
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sim_activate (uptr, /* sched done */
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rx_swait * abs (rx_track - uptr->TRACK));
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return SCPE_OK;
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case RWXFR:
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if ((uptr->flags & UNIT_BUF) == 0) { /* not buffered? */
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rx_done (0, 0110); /* done, error */
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return IORETURN (rx_stopioe, SCPE_UNATT);
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}
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if (rx_track >= RX_NUMTR) { /* bad track? */
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rx_done (0, 0040); /* done, error */
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break;
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}
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uptr->TRACK = rx_track; /* now on track */
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if ((rx_sector == 0) || (rx_sector > RX_NUMSC)) { /* bad sect? */
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rx_done (0, 0070); /* done, error */
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break;
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}
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da = CALC_DA (rx_track, rx_sector); /* get disk address */
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if (func == RXCS_WRDEL) /* del data? */
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rx_esr = rx_esr | RXES_DD;
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if (func == RXCS_READ) { /* read? */
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for (i = 0; i < RX_NUMBY; i++)
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rx_buf[i] = fbuf[da + i];
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}
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else {
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if (uptr->flags & UNIT_WPRT) { /* write and locked? */
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rx_done (RXES_WLK, 0100); /* done, error */
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break;
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}
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for (i = 0; i < RX_NUMBY; i++) /* write */
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fbuf[da + i] = rx_buf[i];
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da = da + RX_NUMBY;
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if (da > uptr->hwmark)
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uptr->hwmark = da;
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}
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rx_done (0, 0); /* done */
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break;
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case CMD_COMPLETE: /* command complete */
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if (func == RXCS_ECODE) { /* read ecode? */
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rx_dbr = rx_ecode; /* set dbr */
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rx_done (0, -1); /* don't update */
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}
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else rx_done (0, 0);
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break;
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case INIT_COMPLETE: /* init complete */
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rx_unit[0].TRACK = 1; /* drive 0 to trk 1 */
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rx_unit[1].TRACK = 0; /* drive 1 to trk 0 */
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if ((rx_unit[0].flags & UNIT_BUF) == 0) { /* not buffered? */
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rx_done (RXES_ID, 0010); /* init done, error */
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break;
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}
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da = CALC_DA (1, 1); /* track 1, sector 1 */
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for (i = 0; i < RX_NUMBY; i++) /* read sector */
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rx_buf[i] = fbuf[da + i];
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rx_done (RXES_ID, 0); /* set done */
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if ((rx_unit[1].flags & UNIT_ATT) == 0)
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rx_ecode = 0020;
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break;
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} /* end case state */
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return SCPE_OK;
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}
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/* Command complete. Set done and put final value in interface register,
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request interrupt if needed, return to IDLE state.
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*/
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void rx_done (int32 esr_flags, int32 new_ecode)
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{
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int32 drv = (rx_csr & RXCS_DRV)? 1: 0;
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|
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rx_state = IDLE; /* now idle */
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rx_csr = rx_csr | RXCS_DONE; /* set done */
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if (rx_csr & RXCS_IE) SET_INT (RX); /* if ie, intr */
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rx_esr = (rx_esr | esr_flags) & ~RXES_DRDY;
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if (rx_unit[drv].flags & UNIT_ATT)
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rx_esr = rx_esr | RXES_DRDY;
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if (new_ecode > 0) /* test for error */
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rx_csr = rx_csr | RXCS_ERR;
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if (new_ecode < 0) /* don't update? */
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return;
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rx_ecode = new_ecode; /* update ecode */
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rx_dbr = rx_esr; /* update RXDB */
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return;
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}
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|
|
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/* Device initialization. The RX is one of the few devices that schedules
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an I/O transfer as part of its initialization.
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*/
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|
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t_stat rx_reset (DEVICE *dptr)
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|
{
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|
rx_csr = rx_dbr = 0; /* clear regs */
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rx_esr = rx_ecode = 0; /* clear error */
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rx_track = rx_sector = 0; /* clear addr */
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rx_state = IDLE; /* ctrl idle */
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|
CLR_INT (RX); /* clear int req */
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|
sim_cancel (&rx_unit[1]); /* cancel drive 1 */
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|
if (dptr->flags & DEV_DIS) /* disabled? */
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|
sim_cancel (&rx_unit[0]);
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|
else if (rx_unit[0].flags & UNIT_BUF) { /* attached? */
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rx_state = INIT_COMPLETE; /* yes, sched init */
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sim_activate (&rx_unit[0], rx_swait * abs (1 - rx_unit[0].TRACK));
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}
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else rx_done (0, 0010); /* no, error */
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|
return auto_config (0, 0); /* run autoconfig */
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|
}
|
|
|
|
/* Device bootstrap */
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|
|
|
#define BOOT_START 02000 /* start */
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|
#define BOOT_ENTRY (BOOT_START + 002) /* entry */
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|
#define BOOT_UNIT (BOOT_START + 010) /* unit number */
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|
#define BOOT_CSR (BOOT_START + 026) /* CSR */
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|
#define BOOT_LEN (sizeof (boot_rom) / sizeof (int16))
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|
|
|
static const uint16 boot_rom[] = {
|
|
042130, /* "XD" */
|
|
0012706, BOOT_START, /* MOV #boot_start, SP */
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|
0012700, 0000000, /* MOV #unit, R0 ; unit number */
|
|
0010003, /* MOV R0, R3 */
|
|
0006303, /* ASL R3 */
|
|
0006303, /* ASL R3 */
|
|
0006303, /* ASL R3 */
|
|
0006303, /* ASL R3 */
|
|
0012701, 0177170, /* MOV #RXCS, R1 ; csr */
|
|
0032711, 0000040, /* BITB #40, (R1) ; ready? */
|
|
0001775, /* BEQ .-4 */
|
|
0052703, 0000007, /* BIS #READ+GO, R3 */
|
|
0010311, /* MOV R3, (R1) ; read & go */
|
|
0105711, /* TSTB (R1) ; xfr ready? */
|
|
0100376, /* BPL .-2 */
|
|
0012761, 0000001, 0000002, /* MOV #1, 2(R1) ; sector */
|
|
0105711, /* TSTB (R1) ; xfr ready? */
|
|
0100376, /* BPL .-2 */
|
|
0012761, 0000001, 0000002, /* MOV #1, 2(R1) ; track */
|
|
0005003, /* CLR R3 */
|
|
0032711, 0000040, /* BITB #40, (R1) ; ready? */
|
|
0001775, /* BEQ .-4 */
|
|
0012711, 0000003, /* MOV #EMPTY+GO, (R1) ; empty & go */
|
|
0105711, /* TSTB (R1) ; xfr, done? */
|
|
0001776, /* BEQ .-2 */
|
|
0100003, /* BPL .+010 */
|
|
0116123, 0000002, /* MOVB 2(R1), (R3)+ ; move byte */
|
|
0000772, /* BR .-012 */
|
|
0005002, /* CLR R2 */
|
|
0005003, /* CLR R3 */
|
|
0012704, BOOT_START+020, /* MOV #START+20, R4 */
|
|
0005005, /* CLR R5 */
|
|
0005007 /* CLR R7 */
|
|
};
|
|
|
|
t_stat rx_boot (int32 unitno, DEVICE *dptr)
|
|
{
|
|
size_t i;
|
|
extern uint16 *M;
|
|
|
|
for (i = 0; i < BOOT_LEN; i++)
|
|
M[(BOOT_START >> 1) + i] = boot_rom[i];
|
|
M[BOOT_UNIT >> 1] = unitno & RX_M_NUMDR;
|
|
M[BOOT_CSR >> 1] = rx_dib.ba & DMASK;
|
|
cpu_set_boot (BOOT_ENTRY);
|
|
return SCPE_OK;
|
|
}
|