1299 lines
50 KiB
C
1299 lines
50 KiB
C
/* kx10_dt.c: 18b DECtape simulator
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Copyright (c) 2017-2020 Richard Cornwell based on work by Bob Supnik
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Based on PDP18B/pdp18b_dt.c by:
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Copyright (c) 1993-2017, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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RICHARD CORNWELL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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Except as contained in this notice, the name of Richard Cornwell shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Richard Cornwell.
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dt (PDP-4, PDP-7) Type 550/555 DECtape
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(PDP-9) TC02/TU55 DECtape
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(PDP-15) TC15/TU56 DECtape
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18b DECtapes are represented in memory by fixed length buffer of 32b words.
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Three file formats are supported:
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18b/36b 256 words per block [256 x 18b]
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16b 256 words per block [256 x 16b]
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12b 129 words per block [129 x 12b]
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When a 16b or 12b DECtape file is read in, it is converted to 18b/36b format.
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DECtape motion is measured in 3b lines. Time between lines is 33.33us.
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Tape density is nominally 300 lines per inch. The format of a DECtape (as
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taken from the PDP-7 formatter) is:
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reverse end zone 7144 reverse end zone codes ~ 12 feet
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reverse buffer 200 interblock codes
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block 0
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:
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block n
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forward buffer 200 interblock codes
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forward end zone 7144 forward end zone codes ~ 12 feet
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A block consists of five 18b header words, a tape-specific number of data
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words, and five 18b trailer words. All systems except the PDP-8 use a
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standard block length of 256 words; the PDP-8 uses a standard block length
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of 86 words (x 18b = 129 words x 12b). PDP-4/7 DECtapes came in two
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formats. The first 5 controllers used a 4 word header/trailer (missing
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word 0/4). All later serial numbers used the standard header. The later,
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standard header/trailer is simulated here.
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Because a DECtape file only contains data, the simulator cannot support
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write timing and mark track and can only do a limited implementation
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of read all and write all. Read all assumes that the tape has been
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conventionally written forward:
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header word 0 0
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header word 1 block number (for forward reads)
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header words 2,3 0
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header word 4 checksum (for reverse reads)
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:
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trailer word 4 checksum (for forward reads)
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trailer words 3,2 0
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trailer word 1 block number (for reverse reads)
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trailer word 0 0
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Write all writes only the data words and dumps the interblock words in the
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bit bucket.
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*/
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#include "kx10_defs.h"
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#ifndef NUM_DEVS_DT
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#define NUM_DEVS_DT 0
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#endif
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#if (NUM_DEVS_DT > 0)
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#define DT_DEVNUM 0320
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#define DT_NUMDR 8 /* #drives */
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#define UNIT_V_WLK (UNIT_V_UF + 0) /* write locked */
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#define UNIT_V_8FMT (UNIT_V_UF + 1) /* 12b format */
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#define UNIT_V_11FMT (UNIT_V_UF + 2) /* 16b format */
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#define UNIT_WLK (1 << UNIT_V_WLK)
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#define UNIT_8FMT (1 << UNIT_V_8FMT)
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#define UNIT_11FMT (1 << UNIT_V_11FMT)
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#define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write protect */
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/* System independent DECtape constants */
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#define DT_LPERMC 6 /* lines per mark track */
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#define DT_BLKWD 1 /* blk no word in h/t */
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#define DT_CSMWD 4 /* checksum word in h/t */
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#define DT_HTWRD 5 /* header/trailer words */
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#define DT_EZLIN (8192 * DT_LPERMC) /* end zone length */
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#define DT_BFLIN (200 * DT_LPERMC) /* buffer length */
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#define DT_BLKLN (DT_BLKWD * DT_LPERMC) /* blk no line in h/t */
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#define DT_CSMLN (DT_CSMWD * DT_LPERMC) /* csum line in h/t */
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#define DT_HTLIN (DT_HTWRD * DT_LPERMC) /* header/trailer lines */
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/* 16b, 18b, 36b DECtape constants */
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#define D18_WSIZE 6 /* word size in lines */
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#define D18_BSIZE 256 /* block size in 18b */
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#define D18_TSIZE 578 /* tape size */
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#define D18_LPERB (DT_HTLIN + (D18_BSIZE * DT_WSIZE) + DT_HTLIN)
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#define D18_FWDEZ (DT_EZLIN + (D18_LPERB * D18_TSIZE))
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#define D18_CAPAC (D18_TSIZE * D18_BSIZE) /* tape capacity */
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#define D11_FILSIZ (D18_CAPAC * sizeof (int16))
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/* 12b DECtape constants */
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#define D8_WSIZE 4 /* word size in lines */
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#define D8_BSIZE 86 /* block size in 18b */
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#define D8_TSIZE 1474 /* tape size */
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#define D8_LPERB (DT_HTLIN + (D8_BSIZE * DT_WSIZE) + DT_HTLIN)
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#define D8_FWDEZ (DT_EZLIN + (D8_LPERB * D8_TSIZE))
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#define D8_CAPAC (D8_TSIZE * D8_BSIZE) /* tape capacity */
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#define D8_NBSIZE ((D8_BSIZE * D18_WSIZE) / D8_WSIZE)
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#define D8_FILSIZ (D8_NBSIZE * D8_TSIZE * sizeof (int16))
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/* This controller */
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#define DT_CAPAC D18_CAPAC /* default */
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#define DT_WSIZE D18_WSIZE
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/* Calculated constants, per unit */
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#define DTU_BSIZE(u) (((u)->flags & UNIT_8FMT)? D8_BSIZE: D18_BSIZE)
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#define DTU_TSIZE(u) (((u)->flags & UNIT_8FMT)? D8_TSIZE: D18_TSIZE)
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#define DTU_LPERB(u) (((u)->flags & UNIT_8FMT)? D8_LPERB: D18_LPERB)
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#define DTU_FWDEZ(u) (((u)->flags & UNIT_8FMT)? D8_FWDEZ: D18_FWDEZ)
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#define DTU_CAPAC(u) (((u)->flags & UNIT_8FMT)? D8_CAPAC: D18_CAPAC)
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#define DT_LIN2BL(p,u) (((p) - DT_EZLIN) / DTU_LPERB (u))
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#define DT_LIN2OF(p,u) (((p) - DT_EZLIN) % DTU_LPERB (u))
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#define DT_LIN2WD(p,u) ((DT_LIN2OF (p,u) - DT_HTLIN) / DT_WSIZE)
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#define DT_BLK2LN(p,u) (((p) * DTU_LPERB (u)) + DT_EZLIN)
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#define DT_QREZ(u) (((u)->pos) < DT_EZLIN)
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#define DT_QFEZ(u) (((u)->pos) >= ((uint32) DTU_FWDEZ (u)))
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#define DT_QEZ(u) (DT_QREZ (u) || DT_QFEZ (u))
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/* Status register A */
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#define DTC_FLAG_PIA 07 /* PI Channel */
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#define DTC_DATA_PIA 070 /* PI Channel */
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#define DTC_V_FNC 6
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#define DTC_M_FNC 07
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#define FNC_MOVE 00 /* move */
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#define FNC_RALL 01 /* read all */
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#define FNC_SRCH 02 /* search */
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#define FNC_READ 03 /* read */
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#define FNC_WMRK 04 /* write timing */
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#define FNC_WALL 05 /* write All */
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#define FNC_WBLK 06 /* Write Block */
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#define FNC_WRIT 07 /* write data */
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#define DTC_V_UNIT 9 /* unit select */
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#define DTC_M_UNIT 07
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#define DTC_DESEL 0010000 /* Deslect all units */
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#define DTC_SEL 0020000 /* Select unit */
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#define DTC_NODELAY 0040000 /* Don't delay */
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#define DTC_RVDRV 0100000 /* Move unit reverse */
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#define DTC_FWDRV 0200000 /* Move unit forward */
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#define DTC_STSTOP 0400000 /* Stop unit */
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#define CMD u3
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/* Flags in lower bits of u3 */
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#define DTC_FNC_STOP 001 /* Unit stopping */
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#define DTC_FNC_START 002 /* Start unit motion */
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#define DTC_FNC_REV 004 /* Unit to change direction */
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/* CONO Unit +4 bit */
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#define DTS_FUNC_STOP 0000001
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#define DTS_STOP_ALL 0000002
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#define DTS_BLK_MISS 0010000
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#define DTS_END_ZONE 0020000
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#define DTS_ILL_OP 0040000
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#define DTS_JOB_DONE 0100000
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#define DTS_DATA_MISS 0200000
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#define DTS_PAR_ERR 0400000
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#define DTC_GETFNC(x) (((x) >> DTC_V_FNC) & DTC_M_FNC)
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#define DTC_GETUNI(x) (((x) >> DTC_V_UNIT) & DTC_M_UNIT)
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/* Status register B */
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#define DTB_PARENB 0400000000000LL /* Parity Error Enable */
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#define DTB_TIMENB 0200000000000LL /* Data missed Enable */
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#define DTB_JOBENB 0100000000000LL /* Job done Enable */
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#define DTB_ILLENB 0040000000000LL /* Illegal Operation Enable */
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#define DTB_ENDENB 0020000000000LL /* End Zone Enable */
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#define DTB_MISENB 0010000000000LL /* Block Missed Enable */
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#define DTB_DLY 0004000000000LL /* Delay in progress */
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#define DTB_ACT 0002000000000LL /* Active */
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#define DTB_SPD 0001000000000LL /* Controller up to speed */
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#define DTB_BLK 0000400000000LL /* Block number */
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#define DTB_REV 0000200000000LL /* Reverse Check */
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#define DTB_DAT 0000100000000LL /* Data */
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#define DTB_FIN 0000040000000LL /* Final */
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#define DTB_CHK 0000020000000LL /* Checksum */
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#define DTB_IDL 0000010000000LL /* Idle */
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#define DTB_BLKRD 0000004000000LL /* Block Number Read */
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#define DTB_STOP 0000001000000LL /* Function Stop */
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#define DTB_PAR 0000000400000LL /* Parity Error */
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#define DTB_MIS 0000000200000LL /* Data Missed */
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#define DTB_DONE 0000000100000LL /* Job Done */
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#define DTB_ILL 0000000040000LL /* Illegal operation */
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#define DTB_END 0000000020000LL /* End Zone */
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#define DTB_BLKMIS 0000000010000LL /* Block Missed */
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#define DTB_WRLK 0000000004000LL /* Write Lock */
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#define DTB_WRMK 0000000002000LL /* Write Mark Switch */
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#define DTB_INCBLK 0000000001000LL /* Incomplete Block */
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#define DTB_MRKERR 0000000000200LL /* Mark Track Error */
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#define DTB_SELERR 0000000000100LL /* Select error */
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#define DTB_FLGREQ 0000000000002LL /* Flag Request */
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#define DTB_DATREQ 0000000000001LL /* Data Request */
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#define DSTATE u5 /* Dectape current state */
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/* Current Dectape state in u5 */
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#define DTC_FEND 0 /* Tape in endzone */
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#define DTC_FBLK 1 /* In forward block number */
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#define DTC_FCHK 2 /* In forward checksum */
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#define DTC_BLOCK 3 /* In block */
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#define DTC_RCHK 4 /* In reverse checksum */
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#define DTC_RBLK 5 /* In reverse block number */
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#define DTC_REND 7 /* In final endzone */
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#define DTC_MOTMASK 0170
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#define DTC_MOT 0010 /* Tape in motion */
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#define DTC_REV 0020 /* Tape in reverse */
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#define DTC_STOP 0040 /* Tape to stop */
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#define DTC_ACCL 0100 /* Tape accel or decl */
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#define DTC_V_WORD 8 /* Shift for word count */
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#define DTC_M_WORD 0177 /* 128 words per block */
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#define DTC_V_BLK 16 /* Shift for Block number */
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#define DTC_M_BLK 01777 /* Block mask */
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/* Logging */
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#define LOG_MS 00200 /* move, search */
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#define LOG_RW 00400 /* read, write */
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#define LOG_RA 01000 /* read all */
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#define LOG_BL 02000 /* block # lblk */
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#define ABS(x) (((x) < 0)? (-(x)): (x))
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#define DT_WRDTIM 10000
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#define WRITTEN u6 /* Set when tape modified */
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int32 dtsa = 0; /* status A */
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uint64 dtsb = 0; /* status B */
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uint64 dtdb = 0; /* data buffer */
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int dt_mpx_lvl;
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t_stat dt_devio(uint32 dev, uint64 *data);
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t_stat dt_svc (UNIT *uptr);
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t_stat dt_boot(int32 unit_num, DEVICE * dptr);
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t_stat dt_reset (DEVICE *dptr);
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t_stat dt_attach (UNIT *uptr, CONST char *cptr);
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void dt_flush (UNIT *uptr);
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t_stat dt_detach (UNIT *uptr);
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#if MPX_DEV
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t_stat dt_set_mpx (UNIT *uptr, int32 val, CONST char *cptr, void *desc) ;
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t_stat dt_show_mpx (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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#endif
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/* DT data structures
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dt_dev DT device descriptor
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dt_unit DT unit list
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dt_reg DT register list
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dt_mod DT modifier list
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*/
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DIB dt_dib = { DT_DEVNUM, 2, &dt_devio, NULL};
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UNIT dt_unit[] = {
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{ UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
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UNIT_ROABLE, DT_CAPAC) },
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{ UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
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UNIT_ROABLE, DT_CAPAC) },
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{ UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
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UNIT_ROABLE, DT_CAPAC) },
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{ UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
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UNIT_ROABLE, DT_CAPAC) },
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{ UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
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UNIT_ROABLE, DT_CAPAC) },
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{ UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
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UNIT_ROABLE, DT_CAPAC) },
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{ UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
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UNIT_ROABLE, DT_CAPAC) },
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{ UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
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UNIT_ROABLE, DT_CAPAC) }
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};
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REG dt_reg[] = {
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{ ORDATA (DTSA, dtsa, 18) },
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{ ORDATA (DTSB, dtsb, 18) },
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{ ORDATA (DTDB, dtdb, 18) },
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{ ORDATA (MPX, dt_mpx_lvl, 3) },
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{ URDATA (POS, dt_unit[0].pos, 10, T_ADDR_W, 0,
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DT_NUMDR, PV_LEFT | REG_RO | REG_UNIT) },
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{ NULL }
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};
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MTAB dt_mod[] = {
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{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
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{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
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{ UNIT_8FMT + UNIT_11FMT, 0, "18b", NULL, NULL },
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{ UNIT_8FMT + UNIT_11FMT, UNIT_8FMT, "12b", NULL, NULL },
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{ UNIT_8FMT + UNIT_11FMT, UNIT_11FMT, "16b", NULL, NULL },
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#if MPX_DEV
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{MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "MPX", "MPX",
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&dt_set_mpx, &dt_show_mpx, NULL},
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#endif
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{ 0 }
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};
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DEBTAB dt_deb[] = {
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{ "CMD", DEBUG_CMD, "Show command execution to devices"},
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{ "DATA", DEBUG_DATA, "Show data transfers"},
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{ "DETAIL", DEBUG_DETAIL, "Show details about device"},
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{ "EXP", DEBUG_EXP, "Show exception information"},
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{ "CONI", DEBUG_CONI, "Show coni instructions"},
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{ "CONO", DEBUG_CONO, "Show coni instructions"},
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{ "DATAIO", DEBUG_DATAIO, "Show datai and datao instructions"},
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{ "MOTION", LOG_MS },
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{ "DATA", LOG_RW },
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{ "READALL", LOG_RA },
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{ "BLOCK", LOG_BL },
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{ NULL, 0 }
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};
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DEVICE dt_dev = {
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"DT", dt_unit, dt_reg, dt_mod,
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DT_NUMDR, 8, 24, 1, 8, 18,
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NULL, NULL, &dt_reset, &dt_boot, &dt_attach, &dt_detach,
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&dt_dib, DEV_DISABLE | DEV_DEBUG, 0,
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dt_deb, NULL, NULL
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};
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/* IOT routines */
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t_stat dt_devio(uint32 dev, uint64 *data) {
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int i;
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switch(dev & 07) {
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case CONI:
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*data = (uint64)dtsa;
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sim_debug(DEBUG_CONI, &dt_dev, "DTA %03o CONI %06o PC=%o\n",
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dev, (uint32)*data, PC);
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break;
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case CONO:
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clr_interrupt(dev);
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clr_interrupt(dev|4);
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/* Copy over command and priority */
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dtsa &= ~0777;
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dtsa |= (*data & 0777);
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dtsb = 0;
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sim_debug(DEBUG_CONO, &dt_dev, "DTA %03o CONO %06o PC=%o\n",
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dev, (uint32)*data, PC);
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/* Check bits in command register */
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if (*data & DTC_DESEL) {
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/* Stop all drives and clear drive unit */
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dtsa &= 0770777;
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for (i = 0; i < DT_NUMDR; i++) {
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dt_unit[i].CMD &= ~0700;
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}
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if ((*data & DTC_SEL) == 0)
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break;
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}
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if (*data & DTC_SEL) {
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dtsa |= *data & 07000;
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i = DTC_GETUNI(dtsa);
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if ((dt_unit[i].flags & UNIT_ATT) == 0) {
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dtsb |= DTB_ILL|DTB_SELERR;
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dtsb &= ~DTB_IDL;
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if (dtsb & DTB_ILLENB)
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set_interrupt(DT_DEVNUM, dtsa);
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return SCPE_OK;
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}
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if (i < DT_NUMDR && !sim_is_active(&dt_unit[i]))
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sim_activate(&dt_unit[i], 1000);
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if (dt_unit[i].DSTATE & DTC_MOT) {
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switch (dt_unit[i].DSTATE & 7) {
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case DTC_FEND: /* Tape in endzone */
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case DTC_REND: /* In final endzone */
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dtsb |= DTB_END|DTB_IDL;
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break;
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case DTC_FBLK: /* In forward block number */
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case DTC_RBLK: /* In reverse block number */
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dtsb |= DTB_BLK|DTB_IDL;
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break;
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|
|
case DTC_RCHK: /* In reverse checksum */
|
|
case DTC_FCHK: /* In forward checksum */
|
|
dtsb |= DTB_CHK|DTB_IDL;
|
|
break;
|
|
|
|
case DTC_BLOCK: /* In block */
|
|
dtsb |= DTB_DAT;
|
|
break;
|
|
}
|
|
} else {
|
|
dtsb |= DTB_IDL;
|
|
}
|
|
}
|
|
if (*data & (DTC_FWDRV|DTC_RVDRV|DTC_STSTOP)) {
|
|
i = DTC_GETUNI(dtsa);
|
|
#if DT_NUMDR < 8
|
|
if (i >= DT_NUMDR)
|
|
break;
|
|
#endif
|
|
if ((dt_unit[i].flags & UNIT_ATT) == 0) {
|
|
dtsb |= DTB_ILL;
|
|
dtsb &= ~DTB_IDL;
|
|
if (dtsb & DTB_ILLENB)
|
|
set_interrupt(DT_DEVNUM, dtsa);
|
|
return SCPE_OK;
|
|
}
|
|
if (*data & DTC_STSTOP) {
|
|
if ((dt_unit[i].DSTATE & (DTC_MOT)) != 0) {
|
|
dt_unit[i].CMD |= DTC_FNC_STOP;
|
|
}
|
|
dtsa &=~ (DTC_FWDRV|DTC_RVDRV);
|
|
} else {
|
|
/* Start the unit if not already running */
|
|
dt_unit[i].CMD &= ~DTC_FNC_STOP;
|
|
if ((dt_unit[i].DSTATE & (DTC_MOT)) == 0) {
|
|
dt_unit[i].CMD |= DTC_FNC_START;
|
|
dtsb |= DTB_DLY;
|
|
if (!sim_is_active(&dt_unit[i]))
|
|
sim_activate(&dt_unit[i], 10000);
|
|
}
|
|
dtsa &=~ (DTC_FWDRV|DTC_RVDRV);
|
|
switch(*data & (DTC_FWDRV|DTC_RVDRV)) {
|
|
case DTC_FWDRV:
|
|
if (dt_unit[i].DSTATE & DTC_REV) {
|
|
dt_unit[i].CMD |= DTC_FNC_REV;
|
|
dtsa |= (DTC_RVDRV);
|
|
} else
|
|
dtsa |= (DTC_FWDRV);
|
|
break;
|
|
case DTC_RVDRV:
|
|
if ((dt_unit[i].DSTATE & DTC_REV) == 0) {
|
|
dt_unit[i].CMD |= DTC_FNC_REV;
|
|
dtsa |= (DTC_RVDRV);
|
|
} else
|
|
dtsa |= (DTC_FWDRV);
|
|
break;
|
|
case DTC_FWDRV|DTC_RVDRV:
|
|
dt_unit[i].CMD |= DTC_FNC_REV;
|
|
if ((dt_unit[i].DSTATE & DTC_REV) == 0)
|
|
dtsa |= (DTC_RVDRV);
|
|
else
|
|
dtsa |= (DTC_FWDRV);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
|
|
case DATAI:
|
|
*data = dtdb;
|
|
dtsb &= ~DTB_DATREQ;
|
|
clr_interrupt(dev|4);
|
|
sim_debug(DEBUG_DATAIO, &dt_dev, "DTA %03o DATI %012llo PC=%06o\n",
|
|
dev, *data, PC);
|
|
|
|
break;
|
|
|
|
case DATAO:
|
|
dtdb = *data;
|
|
dtsb &= ~DTB_DATREQ;
|
|
clr_interrupt(dev|4);
|
|
sim_debug(DEBUG_DATAIO, &dt_dev, "DTA %03o DATO %012llo PC=%06o\n",
|
|
dev, *data, PC);
|
|
break;
|
|
|
|
case CONI|04:
|
|
*data = dtsb;
|
|
if (dtsb & 0770000)
|
|
*data |= DTB_FLGREQ;
|
|
sim_debug(DEBUG_CONI, &dt_dev, "DTB %03o CONI %012llo PC=%o\n",
|
|
dev, *data, PC);
|
|
break;
|
|
|
|
case CONO|04:
|
|
dtsb = 0;
|
|
clr_interrupt(dev);
|
|
clr_interrupt(dev|4);
|
|
if (*data & DTS_STOP_ALL) {
|
|
/* Stop all other drives */
|
|
for (i = 0; i < DT_NUMDR; i++) {
|
|
if (i != DTC_GETUNI(dtsa) &&
|
|
(dt_unit[i].DSTATE & DTC_MOT) != 0)
|
|
dt_unit[i].CMD |= DTC_FNC_STOP;
|
|
}
|
|
}
|
|
dtsb = (uint64)((*data & (DTS_PAR_ERR|DTS_DATA_MISS|DTS_JOB_DONE| \
|
|
DTS_ILL_OP|DTS_END_ZONE|DTS_BLK_MISS)) << 18);
|
|
if (*data & DTS_FUNC_STOP)
|
|
dtsb |= DTB_STOP;
|
|
|
|
sim_debug(DEBUG_CONO, &dt_dev, "DTB %03o CONO %06o PC=%o DTSB=%012llo\n",
|
|
dev, (uint32)*data, PC, dtsb);
|
|
break;
|
|
|
|
case DATAI|4:
|
|
sim_debug(DEBUG_DATAIO, &dt_dev, "DTB %03o DATI %012llo PC=%06o\n",
|
|
dev, *data, PC);
|
|
break;
|
|
case DATAO|4:
|
|
sim_debug(DEBUG_DATAIO, &dt_dev, "DTB %03o DATO %012llo PC=%06o\n",
|
|
dev, *data, PC);
|
|
break;
|
|
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
void dt_getword(uint64 *data, int req) {
|
|
int dev = dt_dib.dev_num;
|
|
clr_interrupt(dev|4);
|
|
if (dtsb & DTB_DATREQ) {
|
|
dtsb |= DTB_MIS;
|
|
return;
|
|
}
|
|
*data = dtdb;
|
|
if (req) {
|
|
dtsb |= DTB_DATREQ;
|
|
set_interrupt_mpx(dev|4, dtsa >> 3, dt_mpx_lvl);
|
|
}
|
|
}
|
|
|
|
void dt_putword(uint64 *data) {
|
|
int dev = dt_dib.dev_num;
|
|
clr_interrupt(dev|4);
|
|
if (dtsb & DTB_DATREQ) {
|
|
dtsb |= DTB_MIS;
|
|
return;
|
|
}
|
|
dtdb = *data;
|
|
dtsb |= DTB_DATREQ;
|
|
set_interrupt_mpx(dev|4, dtsa >> 3, dt_mpx_lvl);
|
|
}
|
|
|
|
/* Unit service
|
|
|
|
Unit must be attached, detach cancels operation
|
|
*/
|
|
|
|
t_stat dt_svc (UNIT *uptr)
|
|
{
|
|
int word;
|
|
uint64 data = 0;
|
|
uint32 *fbuf = (uint32 *) uptr->filebuf; /* file buffer */
|
|
int u = uptr-dt_unit;
|
|
int blk;
|
|
int off;
|
|
/*
|
|
* Check if in motion or stopping.
|
|
*/
|
|
if (uptr->DSTATE & DTC_MOT) {
|
|
/* Check if stoping */
|
|
if (uptr->CMD & DTC_FNC_STOP) {
|
|
/* Stop delay */
|
|
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o stopping\n", u);
|
|
sim_activate(uptr, DT_WRDTIM*10);
|
|
uptr->CMD &= ~DTC_FNC_STOP;
|
|
uptr->DSTATE &= ~(DTC_MOT);
|
|
blk = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
uptr->DSTATE = (0100 << DTC_V_WORD) | DTC_BLOCK | (DTC_MOTMASK & uptr->DSTATE);
|
|
if (uptr->DSTATE & DTC_REV) {
|
|
if (blk <= 0) {
|
|
blk = 0;
|
|
uptr->DSTATE = DTC_FEND | (DTC_MOTMASK & uptr->DSTATE);
|
|
} else {
|
|
blk--;
|
|
}
|
|
} else {
|
|
if (blk <= 01100)
|
|
blk++;
|
|
}
|
|
uptr->DSTATE |= (blk << DTC_V_BLK);
|
|
return SCPE_OK;
|
|
}
|
|
if (uptr->CMD & DTC_FNC_REV) {
|
|
sim_activate(uptr, DT_WRDTIM*10);
|
|
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o reversing\n", u);
|
|
uptr->CMD &= ~DTC_FNC_REV;
|
|
uptr->DSTATE ^= DTC_REV;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
if (DTC_GETUNI(dtsa) == u) {
|
|
dtsb |= DTB_SPD;
|
|
dtsb &= ~(DTB_DLY|DTB_IDL);
|
|
}
|
|
/* Moving in reverse direction */
|
|
if (uptr->DSTATE & DTC_REV) {
|
|
if (DTC_GETUNI(dtsa) == u) {
|
|
dtsb |= DTB_REV;
|
|
dtsa &=~ DTC_FWDRV;
|
|
dtsa |= DTC_RVDRV;
|
|
}
|
|
switch (uptr->DSTATE & 7) {
|
|
case DTC_FEND: /* Tape in endzone */
|
|
/* Set stop */
|
|
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o rev forward end\n", u);
|
|
uptr->CMD |= DTC_FNC_STOP;
|
|
uptr->u6 = 0;
|
|
dtsb |= DTB_END;
|
|
dtsb &= ~DTB_IDL;
|
|
if (dtsb & DTB_ENDENB)
|
|
set_interrupt(DT_DEVNUM, dtsa);
|
|
sim_activate(uptr, DT_WRDTIM*10);
|
|
break;
|
|
|
|
case DTC_FBLK: /* In forward block number */
|
|
sim_activate(uptr,DT_WRDTIM);
|
|
word = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
word--;
|
|
if (word == 0)
|
|
uptr->DSTATE = DTC_FEND | (DTC_MOTMASK & uptr->DSTATE);
|
|
else
|
|
uptr->DSTATE = DTC_RBLK|(word << DTC_V_BLK) | (DTC_MOTMASK & uptr->DSTATE);
|
|
dtsb &= ~(DTB_CHK);
|
|
dtsb |= DTB_IDL;
|
|
if (dtsb & DTB_STOP)
|
|
dtsa &= ~0700; /* Clear command */
|
|
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o rev forward block\n", u);
|
|
switch (DTC_GETFNC(uptr->CMD)) {
|
|
case FNC_MOVE:
|
|
case FNC_SRCH:
|
|
case FNC_WBLK:
|
|
if ((dtsb & DTB_STOP) == 0)
|
|
break;
|
|
/* Fall through */
|
|
case FNC_WALL:
|
|
case FNC_RALL:
|
|
case FNC_WRIT:
|
|
case FNC_READ:
|
|
uptr->CMD &= 077077;
|
|
dtsb |= DTB_DONE;
|
|
if (dtsb & DTB_JOBENB)
|
|
set_interrupt(DT_DEVNUM, dtsa);
|
|
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o rev stop\n", u);
|
|
dtsb &= ~DTB_STOP;
|
|
break;
|
|
case FNC_WMRK:
|
|
dtsb |= DTS_ILL_OP;
|
|
if (dtsb & DTB_ILLENB)
|
|
set_interrupt(DT_DEVNUM, dtsa);
|
|
break;
|
|
}
|
|
if (dtsb & (DTB_PAR|DTB_MIS|DTB_ILL|DTB_END|DTB_INCBLK|DTB_MRKERR)) {
|
|
uptr->CMD |= DTC_FNC_STOP;
|
|
}
|
|
if (DTC_GETUNI(dtsa) == u) {
|
|
uptr->CMD &= 077077;
|
|
uptr->CMD |= dtsa & 0700; /* Copy command */
|
|
}
|
|
if (word <= 0) {
|
|
uptr->DSTATE = DTC_FEND | (DTC_MOTMASK & uptr->DSTATE);
|
|
}
|
|
break;
|
|
|
|
case DTC_FCHK: /* In forward checksum */
|
|
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o rev forward check\n", u);
|
|
sim_activate(uptr,DT_WRDTIM*2);
|
|
word = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
uptr->DSTATE = DTC_FBLK|(word << DTC_V_BLK) | (DTC_MOTMASK & uptr->DSTATE);
|
|
dtsb &= ~(DTB_DAT|DTB_FIN);
|
|
dtsb |= DTB_CHK;
|
|
break;
|
|
|
|
case DTC_BLOCK: /* In block */
|
|
sim_activate(uptr,DT_WRDTIM);
|
|
dtsb |= DTB_DAT;
|
|
blk = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
word = (uptr->DSTATE >> DTC_V_WORD) & DTC_M_WORD;
|
|
off = ((blk << 7) + word) << 1;
|
|
/* Check if at end of block */
|
|
if (word == 0) {
|
|
uptr->DSTATE &= ~((DTC_M_WORD << DTC_V_WORD) | 7);
|
|
uptr->DSTATE |= DTC_FCHK; /* Move to Checksum */
|
|
dtsb &= ~DTB_DAT;
|
|
dtsb |= DTB_FIN;
|
|
} else {
|
|
uptr->DSTATE &= ~(DTC_M_WORD << DTC_V_WORD);
|
|
uptr->DSTATE |= (word - 1) << DTC_V_WORD;
|
|
}
|
|
uptr->u6-=2;
|
|
switch (DTC_GETFNC(uptr->CMD)) {
|
|
case FNC_MOVE:
|
|
case FNC_SRCH:
|
|
case FNC_WBLK:
|
|
break;
|
|
case FNC_WMRK:
|
|
dtsb |= DTS_ILL_OP;
|
|
if (dtsb & DTB_ILLENB)
|
|
set_interrupt(DT_DEVNUM, dtsa);
|
|
break;
|
|
case FNC_RALL:
|
|
case FNC_READ:
|
|
data = ((uint64)fbuf[off]) << 18;
|
|
data |= ((uint64)fbuf[off+1]);
|
|
if ((dtsb & DTB_STOP) == 0)
|
|
dt_putword(&data);
|
|
break;
|
|
|
|
case FNC_WRIT:
|
|
case FNC_WALL:
|
|
if ((dtsb & DTB_STOP) == 0)
|
|
dt_getword(&data, (word != 0));
|
|
else
|
|
data = dtdb;
|
|
fbuf[off] = (data >> 18) & RMASK;
|
|
fbuf[off+1] = data & RMASK;
|
|
uptr->WRITTEN = 1;
|
|
uptr->hwmark = uptr->capac;
|
|
break;
|
|
}
|
|
if (word == 0) {
|
|
dtsb &= ~DTB_DAT;
|
|
dtsb |= DTB_FIN;
|
|
}
|
|
sim_debug(DEBUG_DETAIL, &dt_dev,
|
|
"DTA %o rev data word %o:%o %012llo %d %06o %06o\n",
|
|
u, blk, word, data, off, fbuf[off], fbuf[off+1]);
|
|
break;
|
|
|
|
case DTC_RCHK: /* In reverse checksum */
|
|
sim_activate(uptr,DT_WRDTIM*2);
|
|
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o rev reverse check\n", u);
|
|
word = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
uptr->DSTATE = DTC_BLOCK|(word << DTC_V_BLK)|(DTC_M_WORD << DTC_V_WORD) |
|
|
(DTC_MOTMASK & uptr->DSTATE);
|
|
if (dtsb & DTB_STOP)
|
|
dtsa &= ~0700; /* Clear command */
|
|
if (DTC_GETUNI(dtsa) == u) {
|
|
uptr->CMD &= 077077;
|
|
uptr->CMD |= dtsa & 0700; /* Copy command */
|
|
}
|
|
dtsb &= ~DTB_BLKRD;
|
|
switch (DTC_GETFNC(uptr->CMD)) {
|
|
case FNC_WRIT:
|
|
case FNC_WALL:
|
|
dtsb |= DTB_DATREQ;
|
|
set_interrupt_mpx(DT_DEVNUM|4, dtsa >> 3, dt_mpx_lvl);
|
|
break;
|
|
case FNC_RALL:
|
|
case FNC_MOVE:
|
|
case FNC_READ:
|
|
case FNC_WBLK:
|
|
break;
|
|
case FNC_SRCH:
|
|
dtsb |= DTB_DONE;
|
|
dtsb &= ~DTB_STOP;
|
|
if (dtsb & DTB_JOBENB)
|
|
set_interrupt(DT_DEVNUM, dtsa);
|
|
break;
|
|
case FNC_WMRK:
|
|
dtsb |= DTS_ILL_OP;
|
|
if (dtsb & DTB_ILLENB)
|
|
set_interrupt(DT_DEVNUM, dtsa);
|
|
break;
|
|
}
|
|
if (dtsb & (DTB_PAR|DTB_MIS|DTB_ILL|DTB_END|DTB_INCBLK|DTB_MRKERR)) {
|
|
uptr->CMD |= DTC_FNC_STOP;
|
|
}
|
|
break;
|
|
|
|
case DTC_RBLK: /* In reverse block number */
|
|
sim_activate(uptr,DT_WRDTIM*2);
|
|
word = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
data = (uint64)word;
|
|
uptr->DSTATE = DTC_RCHK|(word << DTC_V_BLK)|(DTC_M_WORD << DTC_V_WORD) |
|
|
(DTC_MOTMASK & uptr->DSTATE);
|
|
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o rev reverse block %04o\n", u, word);
|
|
dtsb &= ~DTB_END;
|
|
dtsb |= DTB_BLKRD;
|
|
if (DTC_GETUNI(dtsa) == u) {
|
|
uptr->CMD &= 077077;
|
|
uptr->CMD |= dtsa & 0700; /* Copy command */
|
|
}
|
|
switch (DTC_GETFNC(uptr->CMD)) {
|
|
case FNC_MOVE:
|
|
case FNC_READ:
|
|
case FNC_WMRK:
|
|
case FNC_WRIT:
|
|
break;
|
|
case FNC_RALL:
|
|
dt_putword(&data);
|
|
break;
|
|
case FNC_SRCH:
|
|
dt_putword(&data);
|
|
break;
|
|
case FNC_WALL:
|
|
case FNC_WBLK:
|
|
dt_getword(&data, 0);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case DTC_REND: /* In final endzone */
|
|
sim_activate(uptr, DT_WRDTIM*10);
|
|
word = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
word--;
|
|
uptr->DSTATE = DTC_RBLK|(word << DTC_V_BLK) | (DTC_MOTMASK & uptr->DSTATE);
|
|
break;
|
|
}
|
|
} else {
|
|
if (DTC_GETUNI(dtsa) == u) {
|
|
dtsb &= ~DTB_REV;
|
|
dtsa &=~ DTC_RVDRV;
|
|
dtsa |= DTC_FWDRV;
|
|
}
|
|
/* Moving in forward direction */
|
|
switch (uptr->DSTATE & 7) {
|
|
case DTC_FEND: /* Tape in endzone */
|
|
sim_activate(uptr, DT_WRDTIM*10);
|
|
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o forward end\n", u);
|
|
uptr->DSTATE = DTC_FBLK | (DTC_MOTMASK & uptr->DSTATE); /* Move to first block */
|
|
uptr->u6 = 0;
|
|
dtsb &= ~DTB_IDL;
|
|
break;
|
|
|
|
case DTC_FBLK: /* In forward block number */
|
|
sim_activate(uptr,DT_WRDTIM*2);
|
|
dtsb &= ~DTB_END;
|
|
dtsb |= DTB_BLKRD;
|
|
word = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
uptr->DSTATE = DTC_FCHK|(word << DTC_V_BLK) | (DTC_MOTMASK & uptr->DSTATE);
|
|
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o forward block %04o\n", u, word);
|
|
data = (uint64)word;
|
|
if (DTC_GETUNI(dtsa) == u) {
|
|
uptr->CMD &= 077077;
|
|
uptr->CMD |= dtsa & 0700; /* Copy command */
|
|
}
|
|
switch (DTC_GETFNC(uptr->CMD)) {
|
|
case FNC_RALL:
|
|
case FNC_SRCH:
|
|
dt_putword(&data);
|
|
break;
|
|
case FNC_MOVE:
|
|
case FNC_READ:
|
|
case FNC_WRIT:
|
|
break;
|
|
case FNC_WALL:
|
|
case FNC_WBLK:
|
|
dt_getword(&data, 0);
|
|
break;
|
|
case FNC_WMRK:
|
|
dtsb |= DTS_ILL_OP;
|
|
if (dtsb & DTB_ILLENB)
|
|
set_interrupt(DT_DEVNUM, dtsa);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case DTC_FCHK: /* In forward checksum */
|
|
sim_activate(uptr,DT_WRDTIM*2);
|
|
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o forward check\n", u);
|
|
dtsb &= ~DTB_BLKRD;
|
|
uptr->DSTATE &= ~7;
|
|
uptr->DSTATE |= DTC_BLOCK; /* Move to datablock */
|
|
if (dtsb & DTB_STOP)
|
|
dtsa &= ~0700; /* Clear command */
|
|
if (DTC_GETUNI(dtsa) == u) {
|
|
uptr->CMD &= 077077;
|
|
uptr->CMD |= dtsa & 0700; /* Copy command */
|
|
}
|
|
switch (DTC_GETFNC(uptr->CMD)) {
|
|
case FNC_WRIT:
|
|
case FNC_WALL:
|
|
dtsb |= DTB_DATREQ;
|
|
set_interrupt_mpx(DT_DEVNUM|4, dtsa >> 3, dt_mpx_lvl);
|
|
break;
|
|
case FNC_SRCH:
|
|
dtsb |= DTB_DONE;
|
|
dtsb &= ~DTB_STOP;
|
|
if (dtsb & DTB_JOBENB)
|
|
set_interrupt(DT_DEVNUM, dtsa);
|
|
break;
|
|
case FNC_WMRK:
|
|
dtsb |= DTS_ILL_OP;
|
|
if (dtsb & DTB_ILLENB)
|
|
set_interrupt(DT_DEVNUM, dtsa);
|
|
break;
|
|
case FNC_RALL:
|
|
case FNC_READ:
|
|
case FNC_WBLK:
|
|
case FNC_MOVE:
|
|
break;
|
|
}
|
|
if (dtsb & (DTB_PAR|DTB_MIS|DTB_ILL|DTB_END|DTB_INCBLK|DTB_MRKERR)) {
|
|
uptr->CMD |= DTC_FNC_STOP;
|
|
}
|
|
break;
|
|
|
|
case DTC_BLOCK: /* In block */
|
|
sim_activate(uptr,DT_WRDTIM);
|
|
blk = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
word = (uptr->DSTATE >> DTC_V_WORD) & DTC_M_WORD;
|
|
off = ((blk << 7) + word) << 1;
|
|
dtsb |= DTB_DAT;
|
|
/* Check if at end of block */
|
|
if (word == DTC_M_WORD) {
|
|
uptr->DSTATE &= ~7;
|
|
uptr->DSTATE |= DTC_RCHK; /* Move to checksum */
|
|
dtsb |= DTB_FIN;
|
|
} else {
|
|
uptr->DSTATE &= ~(DTC_M_WORD << DTC_V_WORD);
|
|
uptr->DSTATE |= (word + 1) << DTC_V_WORD;
|
|
}
|
|
switch (DTC_GETFNC(uptr->CMD)) {
|
|
case FNC_MOVE:
|
|
case FNC_SRCH:
|
|
case FNC_WALL:
|
|
case FNC_WBLK:
|
|
break;
|
|
case FNC_RALL:
|
|
case FNC_READ:
|
|
data = ((uint64)fbuf[off]) << 18;
|
|
data |= (uint64)fbuf[off+1];
|
|
if ((dtsb & DTB_STOP) == 0)
|
|
dt_putword(&data);
|
|
else
|
|
uptr->CMD &= 077077;
|
|
break;
|
|
case FNC_WRIT:
|
|
if ((dtsb & DTB_STOP) == 0)
|
|
dt_getword(&data, (word != DTC_M_WORD));
|
|
else {
|
|
uptr->CMD &= 077077;
|
|
data = dtdb;
|
|
}
|
|
fbuf[off] = (data >> 18) & RMASK;
|
|
fbuf[off+1] = data & RMASK;
|
|
uptr->WRITTEN = 1;
|
|
uptr->hwmark = uptr->capac;
|
|
break;
|
|
case FNC_WMRK:
|
|
dtsb |= DTS_ILL_OP;
|
|
if (dtsb & DTB_ILLENB)
|
|
set_interrupt(DT_DEVNUM, dtsa);
|
|
break;
|
|
}
|
|
if (word == DTC_M_WORD) {
|
|
dtsb &= ~DTB_DAT;
|
|
dtsb |= DTB_FIN;
|
|
}
|
|
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o data word %o:%o %012llo %d %06o %06o\n",
|
|
u, blk, word, data, off, fbuf[off], fbuf[off+1]);
|
|
break;
|
|
|
|
case DTC_RCHK: /* In reverse checksum */
|
|
sim_activate(uptr,DT_WRDTIM*2);
|
|
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o reverse check\n", u);
|
|
uptr->DSTATE &= ~(DTC_M_WORD << DTC_V_WORD) | 7;
|
|
uptr->DSTATE |= DTC_RBLK; /* Move to end of block */
|
|
dtsb &= ~(DTB_DAT|DTB_FIN);
|
|
dtsb |= DTB_CHK;
|
|
break;
|
|
|
|
case DTC_RBLK: /* In reverse block number */
|
|
sim_activate(uptr,DT_WRDTIM*2);
|
|
dtsb &= ~(DTB_CHK);
|
|
dtsb |= DTB_IDL;
|
|
if (DTC_GETUNI(dtsa) == u) {
|
|
uptr->CMD &= 077077;
|
|
uptr->CMD |= dtsa & 0700; /* Copy command */
|
|
}
|
|
word = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
word++;
|
|
if (word > 01101) {
|
|
uptr->DSTATE = DTC_REND|(word << DTC_V_BLK)|(DTC_M_WORD << DTC_V_WORD) |
|
|
(DTC_MOTMASK & uptr->DSTATE);
|
|
} else {
|
|
uptr->DSTATE = DTC_FBLK|(word << DTC_V_BLK) | (DTC_MOTMASK & uptr->DSTATE);
|
|
}
|
|
if (dtsb & DTB_STOP)
|
|
dtsa &= ~0700; /* Clear command */
|
|
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o reverse block %o\n", u, word);
|
|
switch (DTC_GETFNC(uptr->CMD)) {
|
|
case FNC_MOVE:
|
|
case FNC_WBLK:
|
|
case FNC_SRCH:
|
|
if ((dtsb & DTB_STOP) == 0)
|
|
break;
|
|
/* Fall through */
|
|
case FNC_WALL:
|
|
case FNC_RALL:
|
|
case FNC_WRIT:
|
|
case FNC_READ:
|
|
case FNC_WMRK:
|
|
uptr->CMD &= 077077;
|
|
dtsb |= DTB_DONE;
|
|
if (dtsb & DTB_JOBENB)
|
|
set_interrupt(DT_DEVNUM, dtsa);
|
|
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o stop\n", u);
|
|
dtsb &= ~DTB_STOP;
|
|
break;
|
|
}
|
|
if (dtsb & (DTB_PAR|DTB_MIS|DTB_ILL|DTB_END|DTB_INCBLK|DTB_MRKERR)) {
|
|
uptr->CMD |= DTC_FNC_STOP;
|
|
}
|
|
break;
|
|
|
|
case DTC_REND: /* In final endzone */
|
|
/* Set stop */
|
|
uptr->CMD |= DTC_FNC_STOP;
|
|
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o reverse end\n", u);
|
|
dtsb &= ~DTB_IDL;
|
|
dtsb |= DTB_END;
|
|
if (dtsb & DTB_ENDENB)
|
|
set_interrupt(DT_DEVNUM, dtsa);
|
|
sim_activate(uptr, DT_WRDTIM*10);
|
|
break;
|
|
}
|
|
}
|
|
/* Check if starting */
|
|
} else if (uptr->CMD & DTC_FNC_START) {
|
|
/* Start up delay */
|
|
sim_activate(uptr, DT_WRDTIM*10);
|
|
uptr->CMD &= ~(0700 | DTC_FNC_START);
|
|
if (DTC_GETUNI(dtsa) == u)
|
|
uptr->CMD |= dtsa & 0700; /* Copy command */
|
|
uptr->DSTATE |= DTC_MOT;
|
|
if (uptr->CMD & DTC_FNC_REV) {
|
|
uptr->CMD &= ~DTC_FNC_REV;
|
|
uptr->DSTATE ^= DTC_REV;
|
|
}
|
|
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o start %06o\n", u, uptr->CMD);
|
|
return SCPE_OK;
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Boot from given device */
|
|
t_stat
|
|
dt_boot(int32 unit_num, DEVICE * dptr)
|
|
{
|
|
UNIT *uptr = &dptr->units[unit_num];
|
|
uint32 *fbuf = (uint32 *) uptr->filebuf; /* file buffer */
|
|
uint64 word = 0;
|
|
int off;
|
|
int wc, addr;
|
|
|
|
if ((uptr->flags & UNIT_ATT) == 0)
|
|
return SCPE_UNATT; /* attached? */
|
|
|
|
off = 0;
|
|
wc = fbuf[off++];
|
|
addr = fbuf[off++];
|
|
while (wc != 0) {
|
|
wc = (wc + 1) & RMASK;
|
|
addr = (addr + 1) & RMASK;
|
|
word = ((uint64)fbuf[off++]) << 18;
|
|
word |= (uint64)fbuf[off++];
|
|
if (addr < 020)
|
|
FM[addr] = word;
|
|
else
|
|
M[addr] = word;
|
|
}
|
|
if (addr < 020)
|
|
FM[addr] = word;
|
|
else
|
|
M[addr] = word;
|
|
uptr->DSTATE = (1 << DTC_V_BLK) | DTC_BLOCK | DTC_MOT;
|
|
sim_activate(uptr,30000);
|
|
PC = word & RMASK;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
#if MPX_DEV
|
|
/* set MPX level number */
|
|
t_stat dt_set_mpx (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
|
|
{
|
|
int32 mpx;
|
|
t_stat r;
|
|
|
|
if (cptr == NULL)
|
|
return SCPE_ARG;
|
|
mpx = (int32) get_uint (cptr, 8, 8, &r);
|
|
if (r != SCPE_OK)
|
|
return r;
|
|
dt_mpx_lvl = mpx;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat dt_show_mpx (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
|
|
{
|
|
if (uptr == NULL)
|
|
return SCPE_IERR;
|
|
|
|
fprintf (st, "MPX=%o", dt_mpx_lvl);
|
|
return SCPE_OK;
|
|
}
|
|
#endif
|
|
|
|
/* Reset routine */
|
|
|
|
t_stat dt_reset (DEVICE *dptr)
|
|
{
|
|
int i;
|
|
|
|
dtsb = dtsa = 0; /* clear status */
|
|
for (i = 0; i < DT_NUMDR; i++) {
|
|
if ((dt_unit[i].DSTATE & DTC_MOT) != 0)
|
|
dt_unit[i].CMD |= DTC_FNC_STOP;
|
|
}
|
|
clr_interrupt(DT_DEVNUM);
|
|
clr_interrupt(DT_DEVNUM|4);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Attach routine
|
|
|
|
Determine 12b, 16b, or 18b/36b format
|
|
Allocate buffer
|
|
If 12b, read 12b format and convert to 18b in buffer
|
|
If 16b, read 16b format and convert to 18b in buffer
|
|
If 18b/36b, read data into buffer
|
|
*/
|
|
|
|
t_stat dt_attach (UNIT *uptr, CONST char *cptr)
|
|
{
|
|
uint16 pdp8b[D8_NBSIZE];
|
|
uint16 pdp11b[D18_BSIZE];
|
|
uint32 ba, sz, k, *fbuf;
|
|
int32 u = uptr - dt_dev.units;
|
|
t_stat r;
|
|
|
|
r = attach_unit (uptr, cptr); /* attach */
|
|
if (r != SCPE_OK) /* error? */
|
|
return r;
|
|
if ((sim_switches & SIM_SW_REST) == 0) { /* not from rest? */
|
|
uptr->flags = uptr->flags & ~(UNIT_8FMT | UNIT_11FMT); /* default 18b */
|
|
if (sim_switches & SWMASK ('T')) /* att 12b? */
|
|
uptr->flags = uptr->flags | UNIT_8FMT;
|
|
else if (sim_switches & SWMASK ('S')) /* att 16b? */
|
|
uptr->flags = uptr->flags | UNIT_11FMT;
|
|
else if (!(sim_switches & SWMASK ('A')) && /* autosize? */
|
|
(sz = sim_fsize (uptr->fileref))) {
|
|
if (sz == D8_FILSIZ)
|
|
uptr->flags = uptr->flags | UNIT_8FMT;
|
|
else if (sz == D11_FILSIZ)
|
|
uptr->flags = uptr->flags | UNIT_11FMT;
|
|
}
|
|
}
|
|
uptr->capac = DTU_CAPAC (uptr); /* set capacity */
|
|
uptr->filebuf = calloc (uptr->capac, sizeof (uint32));
|
|
if (uptr->filebuf == NULL) { /* can't alloc? */
|
|
detach_unit (uptr);
|
|
return SCPE_MEM;
|
|
}
|
|
fbuf = (uint32 *) uptr->filebuf; /* file buffer */
|
|
sim_printf ("%s%d: ", sim_dname (&dt_dev), u);
|
|
if (uptr->flags & UNIT_8FMT)
|
|
sim_printf ("12b format");
|
|
else if (uptr->flags & UNIT_11FMT)
|
|
sim_printf ("16b format");
|
|
else sim_printf ("18b/36b format");
|
|
sim_printf (", buffering file in memory\n");
|
|
uptr->io_flush = dt_flush;
|
|
if (uptr->flags & UNIT_8FMT) { /* 12b? */
|
|
for (ba = 0; ba < uptr->capac; ) { /* loop thru file */
|
|
k = fxread (pdp8b, sizeof (uint16), D8_NBSIZE, uptr->fileref);
|
|
if (k == 0)
|
|
break;
|
|
for ( ; k < D8_NBSIZE; k++)
|
|
pdp8b[k] = 0;
|
|
for (k = 0; k < D8_NBSIZE; k = k + 3) { /* loop thru blk */
|
|
fbuf[ba] = ((uint32) (pdp8b[k] & 07777) << 6) |
|
|
((uint32) (pdp8b[k + 1] >> 6) & 077);
|
|
fbuf[ba + 1] = ((uint32) (pdp8b[k + 1] & 077) << 12) |
|
|
((uint32) pdp8b[k + 2] & 07777);
|
|
ba = ba + 2; /* end blk loop */
|
|
}
|
|
} /* end file loop */
|
|
uptr->hwmark = ba;
|
|
} else if (uptr->flags & UNIT_11FMT) { /* 16b? */
|
|
for (ba = 0; ba < uptr->capac; ) { /* loop thru file */
|
|
k = fxread (pdp11b, sizeof (uint16), D18_BSIZE, uptr->fileref);
|
|
if (k == 0)
|
|
break;
|
|
for ( ; k < D18_BSIZE; k++)
|
|
pdp11b[k] = 0;
|
|
for (k = 0; k < D18_BSIZE; k++)
|
|
fbuf[ba++] = pdp11b[k];
|
|
}
|
|
uptr->hwmark = ba;
|
|
} else uptr->hwmark = fxread (uptr->filebuf, sizeof (uint32),
|
|
uptr->capac, uptr->fileref);
|
|
uptr->flags = uptr->flags | UNIT_BUF; /* set buf flag */
|
|
uptr->pos = DT_EZLIN; /* beyond leader */
|
|
uptr->WRITTEN = 0;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Flush tape image to disk
|
|
|
|
Cancel in progress operation
|
|
If 12b, convert 18b buffer to 12b and write to file
|
|
If 16b, convert 18b buffer to 16b and write to file
|
|
If 18b/36b, write buffer to file
|
|
Deallocate buffer
|
|
*/
|
|
|
|
void dt_flush (UNIT* uptr)
|
|
{
|
|
uint16 pdp8b[D8_NBSIZE];
|
|
uint16 pdp11b[D18_BSIZE];
|
|
uint32 ba, k, *fbuf;
|
|
|
|
if (uptr->WRITTEN && uptr->hwmark && ((uptr->flags & UNIT_RO) == 0)) { /* any data? */
|
|
rewind (uptr->fileref); /* start of file */
|
|
fbuf = (uint32 *) uptr->filebuf; /* file buffer */
|
|
if (uptr->flags & UNIT_8FMT) { /* 12b? */
|
|
for (ba = 0; ba < uptr->hwmark; ) { /* loop thru file */
|
|
for (k = 0; k < D8_NBSIZE; k = k + 3) { /* loop blk */
|
|
pdp8b[k] = (fbuf[ba] >> 6) & 07777;
|
|
pdp8b[k + 1] = ((fbuf[ba] & 077) << 6) |
|
|
((fbuf[ba + 1] >> 12) & 077);
|
|
pdp8b[k + 2] = fbuf[ba + 1] & 07777;
|
|
ba = ba + 2;
|
|
} /* end loop blk */
|
|
fxwrite (pdp8b, sizeof (uint16), D8_NBSIZE, uptr->fileref);
|
|
if (ferror (uptr->fileref))
|
|
break;
|
|
} /* end loop file */
|
|
} else if (uptr->flags & UNIT_11FMT) { /* 16b? */
|
|
for (ba = 0; ba < uptr->hwmark; ) { /* loop thru file */
|
|
for (k = 0; k < D18_BSIZE; k++) /* loop blk */
|
|
pdp11b[k] = fbuf[ba++] & 0177777;
|
|
fxwrite (pdp11b, sizeof (uint16), D18_BSIZE, uptr->fileref);
|
|
if (ferror (uptr->fileref))
|
|
break;
|
|
} /* end loop file */
|
|
} /* end if 16b */
|
|
else fxwrite (uptr->filebuf, sizeof (uint32), /* write file */
|
|
uptr->hwmark, uptr->fileref);
|
|
if (ferror (uptr->fileref))
|
|
sim_perror ("I/O error");
|
|
} /* end if hwmark */
|
|
uptr->WRITTEN = 0;
|
|
}
|
|
|
|
/* Detach routine
|
|
|
|
Cancel in progress operation
|
|
If 12b, convert 18b buffer to 12b and write to file
|
|
If 16b, convert 18b buffer to 16b and write to file
|
|
If 18b/36b, write buffer to file
|
|
Deallocate buffer
|
|
*/
|
|
|
|
t_stat dt_detach (UNIT* uptr)
|
|
{
|
|
int32 u = uptr - dt_dev.units;
|
|
|
|
if (!(uptr->flags & UNIT_ATT))
|
|
return SCPE_OK;
|
|
if (sim_is_active (uptr)) {
|
|
sim_cancel (uptr);
|
|
uptr->CMD = uptr->pos = 0;
|
|
}
|
|
if (uptr->hwmark && ((uptr->flags & UNIT_RO) == 0)) { /* any data? */
|
|
sim_printf ("%s%d: writing buffer to file\n", sim_dname (&dt_dev), u);
|
|
dt_flush(uptr);
|
|
} /* end if hwmark */
|
|
free (uptr->filebuf); /* release buf */
|
|
uptr->flags = uptr->flags & ~UNIT_BUF; /* clear buf flag */
|
|
uptr->filebuf = NULL; /* clear buf ptr */
|
|
uptr->flags = uptr->flags & ~(UNIT_8FMT | UNIT_11FMT); /* default fmt */
|
|
uptr->capac = DT_CAPAC; /* default size */
|
|
return detach_unit (uptr);
|
|
}
|
|
#endif
|