07f99bb8c3
- This release of the HP 3000 simulator adds the following device simulation:
- 30209A Line Printer Controller with One 2607/13/17/18 Line Printer
The simulation supports the use of custom VFU tape images, as well as the
built-in HP-standard VFU tape. The simulated device name is "LP". The full set
of configurable options is detailed in a new section of the HP 3000 Simulator
User's Guide.
In addition, the preconfigured MPE-V/R disc image has been updated to add the
following features:
- The MPE cold load command files attach the line printer to the "lp.txt"
output file and specify the "-n" option to clear the file before use.
- Preinstalled User-Defined Commands (UDCs) provide access to the COBOL 74
compiler with the MPE-V/E :COBOLII, :COBOLIIPREP, and :COBOLIIGO commands,
and to the COBOL 85 compiler with :COBOLIIX, :COBOLIIXPREP, and :COBOLIIXGO.
However, see the implementation note below.
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Implementation Notes
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- MPE requires a line printer, so it is recommended that the MPE startup
simulator command file include an ATTACH LP <filename> command to load paper
into the printer before cold loading. If the printer is not attached, it
will appear to MPE to be out of paper.
- The line printer terminates each print line with an HP-standard CR/LF pair.
If the output file is to be retained as a text file on a Unix system, removal
of the carriage returns, e.g., via the "dos2unix" utility, may be desirable.
- The simulator currently does not provide the HP 32234A COBOL II firmware
instructions, so programs generated by the COBOLII compiler will abort at run
time with an "ILLEGAL INSTRUCTION" error. Programs generated by the COBOL
compiler do not use these instructions and therefore are not affected.
----------
Bugs Fixed
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1. PROBLEM: The effective address of a byte pointer with a negative index is
calculated incorrectly.
VERSION: Release 1
OBSERVATION: Defining a :WELCOME message in MPE appears to work, but when
the next logon attempts to print the message, an infinite number of CRLFs
are printed instead.
CAUSE: The welcome message is stored in an extra data segment. The format
for each message line is a line length stored in the lower byte of the word
preceding the message string. The code defines BYTE POINTER NEXTLINE and
points NEXTLINE to the first message character. The line length is set
with NEXTLINE(-1) := IOCOUNT. This generates a LOAD <IOCOUNT> ; LDXN 1 ;
STB <NEXTLINE>,I,X sequence.
In the "cpu_ea" routine, the indexing adds the X register value (-1) to the
byte pointer (NEXTLINE). This causes an overflow that is not masked to 16
bits. For a word access, this displacement is added to the base register
and then masked to 16 bits, which gives the correct value. However, for
byte accesses, the displacement is divided by 2 and then added, and the sum
is masked. Dividing by 2 shifts the overflow bit into the MSB, causing the
addition result to be off by 32K. The STB goes to the wrong location, the
original zero in the length byte location is retained, and when the welcome
message is printed, a zero-length line is printed, and the byte pointer is
incremented by zero, so the null line is printed forever.
RESOLUTION: Modify "cpu_ea" (hp3000_cpu.c) to mask indexed displacements
to 16 bits after adding the X register value.
STATUS: Fixed in Release 2.
2. PROBLEM: An SMSK instruction may clear the interrupt mask flip-flop of a
device that specifies that it is should be "always enabled."
VERSION: Release 1
OBSERVATION: If the TOS word is zero, an SMSK instruction will clear the
interrupt mask flip-flop of a device whose mask jumper is set to "E"
(always enabled).
CAUSE: In response to a DSETMASK signal, device interfaces set their
interrupt mask flip-flops by "anding" the incoming data word with the
interrupt mask jumper setting. The jumper setting value for "always
enabled" is %177777, which sets the mask flip-flop in all cases, except
when the data word is zero.
RESOLUTION: Modify hp3000_atc.c, hp3000_ds.c, and hp3000_ms.c to set their
mask flip-flops unconditionally if the jumper setting is "E".
STATUS: Fixed in Release 2.
3. PROBLEM: The "SET <dev> INTMASK=<n>" command sets the wrong bit in the
device interface's interrupt mask jumper setting.
VERSION: Release 1
OBSERVATION: The interrupt mask jumper on a device interface is set by
specifying the mask bit number in a "SET <dev> INTMASK=<n>" command. This
sets a bit in the device's interrupt mask jumper word corresponding to the
bit number requested. However, the bit numbering is incorrect; setting the
jumper for bit 15, for example, sets bit 0 of the jumper word. Therefore,
the interface's mask flip-flop is not set as expected when an SMSK
instruction is executed.
CAUSE: The bit numbers were counted from the wrong end of the word.
RESOLUTION: Modify "hp_set_dib" and "hp_show_dib" (hp3000_sys.c) to number
the bits from the MSB instead of the LSB.
STATUS: Fixed in Release 2.
4. PROBLEM: The Multiplexer Channel is not generating the ACKSR signal
correctly.
VERSION: Release 1
OBSERVATION: The line printer controller hangs when an SIO chained write
is performed. The first programmed write completes normally, but the
second does not start. The channel is waiting for a service request that
does not occur.
CAUSE: The service request from the last write of the first block transfer
is being cleared by an ACKSR generated by the Multiplexer Channel when it
performs the IOCW fetch in State A for the second write request. The
channel should omit this ACKSR when the previous I/O order was a chained
read or write. However, the simulator is testing the order just fetched
(Write) instead of the order that has just completed (Write Chained).
RESOLUTION: Modify "mpx_service" (hp3000_mpx.c) to test the correct I/O
order in State A.
STATUS: Fixed in Release 2.
365 lines
19 KiB
C
365 lines
19 KiB
C
/* hp3000_io.h: HP 3000 device-to-IOP/MPX/SEL interface declarations
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Copyright (c) 2016, J. David Bryan
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of the author shall not be used
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in advertising or otherwise to promote the sale, use or other dealings in
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this Software without prior written authorization from the author.
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11-Jun-16 JDB Bit mask constants are now unsigned
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21-Mar-16 JDB Changed type of inbound_value of CNTLR_INTRF to HP_WORD
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20-Jan-16 JDB First release version
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11-Dec-12 JDB Created
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This file contains declarations used by I/O devices to interface with the HP
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3000 I/O Processor, Multiplexer Channel, and Selector Channel. It is
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required by any module that uses Device Information Blocks (DIBs).
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*/
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/* I/O bus signals.
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The INBOUND_SIGNAL and OUTBOUND_SIGNAL declarations mirror the hardware
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signals that are received and asserted, respectively, by the I/O interfaces
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on the IOP, selector/multiplexer channel, and power buses. A set of one or
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more signals forms an INBOUND_SET or OUTBOUND_SET that is sent to or returned
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from a device interface. Under simulation, the IOP and channels dispatch one
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INBOUND_SET to the target device interface per I/O cycle. The interface
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returns a combined OUTBOUND_SET and data value to the caller.
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Hardware allows parallel action for concurrent signals. Under simulation, a
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"concurrent" set of signals is processed sequentially by the interface in
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order of ascending numerical value.
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In addition, some signals must be asserted asynchronously, e.g., in response
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to an event service call. The IOP and channels provide asynchronous
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assertion via function calls for the INTREQ, REQ, SRn, and CHANSR signals.
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Implementation notes:
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1. The enumerations describe signals. A set of signals normally would be
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modeled as an unsigned integer, as a set may contain more than one
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signal. However, we define a set as the enumeration, as the "gdb"
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debugger has special provisions for an enumeration of discrete bit values
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and will display the set in "ORed" form.
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2. The null set -- NO_SIGNALS -- cannot be defined as an enumeration
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constant because the C language has a single name space for all
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enumeration constants, so separate "no inbound signals" and "no outbound
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signals" identifiers would be required, and because including them would
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require handlers for them in "switch" statements, which is undesirable.
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Therefore, we define NO_SIGNALS as an explicit integer 0, so that it is
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compatible with both enumerations.
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3. Outbound signal values are restricted to the upper 16 bits to allow the
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combined signal/data value to fit in 32 bits.
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4. Inbound and outbound signal definitions are separated to allow for future
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inbound expansion, if necessary.
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5. In hardware, the IOP encodes direct I/O commands as a 3-bit IOCMD signal
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set on the IOP bus. Each device interface decodes these signals into
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individual strobes to control the logic. Under simulation, the IOCMD
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values are decoded by the IOP into individual signals for inclusion in
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the INBOUND_SIGNAL set that is passed to the interfaces.
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6. The ACKSR signal must come before the programmed I/O and TOGGLESR
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signals, as they may set an interface's Service Request flip-flop.
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7. The READNEXTWD signal must come after PREADSTB, as the former overwrites
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the input data word used by the latter.
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8. The TOGGLEnXFER signals must come after PREADSTB and PWRITESTB and before
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READNEXTWD, so that the strobes can test the interface's Device End
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flip-flop before the toggles can reset it.
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9. The EOT signal must come after PREADSTB and PWRITESTB and before the
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TOGGLEnXFER signals. The former condition is required for the SCMB to
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return the correct EOT count, and the latter is required for the DS to
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set its End-of-Data flip-flop correctly.
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10. The SETINT signal must come before, and the TOGGLESIOOK signal must come
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after, the PSTATSTB signal so that the status of the interrupt request
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and SIO Busy flip-flops can be reported correctly.
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11. The CHANSO signal must come after all programmed I/O signals, as it is
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used by channel devices to assert CHANSR when needed.
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*/
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#define NO_SIGNALS 0 /* a universal "no signals are asserted" value */
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typedef enum { /* --- source of signal --- */
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DSETINT = 000000000001, /* SIN instruction */
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DCONTSTB = 000000000002, /* CIO instruction */
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DSTARTIO = 000000000004, /* SIO instruction */
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DWRITESTB = 000000000010, /* WIO instruction */
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DRESETINT = 000000000020, /* IXIT instruction */
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DSTATSTB = 000000000040, /* TIO instruction */
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DSETMASK = 000000000100, /* SMSK instruction */
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DREADSTB = 000000000200, /* RIO instruction */
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ACKSR = 000000000400, /* Multiplexer SR response */
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TOGGLESR = 000000001000, /* Read/Write/Control/End order */
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SETINT = 000000002000, /* Interrupt/End channel order */
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PCMD1 = 000000004000, /* Control channel order */
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PCONTSTB = 000000010000, /* Control channel order */
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SETJMP = 000000020000, /* Jump channel order */
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PSTATSTB = 000000040000, /* Sense channel order */
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PWRITESTB = 000000100000, /* Write channel order */
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PREADSTB = 000000200000, /* Read channel order */
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EOT = 000000400000, /* Read/Write channel order */
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TOGGLEINXFER = 000001000000, /* Read channel order */
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TOGGLEOUTXFER = 000002000000, /* Write channel order */
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READNEXTWD = 000004000000, /* Read channel order */
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TOGGLESIOOK = 000010000000, /* End channel order */
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DEVNODB = 000020000000, /* Multiplexer DRT Fetch */
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INTPOLLIN = 000040000000, /* IOP interrupt poll */
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XFERERROR = 000100000000, /* Multiplexer channel abort */
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CHANSO = 000200000000, /* Channel service call to interface */
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PFWARN = 000400000000 /* SET CPU POWERFAIL */
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/* = 001000000000 (available) */
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/* = 002000000000 (available) */
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/* = 004000000000 (available) */
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/* = 010000000000 (available) */
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/* = 020000000000 (available) */
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} INBOUND_SIGNAL;
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typedef INBOUND_SIGNAL INBOUND_SET; /* a set of INBOUND_SIGNALs */
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typedef enum { /* --- destination of signal --- */
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INTREQ = 000000200000, /* IOP, to request an external interrupt */
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INTACK = 000000400000, /* IOP, to acknowledge an external interrupt request */
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INTPOLLOUT = 000001000000, /* IOP, to clear an external interrupt request */
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DEVEND = 000002000000, /* Channel, to terminate a read/write order */
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JMPMET = 000004000000, /* Channel, to enable a Conditional Jump order */
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CHANACK = 000010000000, /* Channel, to acknowledge interface call */
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CHANSR = 000020000000, /* Selector channel, to request service */
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SRn = 000040000000 /* Multiplexer channel, to request service */
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/* = 000100000000 (available) */
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/* = 000200000000 (available) */
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/* = 000400000000 (available) */
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/* = 001000000000 (available) */
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/* = 002000000000 (available) */
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/* = 004000000000 (available) */
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/* = 010000000000 (available) */
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/* = 020000000000 (available) */
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} OUTBOUND_SIGNAL;
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typedef OUTBOUND_SIGNAL OUTBOUND_SET; /* a set of OUTBOUND_SIGNALs */
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typedef uint32 SIGNALS_DATA; /* a combined outbound signal set and data value */
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/* I/O macros.
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The following macros are useful in device interface signal handlers and unit
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service routines. The parameter definition symbols employed are:
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P = a priority set value
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S = an INBOUND_SET or OUTBOUND_SET value
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L = an INBOUND_SIGNAL value
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D = an outbound 16-bit data value
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C = a SIGNALS_DATA value
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B = a DIB value
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A priority set is an unsigned value, where each bit represents an assertion
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of some nature (e.g., I/O signals, interrupt requests, etc.), and the
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position of the bit represents its priority, which increases from LSB to MSB.
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The IOPRIORITY macro isolates the highest-priority bit from the set. It does
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this by ANDing the value with its two's complement; only the lowest-order bit
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will differ. For example (bits are numbered here from the LSB):
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priority set : ...0 0 1 1 0 1 0 0 0 0 0 0 (bits 6, 8, and 9 are asserted)
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one's compl : ...1 1 0 0 1 0 1 1 1 1 1 1
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two's compl : ...1 1 0 0 1 1 0 0 0 0 0 0
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ANDed value : ...0 0 0 0 0 1 0 0 0 0 0 0 (bit 6 is highest priority)
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If the request set indicates requests by 0 bits, rather than 1 bits, the
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IOPRIORITY macro must be called with the one's complement of the bits.
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The IONEXTSIG macro isolates the next inbound signal in sequence to process
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from the inbound signal set S.
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The IOCLEARSIG macro removes the processed signal L from the inbound signal
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set S.
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The IORETURN macro forms the 32-bit combined outbound signal set and data
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value to be returned by an interface from the signal set S and the 16-bit
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data value D.
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The IOSIGNALS macro isolates the outbound signal set from a 32-bit combined
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status and data value value C.
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The IODATA macro isolates the 16-bit data value from a 32-bit combined signal
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set and data value value C.
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Implementation notes:
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1. The IOPRIORITY macro implements two's complement explicitly, rather than
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using a signed negation, to be compatible with machines using a
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sign-magnitude integer format. "gcc" and "clang" optimize the complement
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and add to a single NEG instruction on x86 machines.
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*/
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#define IOPRIORITY(P) ((P) & ~(P) + 1)
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#define IONEXTSIG(S) ((INBOUND_SIGNAL) IOPRIORITY (S))
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#define IOCLEARSIG(S,L) S = (INBOUND_SIGNAL) ((S) ^ (L))
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#define IORETURN(S,D) ((SIGNALS_DATA) ((S) & ~D16_MASK | (D) & D16_MASK))
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#define IOSIGNALS(C) ((OUTBOUND_SET) ((C) & ~D16_MASK))
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#define IODATA(C) ((HP_WORD) ((C) & D16_MASK))
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/* I/O structures.
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The Device Information Block (DIB) allows devices to be relocated in the
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machine's I/O space. Each DIB contains a pointer to the device controller
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interface routine, values corresponding to hardware jumpers on the controller
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(e.g., device number), and flip-flops that indicate the interrupt and channel
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service states.
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For fast access during I/O, interrupt, and channel service requests, devices
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are accessed via indexed tables. The index employed depends on the
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application. For example, I/O commands are routed via a table that is
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indexed by device number. The tables are built during the instruction
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execution prelude by scanning the DIBs of all devices and placing pointers to
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the DIBs into the tables at the entries associated with the index values.
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Between execution runs, the user may reassign device properties, so the
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tables must be rebuilt each time.
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Implementation notes:
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1. The device number (DEVNO) bus is eight bits in width, and the CPU
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microcode, the IOP, and the device controllers all support device numbers
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up to 255. However, MPE limits the size of the device reference table to
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correspond with a device number of 127, while the CPU reserves memory
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that would correspond to device numbers 0-2. As a result, most device
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controllers provide only seven-bit configurable device numbers. One
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exception is the Selector Channel Maintenance Board. The Selector
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Channel diagnostic tests programmable device numbers > 127, which the
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SCMB provides via bits 8-15 of the counter/buffer register, although only
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seven preset jumpers are provided to set the standard device number for
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the board.
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2. The device_number, service_request_number, and interrupt_priority fields
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could be smaller than the defined 32-bit sizes, but IA-32 processors
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execute instructions with 32-bit operands much faster than those with
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16- or 8-bit operands.
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*/
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#define DEVNO_MAX 127 /* the maximum device number */
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#define DEVNO_MASK 0177u /* the mask for the device number */
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#define DEVNO_BASE 10 /* the radix for the device number */
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#define DEVNO_UNUSED D32_UMAX /* the unused device number indicator */
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#define INTMASK_MAX 15 /* the maximum interrupt mask number */
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#define INTMASK_MASK 017u /* the mask for the interrupt mask number */
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#define INTMASK_BASE 10 /* the radix for the interrupt mask number */
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#define INTMASK_D 0000000u /* the interrupt mask disabled always value */
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#define INTMASK_E 0177777u /* the interrupt mask enabled always value */
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#define INTMASK_UNUSED D32_UMAX /* the unused interrupt mask indicator */
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#define INTPRI_MAX 31 /* the maximum interrupt priority */
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#define INTPRI_MASK 037u /* the mask for the interrupt priority */
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#define INTPRI_BASE 10 /* the radix for the interrupt priority */
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#define INTPRI_UNUSED D32_UMAX /* the unused interrupt priority indicator */
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#define SRNO_MAX 15 /* the maximum service request number */
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#define SRNO_MASK 017u /* the mask for the service request number */
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#define SRNO_BASE 10 /* the radix for the service request number */
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#define SRNO_UNUSED D32_UMAX /* the unused service request number indicator */
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typedef struct dib DIB; /* an incomplete definition */
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typedef SIGNALS_DATA CNTLR_INTRF /* the I/O device controller interface function prototype */
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(DIB *dibptr, /* a pointer to the device information block */
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INBOUND_SET inbound_signals, /* a set of inbound signals */
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HP_WORD inbound_value); /* a 16-bit inbound value */
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struct dib { /* the Device Information Block */
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CNTLR_INTRF *io_interface; /* the controller I/O interface function pointer */
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uint32 device_number; /* the device number 0-255 */
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uint32 service_request_number; /* the service request number 0-15 */
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uint32 interrupt_priority; /* the interrupt priority 0-31 */
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uint32 interrupt_mask; /* the interrupt mask (16 bits) */
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uint32 card_index; /* the card index if multiple interfaces are supported */
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FLIP_FLOP interrupt_request; /* an interrupt has been requested */
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FLIP_FLOP interrupt_active; /* an interrupt is active */
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t_bool service_request; /* channel service has been requested */
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};
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/* Calibrated timer numbers */
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#define TMR_PCLK 0 /* the CPU process clock timer */
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#define TMR_CLK 1 /* the CLK system clock timer */
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#define TMR_ATC 2 /* the ATC input polling timer */
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/* CPU front panel command identifiers */
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typedef enum {
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Run, /* a run request */
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Cold_Load, /* a cold load request */
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Cold_Dump /* a cold dump request */
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} PANEL_TYPE;
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/* Global CPU state and functions */
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extern UNIT *cpu_pclk_uptr; /* pointer to the process clock unit */
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extern t_bool cpu_is_calibrated; /* TRUE if the process clock is calibrated */
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extern void cpu_front_panel (HP_WORD switch_reg, /* set the front panel switches as directed */
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PANEL_TYPE request);
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/* Global asynchronous signal assertion functions */
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extern void iop_assert_INTREQ (DIB *dib_pointer); /* assert the interrupt request signal */
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extern void mpx_assert_REQ (DIB *dib_pointer); /* assert the multiplexer channel request signal */
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extern void mpx_assert_SRn (DIB *dib_pointer); /* assert the multiplexer channel service request signal */
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extern void sel_assert_REQ (DIB *dib_pointer); /* assert the selector channel request signal */
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extern void sel_assert_CHANSR (DIB *dib_pointer); /* assert the selector channel service request signal */
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/* Global channel state */
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extern t_bool mpx_is_idle; /* TRUE if the multiplexer channel is idle */
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extern t_bool sel_is_idle; /* TRUE if the selector channel is idle */
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/* Global ATC state */
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extern t_bool atc_is_polling; /* TRUE if the ATC is polling for the simulation console */
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/* Global CLK functions */
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extern void clk_update_counter (void); /* update the system clock counter register */
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