190 lines
6.7 KiB
C
190 lines
6.7 KiB
C
/* pdp8_clk.c: PDP-8 real-time clock simulator
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Copyright (c) 1993-2012, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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clk real time clock
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18-Apr-12 RMS Added clock coscheduling
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18-Jun-07 RMS Added UNIT_IDLE flag
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01-Mar-03 RMS Aded SET/SHOW CLK FREQ support
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04-Oct-02 RMS Added DIB, device number support
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30-Dec-01 RMS Removed for generalized timers
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05-Sep-01 RMS Added terminal multiplexor support
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17-Jul-01 RMS Moved function prototype
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05-Mar-01 RMS Added clock calibration support
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Note: includes the IOT's for both the PDP-8/E and PDP-8/A clocks
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*/
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#include "pdp8_defs.h"
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extern int32 int_req, int_enable, dev_done, stop_inst;
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int32 clk_tps = 60; /* ticks/second */
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int32 tmxr_poll = 16000; /* term mux poll */
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int32 clk (int32 IR, int32 AC);
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t_stat clk_svc (UNIT *uptr);
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t_stat clk_reset (DEVICE *dptr);
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t_stat clk_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat clk_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc);
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/* CLK data structures
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clk_dev CLK device descriptor
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clk_unit CLK unit descriptor
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clk_reg CLK register list
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*/
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DIB clk_dib = { DEV_CLK, 1, { &clk } };
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UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), 16000 };
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REG clk_reg[] = {
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{ FLDATA (DONE, dev_done, INT_V_CLK) },
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{ FLDATA (ENABLE, int_enable, INT_V_CLK) },
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{ FLDATA (INT, int_req, INT_V_CLK) },
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{ DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },
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{ DRDATA (TPS, clk_tps, 8), PV_LEFT + REG_HRO },
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{ NULL }
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};
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MTAB clk_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 50, NULL, "50HZ",
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&clk_set_freq, NULL, NULL },
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{ MTAB_XTD|MTAB_VDV, 60, NULL, "60HZ",
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&clk_set_freq, NULL, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "FREQUENCY", NULL,
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NULL, &clk_show_freq, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", NULL, NULL, &show_dev },
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{ 0 }
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};
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DEVICE clk_dev = {
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"CLK", &clk_unit, clk_reg, clk_mod,
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1, 0, 0, 0, 0, 0,
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NULL, NULL, &clk_reset,
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NULL, NULL, NULL,
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&clk_dib, 0
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};
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/* IOT routine
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IOT's 6131-6133 are the PDP-8/E clock
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IOT's 6135-6137 are the PDP-8/A clock
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*/
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int32 clk (int32 IR, int32 AC)
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{
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switch (IR & 07) { /* decode IR<9:11> */
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case 1: /* CLEI */
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int_enable = int_enable | INT_CLK; /* enable clk ints */
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int_req = INT_UPDATE; /* update interrupts */
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return AC;
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case 2: /* CLDI */
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int_enable = int_enable & ~INT_CLK; /* disable clk ints */
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int_req = int_req & ~INT_CLK; /* update interrupts */
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return AC;
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case 3: /* CLSC */
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if (dev_done & INT_CLK) { /* flag set? */
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dev_done = dev_done & ~INT_CLK; /* clear flag */
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int_req = int_req & ~INT_CLK; /* clear int req */
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return IOT_SKP + AC;
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}
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return AC;
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case 5: /* CLLE */
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if (AC & 1) /* test AC<11> */
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int_enable = int_enable | INT_CLK;
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else int_enable = int_enable & ~INT_CLK;
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int_req = INT_UPDATE; /* update interrupts */
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return AC;
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case 6: /* CLCL */
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dev_done = dev_done & ~INT_CLK; /* clear flag */
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int_req = int_req & ~INT_CLK; /* clear int req */
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return AC;
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case 7: /* CLSK */
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return (dev_done & INT_CLK)? IOT_SKP + AC: AC;
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default:
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return (stop_inst << IOT_V_REASON) + AC;
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} /* end switch */
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}
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/* Unit service */
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t_stat clk_svc (UNIT *uptr)
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{
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int32 t;
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dev_done = dev_done | INT_CLK; /* set done */
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int_req = INT_UPDATE; /* update interrupts */
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t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
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tmxr_poll = t; /* set mux poll */
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sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat clk_reset (DEVICE *dptr)
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{
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int32 t;
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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dev_done = dev_done & ~INT_CLK; /* clear done, int */
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int_req = int_req & ~INT_CLK;
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int_enable = int_enable & ~INT_CLK; /* clear enable */
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if (!sim_is_running) { /* RESET (not CAF)? */
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t = sim_rtcn_init (clk_unit.wait, TMR_CLK);
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sim_activate (&clk_unit, t); /* activate unit */
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tmxr_poll = t;
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}
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return SCPE_OK;
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}
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/* Set frequency */
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t_stat clk_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc)
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{
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if (cptr)
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return SCPE_ARG;
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if ((val != 50) && (val != 60))
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return SCPE_IERR;
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clk_tps = val;
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return SCPE_OK;
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}
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/* Show frequency */
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t_stat clk_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc)
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{
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fprintf (st, (clk_tps == 50)? "50Hz": "60Hz");
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return SCPE_OK;
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}
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