998 lines
45 KiB
C
998 lines
45 KiB
C
/* hp2100_dq.c: HP 2100 12565A Disc Interface and 2883 disc drive simulator
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Copyright (c) 1993-2006, Bill McDermith
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Copyright (c) 2004-2017, J. David Bryan
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the names of the authors shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from the authors.
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DQ 12565A Disc Interface and 2883 disc drive
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03-Aug-17 JDB Changed perror call for I/O errors to cprintf
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11-Jul-17 JDB Renamed "ibl_copy" to "cpu_ibl"
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09-Mar-17 JDB Deprecated LOCKED/WRITEENABLED for PROTECT/UNPROTECT
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27-Feb-17 JDB ibl_copy no longer returns a status code
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13-May-16 JDB Modified for revised SCP API function parameter types
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30-Dec-14 JDB Added S-register parameters to ibl_copy
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24-Dec-14 JDB Added casts for explicit downward conversions
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18-Dec-12 MP Now calls sim_activate_time to get remaining seek time
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09-May-12 JDB Separated assignments from conditional expressions
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10-Feb-12 JDB Deprecated DEVNO in favor of SC
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28-Mar-11 JDB Tidied up signal handling
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26-Oct-10 JDB Changed I/O signal handler for revised signal model
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10-Aug-08 JDB Added REG_FIT to register variables < 32-bit size
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26-Jun-08 JDB Rewrote device I/O to model backplane signals
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28-Dec-06 JDB Added ioCRS state to I/O decoders
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01-Mar-05 JDB Added SET UNLOAD/LOAD
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07-Oct-04 JDB Fixed enable/disable from either device
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Shortened xtime from 5 to 3 (drive avg 156KW/second)
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Fixed not ready/any error status
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Fixed RAR model
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21-Apr-04 RMS Fixed typo in boot loader (found by Dave Bryan)
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26-Apr-04 RMS Fixed SFS x,C and SFC x,C
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Fixed SR setting in IBL
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Revised IBL loader
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Implemented DMA SRQ (follows FLG)
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25-Apr-03 RMS Fixed bug in status check
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10-Nov-02 RMS Added boot command, rebuilt like 12559/13210
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09-Jan-02 WOM Copied dp driver and mods for 2883
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Reference:
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- 12565A Disc Interface Kit Operating and Service Manual
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(12565-90003, August 1973)
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Differences between 12559/13210 and 12565 controllers:
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- 12565 stops transfers on address miscompares; 12559/13210 only stops writes
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- 12565 does not set error on positioner busy
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- 12565 does not set positioner busy if already on cylinder
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- 12565 does not need eoc logic, it will hit an invalid head number
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The controller's "Record Address Register" (RAR) contains the CHS address of
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the last Position or Load Address command executed. The RAR is shared among
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all drives on the controller. In addition, each drive has an internal
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position register that contains the last cylinder and head position
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transferred to the drive during Position command execution (sector operations
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always start with the RAR sector position).
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In a real drive, the address field of the sector under the head is read and
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compared to the RAR. When they match, the target sector is under the head
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and is ready for reading or writing. If a match doesn't occur, an Address
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Error is indicated. In the simulator, the address field is obtained from the
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drive's current position register during a read, i.e., the "on-disc" address
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field is assumed to match the current position.
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The following implemented behaviors have been inferred from secondary sources
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(diagnostics, operating system drivers, etc.), due to absent or contradictory
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authoritative information; future correction may be needed:
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1. Read Address command starts at the sector number in the RAR.
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*/
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#include "hp2100_defs.h"
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#include "hp2100_cpu.h"
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#define UNIT_V_WLK (UNIT_V_UF + 0) /* write locked */
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#define UNIT_V_UNLOAD (UNIT_V_UF + 1) /* heads unloaded */
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#define UNIT_WLK (1 << UNIT_V_WLK)
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#define UNIT_UNLOAD (1 << UNIT_V_UNLOAD)
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#define FNC u3 /* saved function */
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#define DRV u4 /* drive number (DC) */
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#define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write prot */
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#define DQ_N_NUMWD 7
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#define DQ_NUMWD (1 << DQ_N_NUMWD) /* words/sector */
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#define DQ_NUMSC 23 /* sectors/track */
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#define DQ_NUMSF 20 /* tracks/cylinder */
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#define DQ_NUMCY 203 /* cylinders/disk */
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#define DQ_SIZE (DQ_NUMSF * DQ_NUMCY * DQ_NUMSC * DQ_NUMWD)
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#define DQ_NUMDRV 2 /* # drives */
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/* Command word */
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#define CW_V_FNC 12 /* function */
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#define CW_M_FNC 017
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#define CW_GETFNC(x) (((x) >> CW_V_FNC) & CW_M_FNC)
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/* 000 (unused) */
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#define FNC_STA 001 /* status check */
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#define FNC_RCL 002 /* recalibrate */
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#define FNC_SEEK 003 /* seek */
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#define FNC_RD 004 /* read */
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#define FNC_WD 005 /* write */
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#define FNC_RA 006 /* read address */
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#define FNC_WA 007 /* write address */
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#define FNC_CHK 010 /* check */
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#define FNC_LA 013 /* load address */
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#define FNC_AS 014 /* address skip */
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#define FNC_SEEK1 020 /* fake - seek1 */
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#define FNC_SEEK2 021 /* fake - seek2 */
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#define FNC_SEEK3 022 /* fake - seek3 */
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#define FNC_CHK1 023 /* fake - check1 */
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#define FNC_LA1 024 /* fake - ldaddr1 */
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#define CW_V_DRV 0 /* drive */
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#define CW_M_DRV 01
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#define CW_GETDRV(x) (((x) >> CW_V_DRV) & CW_M_DRV)
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/* Disk address words */
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#define DA_V_CYL 0 /* cylinder */
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#define DA_M_CYL 0377
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#define DA_GETCYL(x) (((x) >> DA_V_CYL) & DA_M_CYL)
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#define DA_V_HD 8 /* head */
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#define DA_M_HD 037
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#define DA_GETHD(x) (((x) >> DA_V_HD) & DA_M_HD)
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#define DA_V_SC 0 /* sector */
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#define DA_M_SC 037
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#define DA_GETSC(x) (((x) >> DA_V_SC) & DA_M_SC)
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#define DA_CKMASK 0777 /* check mask */
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/* Status in dqc_sta[drv] - (d) = dynamic */
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#define STA_DID 0000200 /* drive ID (d) */
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#define STA_NRDY 0000100 /* not ready (d) */
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#define STA_EOC 0000040 /* end of cylinder */
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#define STA_AER 0000020 /* addr error */
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#define STA_FLG 0000010 /* flagged */
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#define STA_BSY 0000004 /* seeking */
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#define STA_DTE 0000002 /* data error */
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#define STA_ERR 0000001 /* any error */
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#define STA_ANYERR (STA_NRDY | STA_EOC | STA_AER | STA_FLG | STA_DTE)
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struct {
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FLIP_FLOP command; /* cch command flip-flop */
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FLIP_FLOP control; /* cch control flip-flop */
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FLIP_FLOP flag; /* cch flag flip-flop */
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FLIP_FLOP flagbuf; /* cch flag buffer flip-flop */
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} dqc = { CLEAR, CLEAR, CLEAR, CLEAR };
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int32 dqc_busy = 0; /* cch xfer */
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int32 dqc_cnt = 0; /* check count */
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int32 dqc_stime = 100; /* seek time */
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int32 dqc_ctime = 100; /* command time */
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int32 dqc_xtime = 3; /* xfer time */
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int32 dqc_dtime = 2; /* dch time */
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struct {
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FLIP_FLOP command; /* dch command flip-flop */
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FLIP_FLOP control; /* dch control flip-flop */
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FLIP_FLOP flag; /* dch flag flip-flop */
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FLIP_FLOP flagbuf; /* dch flag buffer flip-flop */
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} dqd = { CLEAR, CLEAR, CLEAR, CLEAR };
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int32 dqd_obuf = 0, dqd_ibuf = 0; /* dch buffers */
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int32 dqc_obuf = 0; /* cch buffers */
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int32 dqd_xfer = 0; /* xfer in prog */
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int32 dqd_wval = 0; /* write data valid */
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int32 dq_ptr = 0; /* buffer ptr */
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uint8 dqc_rarc = 0; /* RAR cylinder */
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uint8 dqc_rarh = 0; /* RAR head */
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uint8 dqc_rars = 0; /* RAR sector */
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uint8 dqc_ucyl[DQ_NUMDRV] = { 0 }; /* unit cylinder */
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uint8 dqc_uhed[DQ_NUMDRV] = { 0 }; /* unit head */
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uint16 dqc_sta[DQ_NUMDRV] = { 0 }; /* unit status */
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uint16 dqxb[DQ_NUMWD]; /* sector buffer */
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DEVICE dqd_dev, dqc_dev;
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IOHANDLER dqdio;
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IOHANDLER dqcio;
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t_stat dqc_svc (UNIT *uptr);
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t_stat dqd_svc (UNIT *uptr);
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t_stat dqc_reset (DEVICE *dptr);
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t_stat dqc_attach (UNIT *uptr, CONST char *cptr);
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t_stat dqc_detach (UNIT* uptr);
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t_stat dqc_load_unload (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
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t_stat dqc_boot (int32 unitno, DEVICE *dptr);
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void dq_god (int32 fnc, int32 drv, int32 time);
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void dq_goc (int32 fnc, int32 drv, int32 time);
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/* DQD data structures
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dqd_dev DQD device descriptor
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dqd_unit DQD unit list
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dqd_reg DQD register list
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*/
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DIB dq_dib[] = {
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{ &dqdio, DQD },
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{ &dqcio, DQC }
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};
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#define dqd_dib dq_dib[0]
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#define dqc_dib dq_dib[1]
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UNIT dqd_unit = { UDATA (&dqd_svc, 0, 0) };
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REG dqd_reg[] = {
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{ ORDATA (IBUF, dqd_ibuf, 16) },
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{ ORDATA (OBUF, dqd_obuf, 16) },
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{ BRDATA (DBUF, dqxb, 8, 16, DQ_NUMWD) },
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{ DRDATA (BPTR, dq_ptr, DQ_N_NUMWD) },
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{ FLDATA (CMD, dqd.command, 0) },
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{ FLDATA (CTL, dqd.control, 0) },
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{ FLDATA (FLG, dqd.flag, 0) },
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{ FLDATA (FBF, dqd.flagbuf, 0) },
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{ FLDATA (XFER, dqd_xfer, 0) },
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{ FLDATA (WVAL, dqd_wval, 0) },
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{ ORDATA (SC, dqd_dib.select_code, 6), REG_HRO },
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{ ORDATA (DEVNO, dqd_dib.select_code, 6), REG_HRO },
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{ NULL }
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};
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MTAB dqd_mod [] = {
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/* Entry Flags Value Print String Match String Validation Display Descriptor */
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/* ------------------- ----- ------------ ------------ ------------ ------------- ---------------- */
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{ MTAB_XDV, 2u, "SC", "SC", &hp_set_dib, &hp_show_dib, (void *) &dq_dib },
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{ MTAB_XDV | MTAB_NMO, ~2u, "DEVNO", "DEVNO", &hp_set_dib, &hp_show_dib, (void *) &dq_dib },
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{ 0 }
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};
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DEVICE dqd_dev = {
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"DQD", &dqd_unit, dqd_reg, dqd_mod,
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1, 10, DQ_N_NUMWD, 1, 8, 16,
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NULL, NULL, &dqc_reset,
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NULL, NULL, NULL,
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&dqd_dib, DEV_DISABLE
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};
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/* DQC data structures
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dqc_dev DQC device descriptor
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dqc_unit DQC unit list
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dqc_reg DQC register list
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dqc_mod DQC modifier list
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*/
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UNIT dqc_unit[] = {
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{ UDATA (&dqc_svc, UNIT_FIX | UNIT_ATTABLE | UNIT_ROABLE |
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UNIT_DISABLE | UNIT_UNLOAD, DQ_SIZE) },
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{ UDATA (&dqc_svc, UNIT_FIX | UNIT_ATTABLE | UNIT_ROABLE |
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UNIT_DISABLE | UNIT_UNLOAD, DQ_SIZE) }
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};
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REG dqc_reg[] = {
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{ ORDATA (OBUF, dqc_obuf, 16) },
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{ ORDATA (BUSY, dqc_busy, 2), REG_RO },
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{ ORDATA (CNT, dqc_cnt, 9) },
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{ FLDATA (CMD, dqc.command, 0) },
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{ FLDATA (CTL, dqc.control, 0) },
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{ FLDATA (FLG, dqc.flag, 0) },
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{ FLDATA (FBF, dqc.flagbuf, 0) },
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{ DRDATA (RARC, dqc_rarc, 8), PV_RZRO | REG_FIT },
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{ DRDATA (RARH, dqc_rarh, 5), PV_RZRO | REG_FIT },
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{ DRDATA (RARS, dqc_rars, 5), PV_RZRO | REG_FIT },
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{ BRDATA (CYL, dqc_ucyl, 10, 8, DQ_NUMDRV), PV_RZRO },
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{ BRDATA (HED, dqc_uhed, 10, 5, DQ_NUMDRV), PV_RZRO },
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{ BRDATA (STA, dqc_sta, 8, 16, DQ_NUMDRV) },
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{ DRDATA (CTIME, dqc_ctime, 24), PV_LEFT },
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{ DRDATA (DTIME, dqc_dtime, 24), PV_LEFT },
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{ DRDATA (STIME, dqc_stime, 24), PV_LEFT },
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{ DRDATA (XTIME, dqc_xtime, 24), REG_NZ + PV_LEFT },
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{ URDATA (UFNC, dqc_unit[0].FNC, 8, 8, 0,
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DQ_NUMDRV, REG_HRO) },
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{ ORDATA (SC, dqc_dib.select_code, 6), REG_HRO },
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{ ORDATA (DEVNO, dqc_dib.select_code, 6), REG_HRO },
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{ NULL }
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};
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MTAB dqc_mod [] = {
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/* Mask Value Match Value Print String Match String Validation Display Descriptor */
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/* ------------ ------------ ----------------- --------------- ----------------- ------- ---------- */
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{ UNIT_UNLOAD, UNIT_UNLOAD, "heads unloaded", "UNLOADED", &dqc_load_unload, NULL, NULL },
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{ UNIT_UNLOAD, 0, "heads loaded", "LOADED", &dqc_load_unload, NULL, NULL },
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{ UNIT_WLK, UNIT_WLK, "protected", "PROTECT", NULL, NULL, NULL },
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{ UNIT_WLK, 0, "unprotected", "UNPROTECT", NULL, NULL, NULL },
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{ UNIT_WLK, UNIT_WLK, NULL, "LOCKED", NULL, NULL, NULL },
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{ UNIT_WLK, 0, NULL, "WRITEENABLED", NULL, NULL, NULL },
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/* Entry Flags Value Print String Match String Validation Display Descriptor */
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/* ------------------- ----- ------------ ------------ ------------ ------------- ---------------- */
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{ MTAB_XDV, 2u, "SC", "SC", &hp_set_dib, &hp_show_dib, (void *) &dq_dib },
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{ MTAB_XDV | MTAB_NMO, ~2u, "DEVNO", "DEVNO", &hp_set_dib, &hp_show_dib, (void *) &dq_dib },
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{ 0 }
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};
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DEVICE dqc_dev = {
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"DQC", dqc_unit, dqc_reg, dqc_mod,
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DQ_NUMDRV, 8, 24, 1, 8, 16,
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NULL, NULL, &dqc_reset,
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&dqc_boot, &dqc_attach, &dqc_detach,
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&dqc_dib, DEV_DISABLE
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};
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/* Data channel I/O signal handler */
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uint32 dqdio (DIB *dibptr, IOCYCLE signal_set, uint32 stat_data)
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{
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IOSIGNAL signal;
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IOCYCLE working_set = IOADDSIR (signal_set); /* add ioSIR if needed */
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while (working_set) {
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signal = IONEXT (working_set); /* isolate next signal */
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switch (signal) { /* dispatch I/O signal */
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case ioCLF: /* clear flag flip-flop */
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dqd.flag = dqd.flagbuf = CLEAR;
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break;
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case ioSTF: /* set flag flip-flop */
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case ioENF: /* enable flag */
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dqd.flag = dqd.flagbuf = SET;
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break;
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case ioSFC: /* skip if flag is clear */
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setstdSKF (dqd);
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break;
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case ioSFS: /* skip if flag is set */
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setstdSKF (dqd);
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break;
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case ioIOI: /* I/O data input */
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stat_data = IORETURN (SCPE_OK, dqd_ibuf); /* merge in return status */
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break;
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case ioIOO: /* I/O data output */
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dqd_obuf = IODATA (stat_data); /* clear supplied status */
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if (!dqc_busy || dqd_xfer)
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dqd_wval = 1; /* if !overrun, valid */
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break;
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case ioPOPIO: /* power-on preset to I/O */
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dqd.flag = dqd.flagbuf = SET; /* set flag and flag buffer */
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dqd_obuf = 0; /* clear output buffer */
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break;
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case ioCRS: /* control reset */
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dqd.command = CLEAR; /* clear command */
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/* fall into CLC handler */
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case ioCLC: /* clear control flip-flop */
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dqd.control = CLEAR; /* clear control */
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dqd_xfer = 0; /* clr xfer */
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break;
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case ioSTC: /* set control flip-flop */
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dqd.command = SET; /* set ctl, cmd */
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dqd.control = SET;
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if (dqc_busy && !dqd_xfer) /* overrun? */
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dqc_sta[dqc_busy - 1] |= STA_DTE;
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break;
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case ioSIR: /* set interrupt request */
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setstdPRL (dqd); /* set standard PRL signal */
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setstdIRQ (dqd); /* set standard IRQ signal */
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setstdSRQ (dqd); /* set standard SRQ signal */
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break;
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case ioIAK: /* interrupt acknowledge */
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dqd.flagbuf = CLEAR;
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break;
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default: /* all other signals */
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break; /* are ignored */
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}
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working_set = working_set & ~signal; /* remove current signal from set */
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}
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return stat_data;
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}
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/* Command channel I/O signal handler.
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Implementation notes:
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1. The input buffer register is not connected to the disc controller.
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Pullups on the card and an inversion result in reading zeros when IOI is
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signalled.
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*/
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uint32 dqcio (DIB *dibptr, IOCYCLE signal_set, uint32 stat_data)
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{
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int32 fnc, drv;
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IOSIGNAL signal;
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IOCYCLE working_set = IOADDSIR (signal_set); /* add ioSIR if needed */
|
|
|
|
while (working_set) {
|
|
signal = IONEXT (working_set); /* isolate next signal */
|
|
|
|
switch (signal) { /* dispatch I/O signal */
|
|
|
|
case ioCLF: /* clear flag flip-flop */
|
|
dqc.flag = dqc.flagbuf = CLEAR;
|
|
break;
|
|
|
|
|
|
case ioSTF: /* set flag flip-flop */
|
|
case ioENF: /* enable flag */
|
|
dqc.flag = dqc.flagbuf = SET;
|
|
break;
|
|
|
|
|
|
case ioSFC: /* skip if flag is clear */
|
|
setstdSKF (dqc);
|
|
break;
|
|
|
|
|
|
case ioSFS: /* skip if flag is set */
|
|
setstdSKF (dqc);
|
|
break;
|
|
|
|
|
|
case ioIOI: /* I/O data input */
|
|
stat_data = IORETURN (SCPE_OK, 0); /* no data */
|
|
break;
|
|
|
|
|
|
case ioIOO: /* I/O data output */
|
|
dqc_obuf = IODATA (stat_data); /* clear supplied status */
|
|
break;
|
|
|
|
|
|
case ioPOPIO: /* power-on preset to I/O */
|
|
dqc.flag = dqc.flagbuf = SET; /* set flag and flag buffer */
|
|
dqc_obuf = 0; /* clear output buffer */
|
|
break;
|
|
|
|
|
|
case ioCRS: /* control reset */
|
|
case ioCLC: /* clear control flip-flop */
|
|
dqc.command = CLEAR; /* clear command */
|
|
dqc.control = CLEAR; /* clear control */
|
|
|
|
if (dqc_busy)
|
|
sim_cancel (&dqc_unit[dqc_busy - 1]);
|
|
|
|
sim_cancel (&dqd_unit); /* cancel dch */
|
|
dqd_xfer = 0; /* clr dch xfer */
|
|
dqc_busy = 0; /* clr busy */
|
|
break;
|
|
|
|
|
|
case ioSTC: /* set control flip-flop */
|
|
dqc.control = SET; /* set ctl */
|
|
|
|
if (!dqc.command) { /* cmd clr? */
|
|
dqc.command = SET; /* set cmd */
|
|
drv = CW_GETDRV (dqc_obuf); /* get fnc, drv */
|
|
fnc = CW_GETFNC (dqc_obuf); /* from cmd word */
|
|
|
|
switch (fnc) { /* case on fnc */
|
|
case FNC_SEEK: case FNC_RCL: /* seek, recal */
|
|
case FNC_CHK: /* check */
|
|
dqc_sta[drv] = 0; /* clear status */
|
|
case FNC_STA: case FNC_LA: /* rd sta, load addr */
|
|
dq_god (fnc, drv, dqc_dtime); /* sched dch xfer */
|
|
break;
|
|
case FNC_RD: case FNC_WD: /* read, write */
|
|
case FNC_RA: case FNC_WA: /* rd addr, wr addr */
|
|
case FNC_AS: /* address skip */
|
|
dq_goc (fnc, drv, dqc_ctime); /* sched drive */
|
|
break;
|
|
} /* end case */
|
|
} /* end if !CMD */
|
|
break;
|
|
|
|
|
|
case ioSIR: /* set interrupt request */
|
|
setstdPRL (dqc); /* set standard PRL signal */
|
|
setstdIRQ (dqc); /* set standard IRQ signal */
|
|
setstdSRQ (dqc); /* set standard SRQ signal */
|
|
break;
|
|
|
|
|
|
case ioIAK: /* interrupt acknowledge */
|
|
dqc.flagbuf = CLEAR;
|
|
break;
|
|
|
|
|
|
default: /* all other signals */
|
|
break; /* are ignored */
|
|
}
|
|
|
|
working_set = working_set & ~signal; /* remove current signal from set */
|
|
}
|
|
return stat_data;
|
|
}
|
|
|
|
|
|
/* Start data channel operation */
|
|
|
|
void dq_god (int32 fnc, int32 drv, int32 time)
|
|
{
|
|
dqd_unit.DRV = drv; /* save unit */
|
|
dqd_unit.FNC = fnc; /* save function */
|
|
sim_activate (&dqd_unit, time);
|
|
return;
|
|
}
|
|
|
|
/* Start controller operation */
|
|
|
|
void dq_goc (int32 fnc, int32 drv, int32 time)
|
|
{
|
|
int32 t;
|
|
|
|
t = sim_activate_time (&dqc_unit[drv]);
|
|
|
|
if (t) { /* still seeking? */
|
|
sim_cancel (&dqc_unit[drv]); /* cancel */
|
|
time = time + t; /* include seek time */
|
|
}
|
|
dqc_sta[drv] = 0; /* clear status */
|
|
dq_ptr = 0; /* init buf ptr */
|
|
dqc_busy = drv + 1; /* set busy */
|
|
dqd_xfer = 1; /* xfer in prog */
|
|
dqc_unit[drv].FNC = fnc; /* save function */
|
|
sim_activate (&dqc_unit[drv], time); /* activate unit */
|
|
return;
|
|
}
|
|
|
|
/* Data channel unit service
|
|
|
|
This routine handles the data channel transfers. It also handles
|
|
data transfers that are blocked by seek in progress.
|
|
|
|
uptr->DRV = target drive
|
|
uptr->FNC = target function
|
|
|
|
Seek substates
|
|
seek - transfer cylinder
|
|
seek1 - transfer head/surface, sched drive
|
|
Recalibrate substates
|
|
rcl - clear cyl/head/surface, sched drive
|
|
Load address
|
|
la - transfer cylinder
|
|
la1 - transfer head/surface, finish operation
|
|
Status check - transfer status, finish operation
|
|
Check data
|
|
chk - transfer sector count, sched drive
|
|
*/
|
|
|
|
t_stat dqd_svc (UNIT *uptr)
|
|
{
|
|
int32 drv, st;
|
|
|
|
drv = uptr->DRV; /* get drive no */
|
|
|
|
switch (uptr->FNC) { /* case function */
|
|
|
|
case FNC_LA: /* arec, need cyl */
|
|
case FNC_SEEK: /* seek, need cyl */
|
|
if (dqd.command) { /* dch active? */
|
|
dqc_rarc = DA_GETCYL (dqd_obuf); /* set RAR from cyl word */
|
|
dqd_wval = 0; /* clr data valid */
|
|
dqd.command = CLEAR; /* clr dch cmd */
|
|
dqdio (&dqd_dib, ioENF, 0); /* set dch flg */
|
|
if (uptr->FNC == FNC_LA) uptr->FNC = FNC_LA1;
|
|
else uptr->FNC = FNC_SEEK1; /* advance state */
|
|
}
|
|
sim_activate (uptr, dqc_xtime); /* no, wait more */
|
|
break;
|
|
|
|
case FNC_LA1: /* arec, need hd/sec */
|
|
case FNC_SEEK1: /* seek, need hd/sec */
|
|
if (dqd.command) { /* dch active? */
|
|
dqc_rarh = DA_GETHD (dqd_obuf); /* set RAR from head */
|
|
dqc_rars = DA_GETSC (dqd_obuf); /* set RAR from sector */
|
|
dqd_wval = 0; /* clr data valid */
|
|
dqd.command = CLEAR; /* clr dch cmd */
|
|
dqdio (&dqd_dib, ioENF, 0); /* set dch flg */
|
|
if (uptr->FNC == FNC_LA1) {
|
|
dqc.command = CLEAR; /* clr cch cmd */
|
|
dqcio (&dqc_dib, ioENF, 0); /* set cch flg */
|
|
break; /* done if Load Address */
|
|
}
|
|
if (sim_is_active (&dqc_unit[drv])) break; /* if busy, seek check */
|
|
st = abs (dqc_rarc - dqc_ucyl[drv]) * dqc_stime;
|
|
if (st == 0) st = dqc_xtime; /* if on cyl, min time */
|
|
else dqc_sta[drv] = dqc_sta[drv] | STA_BSY; /* set busy */
|
|
dqc_ucyl[drv] = dqc_rarc; /* transfer RAR */
|
|
dqc_uhed[drv] = dqc_rarh;
|
|
sim_activate (&dqc_unit[drv], st); /* schedule op */
|
|
dqc_unit[drv].FNC = FNC_SEEK2; /* advance state */
|
|
}
|
|
else sim_activate (uptr, dqc_xtime); /* no, wait more */
|
|
break;
|
|
|
|
case FNC_RCL: /* recalibrate */
|
|
dqc_rarc = dqc_rarh = dqc_rars = 0; /* clear RAR */
|
|
if (sim_is_active (&dqc_unit[drv])) break; /* ignore if busy */
|
|
st = dqc_ucyl[drv] * dqc_stime; /* calc diff */
|
|
if (st == 0) st = dqc_xtime; /* if on cyl, min time */
|
|
else dqc_sta[drv] = dqc_sta[drv] | STA_BSY; /* set busy */
|
|
sim_activate (&dqc_unit[drv], st); /* schedule drive */
|
|
dqc_ucyl[drv] = dqc_uhed[drv] = 0; /* clear drive pos */
|
|
dqc_unit[drv].FNC = FNC_SEEK2; /* advance state */
|
|
break;
|
|
|
|
case FNC_STA: /* read status */
|
|
if (dqd.command) { /* dch active? */
|
|
if ((dqc_unit[drv].flags & UNIT_UNLOAD) == 0) /* drive up? */
|
|
dqd_ibuf = dqc_sta[drv] & ~STA_DID;
|
|
else dqd_ibuf = STA_NRDY;
|
|
if (dqd_ibuf & STA_ANYERR) /* errors? set flg */
|
|
dqd_ibuf = dqd_ibuf | STA_ERR;
|
|
if (drv) dqd_ibuf = dqd_ibuf | STA_DID;
|
|
dqc.command = CLEAR; /* clr cch cmd */
|
|
dqd.command = CLEAR; /* clr dch cmd */
|
|
dqdio (&dqd_dib, ioENF, 0); /* set dch flg */
|
|
dqc_sta[drv] = dqc_sta[drv] & ~STA_ANYERR; /* clr sta flags */
|
|
}
|
|
else sim_activate (uptr, dqc_xtime); /* wait more */
|
|
break;
|
|
|
|
case FNC_CHK: /* check, need cnt */
|
|
if (dqd.command) { /* dch active? */
|
|
dqc_cnt = dqd_obuf & DA_CKMASK; /* get count */
|
|
dqd_wval = 0; /* clr data valid */
|
|
dq_goc (FNC_CHK1, drv, dqc_ctime); /* sched drv */
|
|
}
|
|
else sim_activate (uptr, dqc_xtime); /* wait more */
|
|
break;
|
|
|
|
default:
|
|
return SCPE_IERR;
|
|
}
|
|
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Drive unit service
|
|
|
|
This routine handles the data transfers.
|
|
|
|
Seek substates
|
|
seek2 - done
|
|
Recalibrate substate
|
|
rcl1 - done
|
|
Check data substates
|
|
chk1 - finish operation
|
|
Read
|
|
Read address
|
|
Address skip (read without header check)
|
|
Write
|
|
Write address
|
|
*/
|
|
|
|
#define GETDA(x,y,z) \
|
|
(((((x) * DQ_NUMSF) + (y)) * DQ_NUMSC) + (z)) * DQ_NUMWD
|
|
|
|
t_stat dqc_svc (UNIT *uptr)
|
|
{
|
|
int32 da, drv, err;
|
|
|
|
err = 0; /* assume no err */
|
|
drv = uptr - dqc_unit; /* get drive no */
|
|
if (uptr->flags & UNIT_UNLOAD) { /* drive down? */
|
|
dqc.command = CLEAR; /* clr cch cmd */
|
|
dqcio (&dqc_dib, ioENF, 0); /* set cch flg */
|
|
dqc_sta[drv] = 0; /* clr status */
|
|
dqc_busy = 0; /* ctlr is free */
|
|
dqd_xfer = dqd_wval = 0;
|
|
return SCPE_OK;
|
|
}
|
|
switch (uptr->FNC) { /* case function */
|
|
|
|
case FNC_SEEK2: /* seek done */
|
|
if (dqc_ucyl[drv] >= DQ_NUMCY) { /* out of range? */
|
|
dqc_sta[drv] = dqc_sta[drv] | STA_BSY | STA_ERR; /* seek check */
|
|
dqc_ucyl[drv] = 0; /* seek to cyl 0 */
|
|
}
|
|
else dqc_sta[drv] = dqc_sta[drv] & ~STA_BSY; /* drive not busy */
|
|
case FNC_SEEK3:
|
|
if (dqc_busy || dqc.flag) { /* ctrl busy? */
|
|
uptr->FNC = FNC_SEEK3; /* next state */
|
|
sim_activate (uptr, dqc_xtime); /* ctrl busy? wait */
|
|
}
|
|
else {
|
|
dqc.command = CLEAR; /* clr cch cmd */
|
|
dqcio (&dqc_dib, ioENF, 0); /* set cch flg */
|
|
}
|
|
return SCPE_OK;
|
|
|
|
case FNC_RA: /* read addr */
|
|
if (!dqd.command) break; /* dch clr? done */
|
|
if (dq_ptr == 0) dqd_ibuf = dqc_ucyl[drv]; /* 1st word? */
|
|
else if (dq_ptr == 1) { /* second word? */
|
|
dqd_ibuf = (dqc_uhed[drv] << DA_V_HD) | /* use drive head */
|
|
(dqc_rars << DA_V_SC); /* and RAR sector */
|
|
dqc_rars = (dqc_rars + 1) % DQ_NUMSC; /* incr sector */
|
|
}
|
|
else break;
|
|
dq_ptr = dq_ptr + 1;
|
|
dqd.command = CLEAR; /* clr dch cmd */
|
|
dqdio (&dqd_dib, ioENF, 0); /* set dch flg */
|
|
sim_activate (uptr, dqc_xtime); /* sched next word */
|
|
return SCPE_OK;
|
|
|
|
case FNC_AS: /* address skip */
|
|
case FNC_RD: /* read */
|
|
case FNC_CHK1: /* check */
|
|
if (dq_ptr == 0) { /* new sector? */
|
|
if (!dqd.command && (uptr->FNC != FNC_CHK1)) break;
|
|
if ((dqc_rarc != dqc_ucyl[drv]) || /* RAR cyl miscompare? */
|
|
(dqc_rarh != dqc_uhed[drv]) || /* RAR head miscompare? */
|
|
(dqc_rars >= DQ_NUMSC)) { /* bad sector? */
|
|
dqc_sta[drv] = dqc_sta[drv] | STA_AER; /* no record found err */
|
|
break;
|
|
}
|
|
if (dqc_rarh >= DQ_NUMSF) { /* bad head? */
|
|
dqc_sta[drv] = dqc_sta[drv] | STA_EOC; /* end of cyl err */
|
|
break;
|
|
}
|
|
da = GETDA (dqc_rarc, dqc_rarh, dqc_rars); /* calc disk addr */
|
|
dqc_rars = (dqc_rars + 1) % DQ_NUMSC; /* incr sector */
|
|
if (dqc_rars == 0) /* wrap? incr head */
|
|
dqc_uhed[drv] = dqc_rarh = dqc_rarh + 1;
|
|
err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET);
|
|
if (err)
|
|
break;
|
|
fxread (dqxb, sizeof (int16), DQ_NUMWD, uptr->fileref);
|
|
err = ferror (uptr->fileref);
|
|
if (err)
|
|
break;
|
|
}
|
|
dqd_ibuf = dqxb[dq_ptr++]; /* get word */
|
|
if (dq_ptr >= DQ_NUMWD) { /* end of sector? */
|
|
if (uptr->FNC == FNC_CHK1) { /* check? */
|
|
dqc_cnt = (dqc_cnt - 1) & DA_CKMASK; /* decr count */
|
|
if (dqc_cnt == 0) break; /* if zero, done */
|
|
}
|
|
dq_ptr = 0; /* wrap buf ptr */
|
|
}
|
|
if (dqd.command && dqd_xfer) { /* dch on, xfer? */
|
|
dqdio (&dqd_dib, ioENF, 0); /* set flag */
|
|
}
|
|
dqd.command = CLEAR; /* clr dch cmd */
|
|
sim_activate (uptr, dqc_xtime); /* sched next word */
|
|
return SCPE_OK;
|
|
|
|
case FNC_WA: /* write address */
|
|
case FNC_WD: /* write */
|
|
if (dq_ptr == 0) { /* sector start? */
|
|
if (!dqd.command && !dqd_wval) break; /* xfer done? */
|
|
if (uptr->flags & UNIT_WPRT) { /* write protect? */
|
|
dqc_sta[drv] = dqc_sta[drv] | STA_FLG;
|
|
break; /* done */
|
|
}
|
|
if ((dqc_rarc != dqc_ucyl[drv]) || /* RAR cyl miscompare? */
|
|
(dqc_rarh != dqc_uhed[drv]) || /* RAR head miscompare? */
|
|
(dqc_rars >= DQ_NUMSC)) { /* bad sector? */
|
|
dqc_sta[drv] = dqc_sta[drv] | STA_AER; /* no record found err */
|
|
break;
|
|
}
|
|
if (dqc_rarh >= DQ_NUMSF) { /* bad head? */
|
|
dqc_sta[drv] = dqc_sta[drv] | STA_EOC; /* end of cyl err */
|
|
break;
|
|
}
|
|
}
|
|
dqxb[dq_ptr++] = dqd_wval ? (uint16) dqd_obuf : 0; /* store word/fill */
|
|
dqd_wval = 0; /* clr data valid */
|
|
if (dq_ptr >= DQ_NUMWD) { /* buffer full? */
|
|
da = GETDA (dqc_rarc, dqc_rarh, dqc_rars); /* calc disk addr */
|
|
dqc_rars = (dqc_rars + 1) % DQ_NUMSC; /* incr sector */
|
|
if (dqc_rars == 0) /* wrap? incr head */
|
|
dqc_uhed[drv] = dqc_rarh = dqc_rarh + 1;
|
|
err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET);
|
|
if (err)
|
|
break;
|
|
fxwrite (dqxb, sizeof (int16), DQ_NUMWD, uptr->fileref);
|
|
err = ferror (uptr->fileref);
|
|
if (err)
|
|
break;
|
|
dq_ptr = 0;
|
|
}
|
|
if (dqd.command && dqd_xfer) { /* dch on, xfer? */
|
|
dqdio (&dqd_dib, ioENF, 0); /* set flag */
|
|
}
|
|
dqd.command = CLEAR; /* clr dch cmd */
|
|
sim_activate (uptr, dqc_xtime); /* sched next word */
|
|
return SCPE_OK;
|
|
|
|
default:
|
|
return SCPE_IERR;
|
|
} /* end case fnc */
|
|
|
|
dqc.command = CLEAR; /* clr cch cmd */
|
|
dqcio (&dqc_dib, ioENF, 0); /* set cch flg */
|
|
dqc_busy = 0; /* ctlr is free */
|
|
dqd_xfer = dqd_wval = 0;
|
|
if (err != 0) { /* error? */
|
|
cprintf ("%s simulator DQ disc I/O error: %s\n", /* then report the error to the console */
|
|
sim_name, strerror (errno));
|
|
|
|
clearerr (uptr->fileref); /* clear the error */
|
|
return SCPE_IOERR;
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Reset routine */
|
|
|
|
t_stat dqc_reset (DEVICE *dptr)
|
|
{
|
|
int32 drv;
|
|
DIB *dibptr = (DIB *) dptr->ctxt; /* DIB pointer */
|
|
|
|
hp_enbdis_pair (dptr, /* make pair cons */
|
|
(dptr == &dqd_dev)? &dqc_dev: &dqd_dev);
|
|
|
|
if (sim_switches & SWMASK ('P')) { /* initialization reset? */
|
|
dqd_ibuf = 0; /* clear buffers */
|
|
dqd_obuf = 0;
|
|
dqc_obuf = 0; /* clear buffer */
|
|
dqc_rarc = dqc_rarh = dqc_rars = 0; /* clear RAR */
|
|
}
|
|
|
|
IOPRESET (dibptr); /* PRESET device (does not use PON) */
|
|
|
|
dqc_busy = 0; /* reset controller state */
|
|
dqd_xfer = 0;
|
|
dqd_wval = 0;
|
|
dq_ptr = 0;
|
|
|
|
sim_cancel (&dqd_unit); /* cancel dch */
|
|
|
|
for (drv = 0; drv < DQ_NUMDRV; drv++) { /* loop thru drives */
|
|
sim_cancel (&dqc_unit[drv]); /* cancel activity */
|
|
dqc_unit[drv].FNC = 0; /* clear function */
|
|
dqc_ucyl[drv] = dqc_uhed[drv] = 0; /* clear drive pos */
|
|
dqc_sta[drv] = 0; /* clear status */
|
|
}
|
|
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Attach routine */
|
|
|
|
t_stat dqc_attach (UNIT *uptr, CONST char *cptr)
|
|
{
|
|
t_stat r;
|
|
|
|
r = attach_unit (uptr, cptr); /* attach unit */
|
|
if (r == SCPE_OK) dqc_load_unload (uptr, 0, NULL, NULL);/* if OK, load heads */
|
|
return r;
|
|
}
|
|
|
|
/* Detach routine */
|
|
|
|
t_stat dqc_detach (UNIT* uptr)
|
|
{
|
|
dqc_load_unload (uptr, UNIT_UNLOAD, NULL, NULL); /* unload heads */
|
|
return detach_unit (uptr); /* detach unit */
|
|
}
|
|
|
|
/* Load and unload heads */
|
|
|
|
t_stat dqc_load_unload (UNIT *uptr, int32 value, CONST char *cptr, void *desc)
|
|
{
|
|
if ((uptr->flags & UNIT_ATT) == 0) return SCPE_UNATT; /* must be attached to load */
|
|
if (value == UNIT_UNLOAD) /* unload heads? */
|
|
uptr->flags = uptr->flags | UNIT_UNLOAD; /* indicate unload */
|
|
else uptr->flags = uptr->flags & ~UNIT_UNLOAD; /* indicate load */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* 7900/7901/2883/2884 bootstrap routine (HP 12992A ROM) */
|
|
|
|
const BOOT_ROM dq_rom = {
|
|
0102501, /*ST LIA 1 ; get switches */
|
|
0106501, /* LIB 1 */
|
|
0013765, /* AND D7 ; isolate hd */
|
|
0005750, /* BLF,CLE,SLB */
|
|
0027741, /* JMP RD */
|
|
0005335, /* RBR,SLB,ERB ; <13>->E, set = 2883 */
|
|
0027717, /* JMP IS */
|
|
0102611, /*LP OTA CC ; do 7900 status to */
|
|
0103711, /* STC CC,C ; clear first seek */
|
|
0102310, /* SFS DC */
|
|
0027711, /* JMP *-1 */
|
|
0002004, /* INA ; get next drive */
|
|
0053765, /* CPA D7 ; all cleared? */
|
|
0002001, /* RSS */
|
|
0027707, /* JMP LP */
|
|
0067761, /*IS LDB SEEKC ; get seek comnd */
|
|
0106610, /* OTB DC ; issue cyl addr (0) */
|
|
0103710, /* STC DC,C ; to dch */
|
|
0106611, /* OTB CC ; seek cmd */
|
|
0103711, /* STC CC,C ; to cch */
|
|
0102310, /* SFS DC ; addr wd ok? */
|
|
0027724, /* JMP *-1 ; no, wait */
|
|
0006400, /* CLB */
|
|
0102501, /* LIA 1 ; get switches */
|
|
0002051, /* SEZ,SLA,RSS ; subchan = 1 or ISS */
|
|
0047770, /* ADB BIT9 ; head 2 */
|
|
0106610, /* OTB DC ; head/sector */
|
|
0103710, /* STC DC,C ; to dch */
|
|
0102311, /* SFS CC ; seek done? */
|
|
0027734, /* JMP *-1 ; no, wait */
|
|
0063731, /* LDA ISSRD ; get read read */
|
|
0002341, /* SEZ,CCE,RSS ; iss disc? */
|
|
0001100, /* ARS ; no, make 7900 read */
|
|
0067776, /*RD LDB DMACW ; DMA control */
|
|
0106606, /* OTB 6 */
|
|
0067762, /* LDB ADDR1 ; memory addr */
|
|
0077741, /* STB RD ; make non re-executable */
|
|
0106602, /* OTB 2 */
|
|
0102702, /* STC 2 ; flip DMA ctrl */
|
|
0067764, /* LDB COUNT ; word count */
|
|
0106602, /* OTB 2 */
|
|
0002041, /* SEZ,RSS */
|
|
0027766, /* JMP NW */
|
|
0102611, /* OTA CC ; to cch */
|
|
0103710, /* STC DC,C ; start dch */
|
|
0103706, /* STC 6,C ; start DMA */
|
|
0103711, /* STC CC,C ; start cch */
|
|
0037773, /* ISZ SK */
|
|
0027773, /* JMP SK */
|
|
0030000, /*SEEKC 030000 */
|
|
0102011, /*ADDR1 102011 */
|
|
0102055, /*ADDR2 102055 */
|
|
0164000, /*COUNT -6144. */
|
|
0000007, /*D7 7 */
|
|
0106710, /*NW CLC DC ; set 'next wd is cmd' flag */
|
|
0001720, /* ALF,ALF ; move to head number loc */
|
|
0001000, /*BIT9 ALS */
|
|
0103610, /* OTA DC,C ; output cold load cmd */
|
|
0103706, /* STC 6,C ; start DMA */
|
|
0102310, /* SFS DC ; done? */
|
|
0027773, /* JMP *-1 ; no, wait */
|
|
0117763, /*XT JSB ADDR2,I ; start program */
|
|
0120010, /*DMACW 120000+DC */
|
|
0000000 /* -ST */
|
|
};
|
|
|
|
t_stat dqc_boot (int32 unitno, DEVICE *dptr)
|
|
{
|
|
const int32 dev = dqd_dib.select_code; /* data chan select code */
|
|
|
|
if (unitno != 0) /* boot supported on drive unit 0 only */
|
|
return SCPE_NOFNC; /* report "Command not allowed" if attempted */
|
|
|
|
cpu_ibl (dq_rom, dev, IBL_OPT, /* copy the boot ROM to memory and configure */
|
|
IBL_DQ | IBL_SET_SC (dev)); /* the S register accordingly */
|
|
|
|
return SCPE_OK;
|
|
}
|