755 lines
34 KiB
C
755 lines
34 KiB
C
/* pdp8_rx.c: RX8E/RX01, RX28/RX02 floppy disk simulator
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Copyright (c) 1993-2013, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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rx RX8E/RX01, RX28/RX02 floppy disk
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17-Sep-13 RMS Changed to use central set_bootpc routine
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03-Sep-13 RMS Added explicit void * cast
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15-May-06 RMS Fixed bug in autosize attach (Dave Gesswein)
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04-Jan-04 RMS Changed sim_fsize calling sequence
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05-Nov-03 RMS Fixed bug in RX28 read status (Charles Dickman)
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26-Oct-03 RMS Cleaned up buffer copy code, fixed double density write
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25-Apr-03 RMS Revised for extended file support
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14-Mar-03 RMS Fixed variable size interaction with save/restore
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03-Mar-03 RMS Fixed autosizing
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08-Oct-02 RMS Added DIB, device number support
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Fixed reset to work with disabled device
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15-Sep-02 RMS Added RX28/RX02 support
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06-Jan-02 RMS Changed enable/disable support
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30-Nov-01 RMS Added read only unit, extended SET/SHOW support
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24-Nov-01 RMS Converted FLG to array
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17-Jul-01 RMS Fixed warning from VC++ 6
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26-Apr-01 RMS Added device enable/disable support
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13-Apr-01 RMS Revised for register arrays
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14-Apr-99 RMS Changed t_addr to unsigned
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15-Aug-96 RMS Fixed bug in LCD
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An RX01 diskette consists of 77 tracks, each with 26 sectors of 128B.
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An RX02 diskette consists of 77 tracks, each with 26 sectors of 128B
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(single density) or 256B (double density). Tracks are numbered 0-76,
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sectors 1-26. The RX8E (RX28) can store data in 8b mode or 12b mode.
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In 8b mode, the controller reads or writes 128 bytes (128B or 256B)
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per sector. In 12b mode, it reads or writes 64 (64 or 128) 12b words
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per sector. The 12b words are bit packed into the first 96 (192) bytes
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of the sector; the last 32 (64) bytes are zeroed on writes.
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*/
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#include "pdp8_defs.h"
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#define RX_NUMTR 77 /* tracks/disk */
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#define RX_M_TRACK 0377
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#define RX_NUMSC 26 /* sectors/track */
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#define RX_M_SECTOR 0177 /* cf Jones!! */
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#define RX_NUMBY 128 /* bytes/sector */
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#define RX2_NUMBY 256
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#define RX_NUMWD (RX_NUMBY / 2) /* words/sector */
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#define RX2_NUMWD (RX2_NUMBY / 2)
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#define RX_SIZE (RX_NUMTR * RX_NUMSC * RX_NUMBY) /* bytes/disk */
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#define RX2_SIZE (RX_NUMTR * RX_NUMSC * RX2_NUMBY)
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#define RX_NUMDR 2 /* drives/controller */
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#define RX_M_NUMDR 01
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#define UNIT_V_WLK (UNIT_V_UF + 0) /* write locked */
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#define UNIT_V_DEN (UNIT_V_UF + 1) /* double density */
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#define UNIT_V_AUTO (UNIT_V_UF + 2) /* autosize */
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#define UNIT_WLK (1u << UNIT_V_WLK)
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#define UNIT_DEN (1u << UNIT_V_DEN)
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#define UNIT_AUTO (1u << UNIT_V_AUTO)
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#define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write protect */
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#define IDLE 0 /* idle state */
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#define CMD8 1 /* 8b cmd, ho next */
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#define RWDS 2 /* rw, sect next */
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#define RWDT 3 /* rw, track next */
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#define RWXFR 4 /* rw, transfer */
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#define FILL 5 /* fill buffer */
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#define EMPTY 6 /* empty buffer */
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#define SDCNF 7 /* set dens, conf next */
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#define SDXFR 8 /* set dens, transfer */
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#define CMD_COMPLETE 9 /* set done next */
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#define INIT_COMPLETE 10 /* init compl next */
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#define RXCS_V_FUNC 1 /* function */
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#define RXCS_M_FUNC 7
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#define RXCS_FILL 0 /* fill buffer */
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#define RXCS_EMPTY 1 /* empty buffer */
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#define RXCS_WRITE 2 /* write sector */
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#define RXCS_READ 3 /* read sector */
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#define RXCS_SDEN 4 /* set density (RX28) */
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#define RXCS_RXES 5 /* read status */
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#define RXCS_WRDEL 6 /* write del data */
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#define RXCS_ECODE 7 /* read error code */
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#define RXCS_DRV 0020 /* drive */
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#define RXCS_MODE 0100 /* mode */
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#define RXCS_MAINT 0200 /* maintenance */
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#define RXCS_DEN 0400 /* density (RX28) */
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#define RXCS_GETFNC(x) (((x) >> RXCS_V_FUNC) & RXCS_M_FUNC)
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#define RXES_CRC 0001 /* CRC error NI */
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#define RXES_ID 0004 /* init done */
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#define RXES_RX02 0010 /* RX02 (RX28) */
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#define RXES_DERR 0020 /* density err (RX28) */
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#define RXES_DEN 0040 /* density (RX28) */
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#define RXES_DD 0100 /* deleted data */
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#define RXES_DRDY 0200 /* drive ready */
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#define TRACK u3 /* current track */
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#define READ_RXDBR ((rx_csr & RXCS_MODE)? AC | (rx_dbr & 0377): rx_dbr)
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#define CALC_DA(t,s,b) (((t) * RX_NUMSC) + ((s) - 1)) * b
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extern int32 int_req, int_enable, dev_done;
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int32 rx_28 = 0; /* controller type */
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int32 rx_tr = 0; /* xfer ready flag */
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int32 rx_err = 0; /* error flag */
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int32 rx_csr = 0; /* control/status */
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int32 rx_dbr = 0; /* data buffer */
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int32 rx_esr = 0; /* error status */
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int32 rx_ecode = 0; /* error code */
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int32 rx_track = 0; /* desired track */
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int32 rx_sector = 0; /* desired sector */
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int32 rx_state = IDLE; /* controller state */
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int32 rx_cwait = 100; /* command time */
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int32 rx_swait = 10; /* seek, per track */
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int32 rx_xwait = 1; /* tr set time */
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int32 rx_stopioe = 0; /* stop on error */
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uint8 rx_buf[RX2_NUMBY] = { 0 }; /* sector buffer */
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int32 rx_bptr = 0; /* buffer pointer */
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DEVICE rx_dev;
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int32 rx (int32 IR, int32 AC);
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t_stat rx_svc (UNIT *uptr);
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t_stat rx_reset (DEVICE *dptr);
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t_stat rx_boot (int32 unitno, DEVICE *dptr);
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t_stat rx_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat rx_attach (UNIT *uptr, char *cptr);
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void rx_cmd (void);
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void rx_done (int32 esr_flags, int32 new_ecode);
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t_stat rx_settype (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat rx_showtype (FILE *st, UNIT *uptr, int32 val, void *desc);
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/* RX8E data structures
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rx_dev RX device descriptor
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rx_unit RX unit list
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rx_reg RX register list
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rx_mod RX modifier list
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*/
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DIB rx_dib = { DEV_RX, 1, { &rx } };
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UNIT rx_unit[] = {
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{ UDATA (&rx_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF+
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UNIT_ROABLE, RX_SIZE) },
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{ UDATA (&rx_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF+
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UNIT_ROABLE, RX_SIZE) }
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};
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REG rx_reg[] = {
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{ ORDATA (RXCS, rx_csr, 12) },
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{ ORDATA (RXDB, rx_dbr, 12) },
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{ ORDATA (RXES, rx_esr, 12) },
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{ ORDATA (RXERR, rx_ecode, 8) },
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{ ORDATA (RXTA, rx_track, 8) },
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{ ORDATA (RXSA, rx_sector, 8) },
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{ DRDATA (STAPTR, rx_state, 4), REG_RO },
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{ DRDATA (BUFPTR, rx_bptr, 8) },
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{ FLDATA (TR, rx_tr, 0) },
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{ FLDATA (ERR, rx_err, 0) },
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{ FLDATA (DONE, dev_done, INT_V_RX) },
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{ FLDATA (ENABLE, int_enable, INT_V_RX) },
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{ FLDATA (INT, int_req, INT_V_RX) },
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{ DRDATA (CTIME, rx_cwait, 24), PV_LEFT },
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{ DRDATA (STIME, rx_swait, 24), PV_LEFT },
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{ DRDATA (XTIME, rx_xwait, 24), PV_LEFT },
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{ FLDATA (STOP_IOE, rx_stopioe, 0) },
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{ BRDATA (SBUF, rx_buf, 8, 8, RX2_NUMBY) },
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{ FLDATA (RX28, rx_28, 0), REG_HRO },
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{ URDATA (CAPAC, rx_unit[0].capac, 10, T_ADDR_W, 0,
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RX_NUMDR, REG_HRO | PV_LEFT) },
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{ ORDATA (DEVNUM, rx_dib.dev, 6), REG_HRO },
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{ NULL }
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};
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MTAB rx_mod[] = {
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{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
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{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
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{ MTAB_XTD | MTAB_VDV, 1, NULL, "RX28", &rx_settype, NULL, NULL },
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{ MTAB_XTD | MTAB_VDV, 0, NULL, "RX8E", &rx_settype, NULL, NULL },
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{ MTAB_XTD | MTAB_VDV, 0, "TYPE", NULL, NULL, &rx_showtype, NULL },
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{ (UNIT_DEN+UNIT_ATT), UNIT_ATT, "single density", NULL, NULL },
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{ (UNIT_DEN+UNIT_ATT), (UNIT_DEN+UNIT_ATT), "double density", NULL, NULL },
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{ (UNIT_AUTO+UNIT_DEN+UNIT_ATT), 0, "single density", NULL, NULL },
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{ (UNIT_AUTO+UNIT_DEN+UNIT_ATT), UNIT_DEN, "double density", NULL, NULL },
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{ (UNIT_AUTO+UNIT_ATT), UNIT_AUTO, "autosize", NULL, NULL },
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{ UNIT_AUTO, UNIT_AUTO, NULL, "AUTOSIZE", NULL },
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{ (UNIT_AUTO+UNIT_DEN), 0, NULL, "SINGLE", &rx_set_size },
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{ (UNIT_AUTO+UNIT_DEN), UNIT_DEN, NULL, "DOUBLE", &rx_set_size },
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{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
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&set_dev, &show_dev, NULL },
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{ 0 }
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};
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DEVICE rx_dev = {
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"RX", rx_unit, rx_reg, rx_mod,
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RX_NUMDR, 8, 20, 1, 8, 8,
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NULL, NULL, &rx_reset,
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&rx_boot, &rx_attach, NULL,
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&rx_dib, DEV_DISABLE
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};
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/* IOT routine */
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int32 rx (int32 IR, int32 AC)
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{
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int32 drv = ((rx_csr & RXCS_DRV)? 1: 0); /* get drive number */
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switch (IR & 07) { /* decode IR<9:11> */
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case 0: /* unused */
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break;
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case 1: /* LCD */
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if (rx_state != IDLE) /* ignore if busy */
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return AC;
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dev_done = dev_done & ~INT_RX; /* clear done, int */
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int_req = int_req & ~INT_RX;
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rx_tr = rx_err = 0; /* clear flags */
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rx_bptr = 0; /* clear buf pointer */
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if (rx_28 && (AC & RXCS_MODE)) { /* RX28 8b mode? */
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rx_dbr = rx_csr = AC & 0377; /* save 8b */
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rx_tr = 1; /* xfer is ready */
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rx_state = CMD8; /* wait for part 2 */
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}
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else {
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rx_dbr = rx_csr = AC; /* save new command */
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rx_cmd (); /* issue command */
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}
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return 0; /* clear AC */
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case 2: /* XDR */
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switch (rx_state & 017) { /* case on state */
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case EMPTY: /* emptying buffer */
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sim_activate (&rx_unit[drv], rx_xwait); /* sched xfer */
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return READ_RXDBR; /* return data reg */
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case CMD8: /* waiting for cmd */
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rx_dbr = AC & 0377;
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rx_csr = (rx_csr & 0377) | ((AC & 017) << 8);
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rx_cmd ();
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break;
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case RWDS:case RWDT:case FILL:case SDCNF: /* waiting for data */
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rx_dbr = AC; /* save data */
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sim_activate (&rx_unit[drv], rx_xwait); /* schedule */
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break;
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default: /* default */
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return READ_RXDBR; /* return data reg */
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}
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break;
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case 3: /* STR */
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if (rx_tr != 0) {
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rx_tr = 0;
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return IOT_SKP + AC;
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}
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break;
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case 4: /* SER */
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if (rx_err != 0) {
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rx_err = 0;
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return IOT_SKP + AC;
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}
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break;
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case 5: /* SDN */
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if ((dev_done & INT_RX) != 0) {
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dev_done = dev_done & ~INT_RX;
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int_req = int_req & ~INT_RX;
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return IOT_SKP + AC;
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}
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break;
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case 6: /* INTR */
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if (AC & 1)
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int_enable = int_enable | INT_RX;
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else int_enable = int_enable & ~INT_RX;
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int_req = INT_UPDATE;
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break;
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case 7: /* INIT */
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rx_reset (&rx_dev); /* reset device */
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break;
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} /* end case pulse */
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return AC;
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}
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void rx_cmd (void)
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{
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int32 drv = ((rx_csr & RXCS_DRV)? 1: 0); /* get drive number */
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switch (RXCS_GETFNC (rx_csr)) { /* decode command */
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case RXCS_FILL:
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rx_state = FILL; /* state = fill */
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rx_tr = 1; /* xfer is ready */
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rx_esr = rx_esr & RXES_ID; /* clear errors */
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break;
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case RXCS_EMPTY:
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rx_state = EMPTY; /* state = empty */
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rx_esr = rx_esr & RXES_ID; /* clear errors */
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sim_activate (&rx_unit[drv], rx_xwait); /* sched xfer */
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break;
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case RXCS_READ: case RXCS_WRITE: case RXCS_WRDEL:
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rx_state = RWDS; /* state = get sector */
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rx_tr = 1; /* xfer is ready */
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rx_esr = rx_esr & RXES_ID; /* clear errors */
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break;
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case RXCS_SDEN:
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if (rx_28) { /* RX28? */
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rx_state = SDCNF; /* state = get conf */
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rx_tr = 1; /* xfer is ready */
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rx_esr = rx_esr & RXES_ID; /* clear errors */
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break;
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} /* else fall thru */
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default:
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rx_state = CMD_COMPLETE; /* state = cmd compl */
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sim_activate (&rx_unit[drv], rx_cwait); /* sched done */
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break;
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} /* end switch func */
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return;
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}
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/* Unit service; the action to be taken depends on the transfer state:
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IDLE Should never get here
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RWDS Save sector, set TR, set RWDT
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RWDT Save track, set RWXFR
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RWXFR Read/write buffer
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FILL copy dbr to rx_buf[rx_bptr], advance ptr
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if rx_bptr > max, finish command, else set tr
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EMPTY if rx_bptr > max, finish command, else
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copy rx_buf[rx_bptr] to dbr, advance ptr, set tr
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CMD_COMPLETE copy requested data to dbr, finish command
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INIT_COMPLETE read drive 0, track 1, sector 1 to buffer, finish command
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For RWDT and CMD_COMPLETE, the input argument is the selected drive;
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otherwise, it is drive 0.
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*/
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t_stat rx_svc (UNIT *uptr)
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{
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int32 i, func, byptr, bps, wps;
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int8 *fbuf = (int8 *) uptr->filebuf;
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uint32 da;
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#define PTR12(x) (((x) + (x) + (x)) >> 1)
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if (rx_28 && (uptr->flags & UNIT_DEN)) /* RX28 and double density? */
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bps = RX2_NUMBY; /* double bytes/sector */
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else bps = RX_NUMBY; /* RX8E, normal count */
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wps = bps / 2;
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func = RXCS_GETFNC (rx_csr); /* get function */
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switch (rx_state) { /* case on state */
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case IDLE: /* idle */
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return SCPE_IERR;
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case EMPTY: /* empty buffer */
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if (rx_csr & RXCS_MODE) { /* 8b xfer? */
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if (rx_bptr >= bps) { /* done? */
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rx_done (0, 0); /* set done */
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break; /* and exit */
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}
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rx_dbr = rx_buf[rx_bptr]; /* else get data */
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}
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else {
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byptr = PTR12 (rx_bptr); /* 12b xfer */
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if (rx_bptr >= wps) { /* done? */
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rx_done (0, 0); /* set done */
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break; /* and exit */
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}
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rx_dbr = (rx_bptr & 1)? /* get data */
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((rx_buf[byptr] & 017) << 8) | rx_buf[byptr + 1]:
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(rx_buf[byptr] << 4) | ((rx_buf[byptr + 1] >> 4) & 017);
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}
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rx_bptr = rx_bptr + 1;
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rx_tr = 1;
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break;
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case FILL: /* fill buffer */
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if (rx_csr & RXCS_MODE) { /* 8b xfer? */
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rx_buf[rx_bptr] = rx_dbr; /* fill buffer */
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rx_bptr = rx_bptr + 1;
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if (rx_bptr < bps) /* if more, set xfer */
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rx_tr = 1;
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else rx_done (0, 0); /* else done */
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}
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else {
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byptr = PTR12 (rx_bptr); /* 12b xfer */
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if (rx_bptr & 1) { /* odd or even? */
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rx_buf[byptr] = (rx_buf[byptr] & 0360) | ((rx_dbr >> 8) & 017);
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rx_buf[byptr + 1] = rx_dbr & 0377;
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}
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else {
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rx_buf[byptr] = (rx_dbr >> 4) & 0377;
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rx_buf[byptr + 1] = (rx_dbr & 017) << 4;
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}
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rx_bptr = rx_bptr + 1;
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if (rx_bptr < wps) /* if more, set xfer */
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rx_tr = 1;
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else {
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for (i = PTR12 (wps); i < bps; i++)
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rx_buf[i] = 0; /* else fill sector */
|
|
rx_done (0, 0); /* set done */
|
|
}
|
|
}
|
|
break;
|
|
|
|
case RWDS: /* wait for sector */
|
|
rx_sector = rx_dbr & RX_M_SECTOR; /* save sector */
|
|
rx_tr = 1; /* set xfer ready */
|
|
rx_state = RWDT; /* advance state */
|
|
return SCPE_OK;
|
|
|
|
case RWDT: /* wait for track */
|
|
rx_track = rx_dbr & RX_M_TRACK; /* save track */
|
|
rx_state = RWXFR;
|
|
sim_activate (uptr, /* sched done */
|
|
rx_swait * abs (rx_track - uptr->TRACK));
|
|
return SCPE_OK;
|
|
|
|
case RWXFR: /* transfer */
|
|
if ((uptr->flags & UNIT_BUF) == 0) { /* not buffered? */
|
|
rx_done (0, 0110); /* done, error */
|
|
return IORETURN (rx_stopioe, SCPE_UNATT);
|
|
}
|
|
if (rx_track >= RX_NUMTR) { /* bad track? */
|
|
rx_done (0, 0040); /* done, error */
|
|
break;
|
|
}
|
|
uptr->TRACK = rx_track; /* now on track */
|
|
if ((rx_sector == 0) || (rx_sector > RX_NUMSC)) { /* bad sect? */
|
|
rx_done (0, 0070); /* done, error */
|
|
break;
|
|
}
|
|
if (rx_28 && /* RX28? */
|
|
(((uptr->flags & UNIT_DEN) != 0) ^
|
|
((rx_csr & RXCS_DEN) != 0))) { /* densities agree? */
|
|
rx_done (RXES_DERR, 0240); /* no, error */
|
|
break;
|
|
}
|
|
da = CALC_DA (rx_track, rx_sector, bps); /* get disk address */
|
|
if (func == RXCS_WRDEL) /* del data? */
|
|
rx_esr = rx_esr | RXES_DD;
|
|
if (func == RXCS_READ) { /* read? */
|
|
for (i = 0; i < bps; i++) rx_buf[i] = fbuf[da + i];
|
|
}
|
|
else { /* write */
|
|
if (uptr->flags & UNIT_WPRT) { /* locked? */
|
|
rx_done (0, 0100); /* done, error */
|
|
break;
|
|
}
|
|
for (i = 0; i < bps; i++)
|
|
fbuf[da + i] = rx_buf[i];
|
|
da = da + bps;
|
|
if (da > uptr->hwmark)
|
|
uptr->hwmark = da;
|
|
}
|
|
rx_done (0, 0); /* done */
|
|
break;
|
|
|
|
case SDCNF: /* confirm set density */
|
|
if ((rx_dbr & 0377) != 0111) { /* confirmed? */
|
|
rx_done (0, 0250); /* no, error */
|
|
break;
|
|
}
|
|
rx_state = SDXFR; /* next state */
|
|
sim_activate (uptr, rx_cwait * 100); /* schedule operation */
|
|
break;
|
|
|
|
case SDXFR: /* erase disk */
|
|
for (i = 0; i < (int32) uptr->capac; i++)
|
|
fbuf[i] = 0;
|
|
uptr->hwmark = uptr->capac;
|
|
if (rx_csr & RXCS_DEN)
|
|
uptr->flags = uptr->flags | UNIT_DEN;
|
|
else uptr->flags = uptr->flags & ~UNIT_DEN;
|
|
rx_done (0, 0);
|
|
break;
|
|
|
|
case CMD_COMPLETE: /* command complete */
|
|
if (func == RXCS_ECODE) { /* read ecode? */
|
|
rx_dbr = rx_ecode; /* set dbr */
|
|
rx_done (0, -1); /* don't update */
|
|
}
|
|
else if (rx_28) { /* no, read sta; RX28? */
|
|
rx_esr = rx_esr & ~RXES_DERR; /* assume dens match */
|
|
if (((uptr->flags & UNIT_DEN) != 0) ^ /* densities mismatch? */
|
|
((rx_csr & RXCS_DEN) != 0))
|
|
rx_done (RXES_DERR, 0240); /* yes, error */
|
|
else rx_done (0, 0); /* no, ok */
|
|
}
|
|
else rx_done (0, 0); /* RX8E status */
|
|
break;
|
|
|
|
case INIT_COMPLETE: /* init complete */
|
|
rx_unit[0].TRACK = 1; /* drive 0 to trk 1 */
|
|
rx_unit[1].TRACK = 0; /* drive 1 to trk 0 */
|
|
if ((rx_unit[0].flags & UNIT_BUF) == 0) { /* not buffered? */
|
|
rx_done (RXES_ID, 0010); /* init done, error */
|
|
break;
|
|
}
|
|
da = CALC_DA (1, 1, bps); /* track 1, sector 1 */
|
|
for (i = 0; i < bps; i++) /* read sector */
|
|
rx_buf[i] = fbuf[da + i];
|
|
rx_done (RXES_ID, 0); /* set done */
|
|
if ((rx_unit[1].flags & UNIT_ATT) == 0)
|
|
rx_ecode = 0020;
|
|
break;
|
|
} /* end case state */
|
|
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Command complete. Set done and put final value in interface register,
|
|
return to IDLE state.
|
|
*/
|
|
|
|
void rx_done (int32 esr_flags, int32 new_ecode)
|
|
{
|
|
int32 drv = (rx_csr & RXCS_DRV)? 1: 0;
|
|
|
|
rx_state = IDLE; /* now idle */
|
|
dev_done = dev_done | INT_RX; /* set done */
|
|
int_req = INT_UPDATE; /* update ints */
|
|
rx_esr = (rx_esr | esr_flags) & ~(RXES_DRDY|RXES_RX02|RXES_DEN);
|
|
if (rx_28) /* RX28? */
|
|
rx_esr = rx_esr | RXES_RX02;
|
|
if (rx_unit[drv].flags & UNIT_ATT) { /* update drv rdy */
|
|
rx_esr = rx_esr | RXES_DRDY;
|
|
if (rx_unit[drv].flags & UNIT_DEN) /* update density */
|
|
rx_esr = rx_esr | RXES_DEN;
|
|
}
|
|
if (new_ecode > 0) /* test for error */
|
|
rx_err = 1;
|
|
if (new_ecode < 0) /* don't update? */
|
|
return;
|
|
rx_ecode = new_ecode; /* update ecode */
|
|
rx_dbr = rx_esr; /* update RXDB */
|
|
return;
|
|
}
|
|
|
|
/* Reset routine. The RX is one of the few devices that schedules
|
|
an I/O transfer as part of its initialization */
|
|
|
|
t_stat rx_reset (DEVICE *dptr)
|
|
{
|
|
rx_dbr = rx_csr = 0; /* 12b mode, drive 0 */
|
|
rx_esr = rx_ecode = 0; /* clear error */
|
|
rx_tr = rx_err = 0; /* clear flags */
|
|
rx_track = rx_sector = 0; /* clear address */
|
|
rx_state = IDLE; /* ctrl idle */
|
|
dev_done = dev_done & ~INT_RX; /* clear done, int */
|
|
int_req = int_req & ~INT_RX;
|
|
int_enable = int_enable & ~INT_RX;
|
|
sim_cancel (&rx_unit[1]); /* cancel drive 1 */
|
|
if (dptr->flags & DEV_DIS) /* disabled? */
|
|
sim_cancel (&rx_unit[0]);
|
|
else if (rx_unit[0].flags & UNIT_BUF) { /* attached? */
|
|
rx_state = INIT_COMPLETE; /* yes, sched init */
|
|
sim_activate (&rx_unit[0], rx_swait * abs (1 - rx_unit[0].TRACK));
|
|
}
|
|
else rx_done (rx_esr | RXES_ID, 0010); /* no, error */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Attach routine */
|
|
|
|
t_stat rx_attach (UNIT *uptr, char *cptr)
|
|
{
|
|
uint32 sz;
|
|
|
|
if ((uptr->flags & UNIT_AUTO) && (sz = sim_fsize_name (cptr))) {
|
|
if (sz > RX_SIZE)
|
|
uptr->flags = uptr->flags | UNIT_DEN;
|
|
else uptr->flags = uptr->flags & ~UNIT_DEN;
|
|
}
|
|
uptr->capac = (uptr->flags & UNIT_DEN)? RX2_SIZE: RX_SIZE;
|
|
return attach_unit (uptr, cptr);
|
|
}
|
|
|
|
/* Set size routine */
|
|
|
|
t_stat rx_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
|
|
{
|
|
if (uptr->flags & UNIT_ATT)
|
|
return SCPE_ALATT;
|
|
if ((rx_28 == 0) && val) /* not on RX8E */
|
|
return SCPE_NOFNC;
|
|
uptr->capac = val? RX2_SIZE: RX_SIZE;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Set controller type */
|
|
|
|
t_stat rx_settype (UNIT *uptr, int32 val, char *cptr, void *desc)
|
|
{
|
|
int32 i;
|
|
|
|
if ((val < 0) || (val > 1) || (cptr != NULL))
|
|
return SCPE_ARG;
|
|
if (val == rx_28)
|
|
return SCPE_OK;
|
|
for (i = 0; i < RX_NUMDR; i++) {
|
|
if (rx_unit[i].flags & UNIT_ATT)
|
|
return SCPE_ALATT;
|
|
}
|
|
for (i = 0; i < RX_NUMDR; i++) {
|
|
if (val)
|
|
rx_unit[i].flags = rx_unit[i].flags | UNIT_DEN | UNIT_AUTO;
|
|
else rx_unit[i].flags = rx_unit[i].flags & ~(UNIT_DEN | UNIT_AUTO);
|
|
rx_unit[i].capac = val? RX2_SIZE: RX_SIZE;
|
|
}
|
|
rx_28 = val;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Show controller type */
|
|
|
|
t_stat rx_showtype (FILE *st, UNIT *uptr, int32 val, void *desc)
|
|
{
|
|
if (rx_28) fprintf (st, "RX28");
|
|
else fprintf (st, "RX8E");
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Bootstrap routine */
|
|
|
|
#define BOOT_START 022
|
|
#define BOOT_ENTRY 022
|
|
#define BOOT_INST 060
|
|
#define BOOT_LEN (sizeof (boot_rom) / sizeof (int16))
|
|
#define BOOT2_START 020
|
|
#define BOOT2_ENTRY 033
|
|
#define BOOT2_LEN (sizeof (boot2_rom) / sizeof (int16))
|
|
|
|
static const uint16 boot_rom[] = {
|
|
06755, /* 22, SDN */
|
|
05022, /* 23, JMP .-1 */
|
|
07126, /* 24, CLL CML RTL ; read command + */
|
|
01060, /* 25, TAD UNIT ; unit no */
|
|
06751, /* 26, LCD ; load read+unit */
|
|
07201, /* 27, CLA IAC ; AC = 1 */
|
|
04053, /* 30, JMS LOAD ; load sector */
|
|
04053, /* 31, JMS LOAD ; load track */
|
|
07104, /* 32, CLL RAL ; AC = 2 */
|
|
06755, /* 33, SDN */
|
|
05054, /* 34, JMP LOAD+1 */
|
|
06754, /* 35, SER */
|
|
07450, /* 36, SNA ; more to do? */
|
|
07610, /* 37, CLA SKP ; error */
|
|
05046, /* 40, JMP 46 ; go empty */
|
|
07402, /* 41-45, HALT ; error */
|
|
07402,
|
|
07402,
|
|
07402,
|
|
07402,
|
|
06751, /* 46, LCD ; load empty */
|
|
04053, /* 47, JMS LOAD ; get data */
|
|
03002, /* 50, DCA 2 ; store */
|
|
02050, /* 51, ISZ 50 ; incr store */
|
|
05047, /* 52, JMP 47 ; loop until done */
|
|
00000, /* LOAD, 0 */
|
|
06753, /* 54, STR */
|
|
05033, /* 55, JMP 33 */
|
|
06752, /* 56, XDR */
|
|
05453, /* 57, JMP I LOAD */
|
|
07024, /* UNIT, CML RAL ; for unit 1 */
|
|
06030 /* 61, KCC */
|
|
};
|
|
|
|
static const uint16 boot2_rom[] = {
|
|
01061, /* READ, TAD UNIT ; next unit+den */
|
|
01046, /* 21, TAD CON360 ; add in 360 */
|
|
00060, /* 22, AND CON420 ; mask to 420 */
|
|
03061, /* 23, DCA UNIT ; 400,420,0,20... */
|
|
07327, /* 24, STL CLA IAC RTL ; AC = 6 = read */
|
|
01061, /* 25, TAD UNIT ; +unit+den */
|
|
06751, /* 26, LCD ; load cmd */
|
|
07201, /* 27, CLA IAC; ; AC = 1 = trksec */
|
|
04053, /* 30, JMS LOAD ; load trk */
|
|
04053, /* 31, JMS LOAD ; load sec */
|
|
07004, /* CN7004, RAL ; AC = 2 = empty */
|
|
06755, /* START, SDN ; done? */
|
|
05054, /* 34, JMP LOAD+1 ; check xfr */
|
|
06754, /* 35, SER ; error? */
|
|
07450, /* 36, SNA ; AC=0 on start */
|
|
05020, /* 37, JMP RD ; try next den,un */
|
|
01061, /* 40, TAD UNIT ; +unit+den */
|
|
06751, /* 41, LCD ; load cmd */
|
|
01061, /* 42, TAD UNIT ; set 60 for sec boot */
|
|
00046, /* 43, AND CON360 ; only density */
|
|
01032, /* 44, TAD CN7004 ; magic */
|
|
03060, /* 45, DCA 60 */
|
|
00360, /* CON360, 360 ; NOP */
|
|
04053, /* 47, JMS LOAD ; get data */
|
|
03002, /* 50, DCA 2 ; store */
|
|
02050, /* 51, ISZ .-1 ; incr store */
|
|
05047, /* 52, JMP .-3 ; loop until done */
|
|
00000, /* LOAD, 0 */
|
|
06753, /* 54, STR ; xfr ready? */
|
|
05033, /* 55, JMP 33 ; no, chk done */
|
|
06752, /* 56, XDR ; get word */
|
|
05453, /* 57, JMP I 53 ; return */
|
|
00420, /* CON420, 420 ; toggle */
|
|
00020 /* UNIT, 20 ; unit+density */
|
|
};
|
|
|
|
t_stat rx_boot (int32 unitno, DEVICE *dptr)
|
|
{
|
|
size_t i;
|
|
extern uint16 M[];
|
|
|
|
if (rx_dib.dev != DEV_RX) /* only std devno */
|
|
return STOP_NOTSTD;
|
|
if (rx_28) {
|
|
for (i = 0; i < BOOT2_LEN; i++)
|
|
M[BOOT2_START + i] = boot2_rom[i];
|
|
cpu_set_bootpc (BOOT2_ENTRY);
|
|
}
|
|
else {
|
|
for (i = 0; i < BOOT_LEN; i++)
|
|
M[BOOT_START + i] = boot_rom[i];
|
|
M[BOOT_INST] = unitno? 07024: 07004;
|
|
cpu_set_bootpc (BOOT_ENTRY);
|
|
}
|
|
return SCPE_OK;
|
|
}
|