simh-testsetgenerator/AltairZ80/i8272.h
2022-10-09 09:10:27 -07:00

45 lines
3.1 KiB
C

/*************************************************************************
* *
* Copyright (c) 2007-2022 Howard M. Harte. *
* https://github.com/hharte *
* *
* Permission is hereby granted, free of charge, to any person obtaining *
* a copy of this software and associated documentation files (the *
* "Software"), to deal in the Software without restriction, including *
* without limitation the rights to use, copy, modify, merge, publish, *
* distribute, sublicense, and/or sell copies of the Software, and to *
* permit persons to whom the Software is furnished to do so, subject to *
* the following conditions: *
* *
* The above copyright notice and this permission notice shall be *
* included in all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, *
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF *
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON- *
* INFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE *
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN *
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN *
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE *
* SOFTWARE. *
* *
* Except as contained in this notice, the names of The Authors shall *
* not be used in advertising or otherwise to promote the sale, use or *
* other dealings in this Software without prior written authorization *
* from the Authors. *
* *
* SIMH Interface based on altairz80_hdsk.c, by Peter Schorn. *
* *
* Module Description: *
* Generic Intel 8272 Disk Controller module for SIMH. *
* *
*************************************************************************/
extern t_stat i8272_attach(UNIT *uptr, CONST char *cptr);
extern t_stat i8272_detach(UNIT *uptr);
extern uint8 I8272_Set_DMA(const uint32 dma_addr);
extern uint8 I8272_Read(const uint32 Addr);
extern uint8 I8272_Write(const uint32 Addr, uint8 cData);
#define I8272_FDC_MSR 0 /* R=FDC Main Status Register, W=Drive Select Register */
#define I8272_FDC_DATA 1 /* R/W FDC Data Register */