302 lines
11 KiB
C
302 lines
11 KiB
C
/* pdp11_cpumod.h: PDP-11 CPU model definitions
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Copyright (c) 2004-2015, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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30-Dec-15 RMS Added 11/03, 11/23 BEVENT disable
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22-Apr-08 RMS Added 11/70 MBRK register
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30-Aug-05 RMS Added additional 11/60 registers
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*/
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#ifndef PDP11_CPUMOD_H_
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#define PDP11_CPUMOD_H_ 0
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#define SOP_1103 (BUS_Q|OPT_BVT)
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#define OPT_1103 (OPT_EIS|OPT_FIS|OPT_BVT)
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#define PSW_1103 0000377
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#define SOP_1104 (BUS_U)
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#define OPT_1104 0
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#define PSW_1104 0000377
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#define SOP_1105 (BUS_U)
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#define OPT_1105 0
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#define PSW_1105 0000377
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#define SOP_1120 (BUS_U)
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#define OPT_1120 0
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#define PSW_1120 0000377
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#define SOP_1123 (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU|OPT_BVT)
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#define OPT_1123 (OPT_FPP|OPT_CIS|OPT_BVT|OPT_MMU)
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#define PSW_F 0170777
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#define PAR_F 0177777
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#define PDR_F 0077516
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#define MM0_F 0160157
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#define MM3_F 0000060
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#define SOP_1123P (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU)
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#define OPT_1123P (OPT_FPP|OPT_CIS)
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#define SOP_1124 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU|OPT_UBM)
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#define OPT_1124 (OPT_FPP|OPT_CIS)
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#define SOP_1134 (BUS_U|OPT_EIS|OPT_MMU)
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#define OPT_1134 (OPT_FPP)
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#define PSW_1134 0170377
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#define PAR_1134 0007777
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#define PDR_1134 0077516
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#define MM0_1134 0160557
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#define SOP_1140 (BUS_U|OPT_EIS|OPT_MMU)
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#define OPT_1140 (OPT_FIS|OPT_MMU)
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#define PSW_1140 0170377
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#define PAR_1140 0007777
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#define PDR_1140 0077516
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#define MM0_1140 0160557
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#define SOP_1144 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU|OPT_UBM)
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#define OPT_1144 (OPT_FPP|OPT_CIS)
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#define PSW_1144 0170777
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#define PAR_1144 0177777
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#define PDR_1144 0177516
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#define MM0_1144 0160557
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#define MM3_1144 0000077
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#define SOP_1145 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU|OPT_RH11)
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#define OPT_1145 (OPT_FPP|OPT_MMU)
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#define PSW_1145 0174377
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#define PAR_1145 0007777
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#define PDR_1145 0077717
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#define MM0_1145 0171777
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#define MM3_1145 0000007
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#define SOP_1160 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU)
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#define OPT_1160 0
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#define PSW_1160 0170377
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#define PAR_1160 0007777
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#define PDR_1160 0077516
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#define MM0_1160 0160557
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#define SOP_1170 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU|OPT_UBM)
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#define OPT_1170 (OPT_FPP|OPT_RH11)
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#define PSW_1170 0174377
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#define PAR_1170 0177777
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#define PDR_1170 0077717
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#define MM0_1170 0171777
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#define MM3_1170 0000067
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#define SOP_1173 (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU)
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#define OPT_1173 (OPT_CIS)
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#define PSW_J 0174777
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#define PAR_J 0177777
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#define PDR_J 0177516
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#define MM0_J 0160177
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#define MM3_J 0000077
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#define SOP_1153 (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU)
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#define OPT_1153 (OPT_CIS)
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#define SOP_1173B (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU)
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#define OPT_1173B (OPT_CIS)
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#define SOP_1183 (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU)
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#define OPT_1183 (OPT_CIS)
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#define SOP_1184 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU|OPT_UBM|OPT_RH11)
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#define OPT_1184 (OPT_CIS)
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#define SOP_1193 (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU)
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#define OPT_1193 (OPT_CIS)
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#define SOP_1194 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU|OPT_UBM|OPT_RH11)
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#define OPT_1194 (OPT_CIS)
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#define MOD_MAX 20
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/* MFPT codes */
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#define MFPT_44 1
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#define MFPT_F 3
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#define MFPT_T 4
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#define MFPT_J 5
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/* KDF11B specific register */
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#define PCRFB_RW 0037477 /* page ctrl reg */
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#define CDRFB_RD 0000377 /* config reg */
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#define CDRFB_WR 0000017
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/* KT24 Unibus map specific registers */
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#define LMAL_RD 0177777 /* last mapped low */
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#define LMAH_RD 0000177 /* last mapped high */
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#define LMAH_WR 0000100
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/* 11/44 specific registers */
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#define CCR44_RD 0033315 /* cache control */
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#define CCR44_WR 0003315
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#define CMR44_RD 0177437 /* cache maint */
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#define CMR44_WR 0000037
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#define CPUE44_BUSE 0004000
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/* 11/60 specific registers */
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#define WCS60_RD 0161776 /* WCS control */
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#define WCS60_WR 0061676
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#define MEME60_RD 0100340 /* memory error */
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#define CCR60_RD 0000315 /* cache control */
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#define CCR60_WR 0000115
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#define MBRK60_WR 0007777 /* microbreak */
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#define CPUE60_RD (CPUE_ODD|CPUE_TMO|CPUE_RED)
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/* 11/70 specific registers */
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#define MBRK70_WR 0000377 /* microbreak */
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/* J11 specific registers */
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/* Maintenance register */
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#define MAINT_V_UQ 9 /* Q/U flag */
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#define MAINT_Q (0 << MAINT_V_UQ) /* Qbus */
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#define MAINT_U (1 << MAINT_V_UQ)
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#define MAINT_V_FPA 8 /* FPA flag */
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#define MAINT_NOFPA (0 << MAINT_V_FPA)
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#define MAINT_FPA (1 << MAINT_V_FPA)
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#define MAINT_V_TYP 4 /* system type */
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#define MAINT_KDJA (1 << MAINT_V_TYP) /* KDJ11A */
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#define MAINT_KDJB (2 << MAINT_V_TYP) /* KDJ11B */
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#define MAINT_KDJD (4 << MAINT_V_TYP) /* KDJ11D */
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#define MAINT_KDJE (5 << MAINT_V_TYP) /* KDJ11E */
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#define MAINT_V_HTRAP 3 /* trap 4 on HALT */
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#define MAINT_HTRAP (1 << MAINT_V_HTRAP)
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#define MAINT_V_POM 1 /* power on option */
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#define MAINT_POODT (0 << MAINT_V_POM) /* power up ODT */
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#define MAINT_POROM (2 << MAINT_V_POM) /* power up ROM */
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#define MAINT_V_BPOK 0 /* power OK */
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#define MAINT_BPOK (1 << MAINT_V_BPOK)
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/* KDJ11B control */
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#define CSRJB_RD 0177767
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#define CSRJB_WR 0037767
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#define CSRJ_LTCI 0020000 /* force LTC int */
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#define CSRJ_LTCD 0010000 /* disable LTC reg */
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#define CSRJ_V_LTCSEL 10
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#define CSRJ_M_LTCSEL 03
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#define CSRJ_LTCSEL(x) (((x) >> CSRJ_V_LTCSEL) & CSRJ_M_LTCSEL)
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#define CSRJ_HBREAK 0001000 /* halt on break */
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#define PCRJB_RW 0077176 /* page ctrl reg */
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#define CDRJB_RD 0000377 /* config register */
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#define CDRJB_WR 0000377
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/* KDJ11D control */
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#define CSRJD_RD 0157777 /* native register */
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#define CSRJD_WR 0000377
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#define CSRJD_15M 0040000 /* 1.5M mem on board */
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/* KDJ11E control */
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#define CSRJE_RD 0137360 /* control reg */
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#define CSRJE_WR 0037370
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#define PCRJE_RW 0177376 /* page ctrl reg */
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#define CDRJE_RD 0000377 /* config register */
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#define CDRJE_WR 0000077
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#define ASRJE_RW 0030462 /* additional status */
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#define ASRJE_V_TOY 8
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#define ASRJE_TOY (1u << ASRJE_V_TOY) /* TOY serial bit */
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#define ASRJE_TOYBIT(x) (((x) >> ASRJE_V_TOY) & 1)
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/* KDJ11E TOY clock */
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#define TOY_HSEC 0
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#define TOY_SEC 1
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#define TOY_MIN 2
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#define TOY_HR 3
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#define TOY_DOW 4
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#define TOY_DOM 5
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#define TOY_MON 6
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#define TOY_YR 7
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#define TOY_LNT 8
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/* KTJ11B Unibus map */
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#define DCRKTJ_RD 0100616 /* diag control */
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#define DCRKTJ_WR 0000416
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#define DDRKTJ_RW 0177777 /* diag data */
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#define MCRKTJ_RD 0000377 /* control register */
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#define MCRKTJ_WR 0000177
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/* Data tables */
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struct cpu_table {
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const char *name; /* model name */
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uint32 std; /* standard flags */
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uint32 opt; /* set/clear flags */
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uint32 maxm; /* max memory */
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uint32 psw; /* PSW mask */
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uint32 mfpt; /* MFPT code */
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uint32 par; /* PAR mask */
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uint32 pdr; /* PDR mask */
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uint32 mm0; /* MMR0 mask */
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uint32 mm3; /* MMR3 mask */
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};
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typedef struct cpu_table CPUTAB;
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struct conf_table {
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uint32 cpum;
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uint32 optm;
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DIB *dib;
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};
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typedef struct conf_table CNFTAB;
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/* Prototypes */
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t_stat cpu_set_model (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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t_stat cpu_set_opt (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat cpu_clr_opt (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat cpu_set_size (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat cpu_set_bus (int32 opt);
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#endif
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