1e4401fd84
The modem and host interface TX services should both be called from the RTC device, but when the host interface was implemented the call was not added.
385 lines
14 KiB
C
385 lines
14 KiB
C
/* h316_rtc.c- BBN ARPAnet IMP/TIP Real Time Clock and Watch Dog Timer
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Based on the SIMH simulator package written by Robert M Supnik.
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Copyright (c) 2013 Robert Armstrong, bob@jfcl.com.
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT ARMSTRONG BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert Armstrong shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert Armstrong.
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rtc real time clock
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wdt watch dog timer
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21-May-13 RLA New file
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OVERVIEW
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The IMP and TIP used a custom real time clock that was apparently created
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by BBN just for those devices. The IMP/TIP RTC is NOT the same as the
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official Honeywell real time clock option, H316-12. When emulating an IMP
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or TIP, this RTC device must be enabled and the standard simh H316 CLK
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device must be disabled.
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The IMP and TIP also had a watch dog timer which, if ever allowed to time
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out, would cause a non-maskable interrupt via location 62(8) - this is the
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same trap location used by the memory lockout option, which the IMP/TIP
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lacked. Not much is known about the WDT, and the current implementation is
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simply a place holder that doesn't do much.
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RTC state is maintained in a set of state variables:
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ENA RTC is enabled
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COUNT current count
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IEN RTC interrupt enabled
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IRQ RTC interrupt pending
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TPS effective ticks per second
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WAIT simulator time until the next tick
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WDT state is maintained in a set of state variables:
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COUNT current countdown
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TMO WDT timed out
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LIGHTS last "set status lights"
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WAIT simulator time until the next tick
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TODO
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Implement the WDT!!
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*/
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#ifdef VM_IMPTIP
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#include "h316_defs.h" // H316 emulator definitions
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#include "h316_imp.h" // ARPAnet IMP/TIP definitions
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// Locals ...
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uint32 rtc_interval = RTC_INTERVAL; // RTC tick interval (in microseconds)
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uint32 rtc_quantum = RTC_QUANTUM; // RTC update interval (in ticks)
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uint32 rtc_tps = 1000000UL / (RTC_INTERVAL * RTC_QUANTUM);
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uint16 rtc_enabled = 1; // RTC enabled
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uint32 rtc_count = 0; // current RTC count
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uint32 wdt_delay = WDT_DELAY; // WDT timeout (in milliseconds, 0=none)
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uint32 wdt_count = 0; // current WDT countdown
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uint16 wdt_lights = 0; // last "set status lights" output
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// Externals from other parts of simh ...
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extern uint16 dev_ext_int, dev_ext_enb; // current IRQ and IEN bit vectors
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extern int32 PC; // current PC (for debug messages)
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extern int32 stop_inst; // needed by IOBADFNC()
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// Forward declarations ...
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int32 rtc_io (int32 inst, int32 fnc, int32 dat, int32 dev);
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t_stat rtc_service (UNIT *uptr);
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t_stat rtc_reset (DEVICE *dptr);
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int32 wdt_io (int32 inst, int32 fnc, int32 dat, int32 dev);
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t_stat wdt_service (UNIT *uptr);
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t_stat wdt_reset (DEVICE *dptr);
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t_stat rtc_set_interval (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat rtc_show_interval (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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t_stat rtc_set_quantum(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat rtc_show_quantum (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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t_stat wdt_set_delay (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat wdt_show_delay (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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////////////////////////////////////////////////////////////////////////////////
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////////////////// R T C D A T A S T R U C T U R E S //////////////////
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////////////////////////////////////////////////////////////////////////////////
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// RTC device information block ...
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DIB rtc_dib = { RTC, 1, IOBUS, IOBUS, INT_V_RTC, INT_V_NONE, &rtc_io, 0 };
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// RTC unit data block (we have only one unit!) ...
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UNIT rtc_unit = { UDATA (&rtc_service, 0, 0), (RTC_INTERVAL*RTC_QUANTUM) };
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// RTC device registers (for "EXAMINE RTC STATE") ...
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REG rtc_reg[] = {
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{ FLDATA (ENA, rtc_enabled, 0) },
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{ DRDATA (COUNT, rtc_count, 16), PV_LEFT },
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{ FLDATA (IEN, dev_ext_enb, INT_V_RTC-INT_V_EXTD) },
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{ FLDATA (IRQ, dev_ext_int, INT_V_RTC-INT_V_EXTD) },
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{ DRDATA (TPS, rtc_tps, 32), PV_LEFT },
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{ DRDATA (WAIT, rtc_unit.wait, 24), REG_NZ + PV_LEFT },
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{ DRDATA (INTERVAL, rtc_interval, 32), PV_LEFT | REG_RO },
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{ DRDATA (QUANTUM, rtc_quantum, 32), PV_LEFT | REG_RO },
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{ NULL }
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};
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// RTC device modifiers (for "SET/SHOW RTC xxx") ...
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MTAB rtc_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 0, "INTERVAL", "INTERVAL", &rtc_set_interval, &rtc_show_interval, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "QUANTUM", "QUANTUM", &rtc_set_quantum, &rtc_show_quantum, NULL },
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{ 0 }
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};
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// RTC debugging flags (for "SET RTC DEBUG=xxx") ...
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DEBTAB rtc_debug[] = {
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{"WARN", IMP_DBG_WARN},
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{"IO", IMP_DBG_IOT},
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{0}
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};
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// And finally tie it all together ...
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DEVICE rtc_dev = {
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"RTC", &rtc_unit, rtc_reg, rtc_mod,
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1, 0, 0, 0, 0, 0,
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NULL, NULL, &rtc_reset, NULL, NULL, NULL,
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&rtc_dib, DEV_DIS|DEV_DISABLE|DEV_DEBUG, 0, rtc_debug, NULL, NULL
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};
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////////////////////////////////////////////////////////////////////////////////
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////////////////// W D T D A T A S T R U C T U R E S //////////////////
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////////////////////////////////////////////////////////////////////////////////
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// WDT device information block ...
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DIB wdt_dib = { WDT, 1, IOBUS, IOBUS, INT_V_NONE, INT_V_NONE, &wdt_io, 0 };
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// WDT unit data block (it has only one) ...
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UNIT wdt_unit = { UDATA (&wdt_service, 0, 0), 1000 };
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// WDT device registers (for "EXAMINE WDT STATE") ...
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REG wdt_reg[] = {
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{ DRDATA (COUNT, wdt_count, 16), PV_LEFT },
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{ DRDATA (WAIT, wdt_unit.wait, 24), REG_NZ | PV_LEFT },
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{ ORDATA (LIGHTS, wdt_lights, 16), REG_RO | PV_LEFT },
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{ NULL }
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};
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// WDT device modifiers (for "SET/SHOW WDT xxx") ...
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MTAB wdt_mod[] = {
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{ MTAB_XTD | MTAB_VDV, 0, "DELAY", "DELAY", &wdt_set_delay, &wdt_show_delay, NULL },
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{ 0 }
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};
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// WDT debugging flags (for "SET WDT DEBUG=xxx") ...
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DEBTAB wdt_debug[] = {
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{"WARN", IMP_DBG_WARN},
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{"IO", IMP_DBG_IOT},
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{"LIGHTS", WDT_DBG_LIGHTS},
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{0}
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};
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// And summarize ...
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DEVICE wdt_dev = {
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"WDT", &wdt_unit, wdt_reg, wdt_mod,
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1, 0, 0, 0, 0, 0,
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NULL, NULL, &wdt_reset, NULL, NULL, NULL,
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&wdt_dib, DEV_DIS|DEV_DISABLE|DEV_DEBUG, 0, wdt_debug, NULL, NULL
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};
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////////////////////////////////////////////////////////////////////////////////
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////////// R T C I / O A N D S E R V I C E R O U T I N E S //////////
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////////////////////////////////////////////////////////////////////////////////
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// Set and clear the RTC IRQ and IEN ...
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#define SET_RTC_IRQ() SET_EXT_INT((1u << (rtc_dib.inum - INT_V_EXTD)))
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#define CLR_RTC_IRQ() CLR_EXT_INT((1u << (rtc_dib.inum - INT_V_EXTD)))
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#define CLR_RTC_IEN() CLR_EXT_ENB((1u << (rtc_dib.inum - INT_V_EXTD)))
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// RTC IO routine ...
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int32 rtc_io (int32 inst, int32 fnc, int32 dat, int32 dev)
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{
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switch (inst) {
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case ioOCP:
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if (fnc == 010) {
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// CLKOFF - turn the RTC off ...
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sim_cancel(&rtc_unit); rtc_enabled = 0; CLR_RTC_IRQ();
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sim_debug(IMP_DBG_IOT, &rtc_dev, "disabled (PC=%06o)\n", PC-1);
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return dat;
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} else if (fnc == 000) {
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// CLKON - turn the RTC on ...
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rtc_enabled = 1; CLR_RTC_IRQ();
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if (sim_is_active(&rtc_unit) == 0)
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sim_activate (&rtc_unit, sim_rtc_init (rtc_unit.wait));
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sim_debug(IMP_DBG_IOT, &rtc_dev, "enabled (PC=%06o)\n", PC-1);
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return dat;
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}
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break;
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case ioINA:
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if ((fnc == 010) || (fnc == 000)) {
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// RDCLOK - return the current count
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sim_debug(IMP_DBG_IOT, &rtc_dev, "read clock (PC=%06o, RTC=%06o)\n", PC-1, (rtc_count & DMASK));
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return IOSKIP((rtc_count & DMASK));
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}
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break;
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}
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sim_debug(IMP_DBG_WARN, &rtc_dev, "UNIMPLEMENTED I/O (PC=%06o, instruction=%o, function=%02o)\n", PC-1, inst, fnc);
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return IOBADFNC(dat);
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}
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// RTC unit service ...
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t_stat rtc_service (UNIT *uptr)
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{
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// Add the current quantum to the clock register and, if the clock register
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// has overflowed, request an interrupt. The real hardware interrupts when
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// there is a carry out of the low byte (in other words, every 256 clocks).
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// Note that we can't simply check the low byte for zero to detect overflows
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// because of the quantum. Since we aren't necessarily incrementing by 1, we
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// may never see a value of exactly zero. We'll have to be more clever.
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uint8 rtc_high = HIBYTE(rtc_count);
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rtc_count = (rtc_count + rtc_quantum) & DMASK;
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if (HIBYTE(rtc_count) != rtc_high) {
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sim_debug(IMP_DBG_IOT, &rtc_dev, "interrupt request\n");
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SET_RTC_IRQ();
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}
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mi_tx_service(rtc_quantum);
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hi_tx_service(rtc_quantum);
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uptr->wait = sim_rtc_calb (rtc_tps); /* recalibrate */
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sim_activate_after (uptr, 1000000/rtc_tps); /* reactivate unit */
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return SCPE_OK;
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}
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////////////////////////////////////////////////////////////////////////////////
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////////// W D T I / O A N D S E R V I C E R O U T I N E S //////////
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////////////////////////////////////////////////////////////////////////////////
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// WDT IO routine ...
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int32 wdt_io (int32 inst, int32 fnc, int32 dat, int32 dev)
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{
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if ((inst == ioOCP) && (fnc == 0)) {
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// Reset WDT ...
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sim_debug(IMP_DBG_IOT, &wdt_dev, "reset (PC=%06o)\n", PC-1);
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return dat;
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} else if ((inst == ioOTA) && (fnc == 0)) {
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// Set status lights ...
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if (wdt_lights != dat) {
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sim_debug(WDT_DBG_LIGHTS, &wdt_dev, "changed to %06o\n", dat);
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}
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sim_debug(IMP_DBG_IOT, &wdt_dev, "set status lights (PC=%06o, LIGHTS=%06o)\n", PC-1, dat);
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wdt_lights = dat; return dat;
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}
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sim_debug(IMP_DBG_WARN, &wdt_dev, "UNIMPLEMENTED I/O (PC=%06o, instruction=%o, function=%02o)\n", PC-1, inst, fnc);
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return IOBADFNC(dat);
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}
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// WDT unit service ...
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t_stat wdt_service (UNIT *uptr)
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{
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return SCPE_OK;
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}
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////////////////////////////////////////////////////////////////////////////////
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/////////////// D E V I C E A C T I O N C O M M A N D S ////////////////
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////////////////////////////////////////////////////////////////////////////////
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// RTC reset routine ...
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t_stat rtc_reset (DEVICE *dptr)
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{
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// Clear the interrupt enable and any pending interrupts, reset the count
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// and enable the clock. At least I assume that's what a reset does - the
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// docs aren't too specific on this point...
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rtc_enabled = 1; rtc_count = 0;
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CLR_RTC_IRQ(); CLR_RTC_IEN();
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sim_cancel (&rtc_unit);
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sim_register_clock_unit ((dptr->flags & DEV_DIS) ? NULL : &rtc_unit);
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return SCPE_OK;
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}
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// WDT reset routine ...
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t_stat wdt_reset (DEVICE *dptr)
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{
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// Clear the WDT countdown and turn off all the lights ...
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wdt_count = 0; wdt_lights = 0;
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sim_cancel (&wdt_unit);
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return SCPE_OK;
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}
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////////////////////////////////////////////////////////////////////////////////
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///////// D E V I C E S E T A N D S H O W C O M M A N D S //////////
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////////////////////////////////////////////////////////////////////////////////
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// Set/Show RTC interval ...
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t_stat rtc_set_interval (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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uint32 newint, newtps; t_stat ret;
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if (cptr == NULL) return SCPE_ARG;
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newint = get_uint (cptr, 10, 1000000, &ret);
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if (ret != SCPE_OK) return ret;
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if (newint == 0) return SCPE_ARG;
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newtps = 1000000UL / (newint * rtc_quantum);
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if ((newtps == 0) || (newtps >= 100000)) return SCPE_ARG;
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rtc_interval = newint; rtc_tps = newtps;
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uptr->wait = sim_rtc_calb (rtc_tps);
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return SCPE_OK;
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}
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t_stat rtc_show_interval (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
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{
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fprintf(st,"interval=%d (us)", rtc_interval);
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return SCPE_OK;
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}
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// Set/Show RTC quantum ...
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t_stat rtc_set_quantum (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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uint32 newquant, newtps; t_stat ret;
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if (cptr == NULL) return SCPE_ARG;
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newquant = get_uint (cptr, 10, 1000000, &ret);
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if (ret != SCPE_OK) return ret;
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if (newquant == 0) return SCPE_ARG;
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newtps = 1000000UL / (rtc_interval * newquant);
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if ((newtps == 0) || (newtps >= 100000)) return SCPE_ARG;
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rtc_quantum = newquant; rtc_tps = newtps;
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uptr->wait = sim_rtc_calb (rtc_tps);
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return SCPE_OK;
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}
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t_stat rtc_show_quantum (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
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{
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fprintf(st,"quantum=%d (ticks)", rtc_quantum);
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return SCPE_OK;
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}
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// Set/Show WDT delay ...
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t_stat wdt_set_delay (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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uint32 newint; t_stat ret;
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if (cptr == NULL) return SCPE_ARG;
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newint = get_uint (cptr, 10, 65535, &ret);
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if (ret != SCPE_OK) return ret;
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if (newint != 0)
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return sim_messagef(SCPE_IERR, "WDT - timeout not yet implemented\n");
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wdt_delay = newint;
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// TBA add calculations here???
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return SCPE_OK;
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}
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t_stat wdt_show_delay (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
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{
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if (wdt_delay > 0)
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fprintf(st,"delay=%d (ms)", wdt_delay);
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else
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fprintf(st,"no timeout");
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return SCPE_OK;
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}
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#endif // #ifdef VM_IMPTIP from the very top
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