ffe537a621
IO: DVT_NOTDEV macro incorrect, Device mapping algorithm creates false dispatch points. This mapped Multi Unit Controller and Single Unit Controller to same device. DP, DP, MT, RAD: Test for non-existent device returns wrong status. DP, DK, MT: TIO status should return non-operational for unattached device.
498 lines
20 KiB
C
498 lines
20 KiB
C
/* sigma_dk.c: 7250/7251-7252 cartridge disk simulator
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Copyright (c) 2007-2024, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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dk 7250/7251-7252 cartridge disk
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11-Feb-24 RMS Report non-operational if not attached (Ken Rector)
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01-Feb-24 RMS Fixed nx unit test (Ken Rector)
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15-Dec-22 RMS Moved SIO interrupt test to devices
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02-Jul-22 RMS Fixed bugs in multi-unit operation
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Transfers are always done a sector at a time.
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*/
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#include "sigma_io_defs.h"
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#include <math.h>
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#define UTRK u3 /* current track */
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/* Constants */
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#define DK_NUMDR 8 /* drives/ctlr */
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#define DK_WDSC 90 /* words/sector */
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#define DK_SCTK 16 /* sectors/track */
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#define DK_TKUN 408 /* tracks/unit */
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#define DK_WDUN (DK_WDSC*DK_SCTK*DK_TKUN) /* words/unit */
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/* Address bytes */
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#define DKA_V_TK 4 /* track offset */
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#define DKA_M_TK 0x1FF
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#define DKA_V_SC 0 /* sector offset */
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#define DKA_M_SC 0xF
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#define DKA_GETTK(x) (((x) >> DKA_V_TK) & DKA_M_TK)
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#define DKA_GETSC(x) (((x) >> DKA_V_SC) & DKA_M_SC)
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/* Status byte 3 is current sector */
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#define DKS_NBY 3
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/* Device state */
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#define DKS_INIT 0x101
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#define DKS_END 0x102
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#define DKS_WRITE 0x01
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#define DKS_READ 0x02
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#define DKS_SEEK 0x03
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#define DKS_SEEK2 0x103
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#define DKS_SENSE 0x04
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#define DKS_CHECK 0x05
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#define DKS_RDEES 0x12
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#define DKS_TEST 0x13
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/* Device status */
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#define DKV_OVR 0x80 /* overrun - NI */
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#define DKV_BADS 0x20 /* bad track */
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#define DKV_WPE 0x10
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#define GET_PSC(x) ((int32) fmod (sim_gtime() / ((double) (x * DK_WDSC)), \
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((double) DK_SCTK)))
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uint32 dk_cmd = 0; /* state */
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uint32 dk_flags = 0; /* status flags */
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uint32 dk_ad = 0; /* disk address */
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uint32 dk_time = 5; /* inter-word time */
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uint32 dk_stime = 20; /* inter-track time */
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uint32 dk_stopioe = 1; /* stop on I/O error */
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extern uint32 chan_ctl_time;
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uint32 dk_disp (uint32 op, uint32 dva, uint32 *dvst);
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uint32 dk_tio_status (uint32 un);
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uint32 dk_tdv_status (uint32 un);
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t_stat dk_chan_err (uint32 dva, uint32 st);
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t_stat dk_svc (UNIT *uptr);
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t_stat dk_reset (DEVICE *dptr);
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t_bool dk_inv_ad (uint32 *da);
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t_bool dk_inc_ad (void);
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t_bool dk_end_sec (UNIT *uptr, uint32 lnt, uint32 exp, uint32 st);
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/* DK data structures
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dk_dev DK device descriptor
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dk_unit DK unit descriptor
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dk_reg DK register list
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*/
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dib_t dk_dib = { DVA_DK, &dk_disp };
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UNIT dk_unit[] = {
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{ UDATA (&dk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF, DK_WDUN) },
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{ UDATA (&dk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF, DK_WDUN) },
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{ UDATA (&dk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF, DK_WDUN) },
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{ UDATA (&dk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF, DK_WDUN) },
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{ UDATA (&dk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF, DK_WDUN) },
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{ UDATA (&dk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF, DK_WDUN) },
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{ UDATA (&dk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF, DK_WDUN) },
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{ UDATA (&dk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF, DK_WDUN) }
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};
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REG dk_reg[] = {
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{ HRDATA (CMD, dk_cmd, 9) },
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{ HRDATA (FLAGS, dk_flags, 8) },
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{ HRDATA (ADDR, dk_ad, 8) },
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{ DRDATA (TIME, dk_time, 24), PV_LEFT+REG_NZ },
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{ DRDATA (STIME, dk_stime, 24), PV_LEFT+REG_NZ },
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{ FLDATA (STOPIOE, dk_stopioe, 0) },
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{ HRDATA (DEVNO, dk_dib.dva, 12), REG_HRO },
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{ NULL }
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};
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MTAB dk_mod[] = {
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{ MTAB_XTD|MTAB_VUN, 0, "write enabled", "WRITEENABLED",
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&set_writelock, &show_writelock, NULL, "Write enable drive" },
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{ MTAB_XTD|MTAB_VUN, 1, NULL, "LOCKED",
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&set_writelock, NULL, NULL, "Write lock drive" },
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{ MTAB_XTD|MTAB_VDV, 0, "CHAN", "CHAN",
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&io_set_dvc, &io_show_dvc, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "DVA", "DVA",
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&io_set_dva, &io_show_dva, NULL },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "CSTATE", NULL,
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NULL, &io_show_cst, NULL },
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{ 0 }
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};
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DEVICE dk_dev = {
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"DK", dk_unit, dk_reg, dk_mod,
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DK_NUMDR, 16, 22, 1, 16, 32,
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NULL, NULL, &dk_reset,
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NULL, NULL, NULL,
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&dk_dib, DEV_DISABLE
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};
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/* DK: IO dispatch routine
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For all calls except AIO, dva is the full channel/device/unit address
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For AIO, the handler must return the unit number
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*/
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uint32 dk_disp (uint32 op, uint32 dva, uint32 *dvst)
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{
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uint32 i;
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uint32 un = DVA_GETUNIT (dva);
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int32 iu;
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UNIT *uptr;
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if ((un >= DK_NUMDR) || /* inv unit num? */
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(dk_unit[un].flags & UNIT_DIS)) { /* disabled unit? */
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*dvst = DVT_NODEV;
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return 0;
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}
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switch (op) { /* case on op */
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case OP_SIO: /* start I/O */
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*dvst = dk_tio_status (un); /* get status */
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if (chan_chk_dvi (dva)) /* int pending? */
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*dvst |= (CC2 << DVT_V_CC); /* SIO fails */
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else if ((*dvst & (DVS_CST|DVS_DST)) == 0) { /* ctrl + dev idle? */
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dk_cmd = DKS_INIT; /* start dev thread */
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sim_activate (&dk_unit[un], chan_ctl_time);
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}
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break;
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case OP_TIO: /* test status */
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*dvst = dk_tio_status (un); /* return status */
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break;
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case OP_TDV: /* test status */
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*dvst = dk_tdv_status (un); /* return status */
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break;
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case OP_HIO: /* halt I/O */
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chan_clr_chi (dva); /* clr int */
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*dvst = dk_tio_status (un); /* get status */
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if ((*dvst & DVS_CST) != 0) { /* ctrl busy? */
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for (i = 0; i < DK_NUMDR; i++) { /* find busy unit */
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uptr = &dk_unit[i];
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if (sim_is_active (uptr)) { /* active? */
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sim_cancel (uptr); /* stop */
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chan_uen (dk_dib.dva | i); /* uend on unit */
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} /* end if active */
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} /* end for */
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}
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break;
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case OP_AIO: /* acknowledge int */
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iu = chan_clr_chi (dk_dib.dva); /* clr int */
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if (iu < 0) { /* no int? */
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*dvst = 0;
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return SCPE_IERR;
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}
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*dvst = dk_tdv_status (iu) | /* get status */
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(iu << DVT_V_UN); /* or in unit */
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break;
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default:
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*dvst = 0;
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return SCPE_IERR;
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}
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return 0;
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}
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/* Unit service */
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t_stat dk_svc (UNIT *uptr)
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{
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uint32 i, sc, da, wd, wd1, cmd, c[3];
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uint32 *fbuf = (uint32 *) uptr->filebuf;
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uint32 un = uptr - dk_unit;
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uint32 dva = dk_dib.dva | un;
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int32 t, dc;
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uint32 st;
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switch (dk_cmd) {
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case DKS_INIT: /* init state */
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st = chan_get_cmd (dva, &cmd); /* get command */
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if (CHS_IFERR (st)) /* channel error? */
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return dk_chan_err (dva,st);
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if ((cmd == 0) || /* invalid cmd? */
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((cmd > DKS_CHECK) && (cmd != DKS_RDEES) && (cmd != DKS_TEST))) {
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chan_uen (dva); /* uend */
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return SCPE_OK;
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}
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dk_flags = 0; /* clear status */
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dk_cmd = cmd & 0x17; /* next state */
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if ((cmd == DKS_SEEK) || /* fast cmd? */
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(cmd == DKS_SENSE) ||
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(cmd == DKS_TEST))
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sim_activate (uptr, chan_ctl_time); /* schedule soon */
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else { /* data transfer */
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sc = DKA_GETSC (dk_ad); /* new sector */
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t = sc - GET_PSC (dk_time); /* delta to new */
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if (t < 0) /* wrap around? */
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t = t + DK_SCTK;
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sim_activate (uptr, t * dk_time * DK_WDSC); /* schedule op */
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}
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return SCPE_OK;
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case DKS_END: /* end state */
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st = chan_end (dva); /* set channel end */
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if (CHS_IFERR (st)) /* channel error? */
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return dk_chan_err (dva,st);
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if (st == CHS_CCH) { /* command chain? */
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dk_cmd = DKS_INIT; /* restart thread */
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sim_activate (uptr, chan_ctl_time);
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}
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return SCPE_OK; /* done */
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case DKS_SEEK: /* seek */
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c[0] = c[1] = 0;
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for (i = 0, st = 0; (i < 2) && (st != CHS_ZBC); i++) {
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st = chan_RdMemB (dva, &c[i]); /* get byte */
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if (CHS_IFERR (st)) /* channel error? */
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return dk_chan_err (dva,st);
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}
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dk_ad = ((c[0] & 0x7F) << 8) | c[1]; /* new address */
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if (((i != 2) || (st != CHS_ZBC)) && /* length error? */
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chan_set_chf (dva, CHF_LNTE)) /* care? */
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return SCPE_OK;
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dc = DKA_GETTK (dk_ad); /* desired track */
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t = abs (uptr->UTRK - dc); /* get track diff */
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if (t == 0)
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t = 1;
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sim_activate (uptr, t * dk_stime);
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uptr->UTRK = dc; /* put on track */
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dk_cmd = DKS_SEEK2;
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return SCPE_OK;
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case DKS_SEEK2: /* seek complete */
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if (uptr->UTRK >= DK_TKUN) {
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dk_flags |= DKV_BADS;
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chan_uen (dva);
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return SCPE_OK;
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}
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break; /* seek done */
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case DKS_SENSE: /* sense */
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c[0] = ((dk_ad >> 8) & 0x7F) | ((uptr->flags & UNIT_RO)? 0x80: 0);
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c[1] = dk_ad & 0xFF; /* address */
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c[2] = GET_PSC (dk_time); /* curr sector */
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for (i = 0, st = 0; (i < DKS_NBY) && (st != CHS_ZBC); i++) {
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st = chan_WrMemB (dva, c[i]); /* store char */
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if (CHS_IFERR (st)) /* channel error? */
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return dk_chan_err (dva,st);
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}
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if (((i != DKS_NBY) || (st != CHS_ZBC)) &&
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chan_set_chf (dva, CHF_LNTE)) /* length error? */
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return SCPE_OK;
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break;
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case DKS_WRITE: /* write */
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if (uptr->flags & UNIT_RO) { /* write locked? */
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dk_flags |= DKV_WPE; /* set status */
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chan_uen (dva); /* uend */
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return SCPE_OK;
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}
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if (dk_inv_ad (&da)) { /* invalid addr? */
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chan_uen (dva); /* uend */
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return SCPE_OK;
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}
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for (i = 0, st = 0; i < DK_WDSC; da++, i++) { /* sector loop */
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if (st != CHS_ZBC) { /* chan not done? */
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st = chan_RdMemW (dva, &wd); /* read word */
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if (CHS_IFERR (st)) { /* channel error? */
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dk_inc_ad (); /* da increments */
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return dk_chan_err (dva,st);
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}
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}
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else wd = 0;
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fbuf[da] = wd; /* store in buffer */
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if (da >= uptr->hwmark) /* update length */
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uptr->hwmark = da + 1;
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}
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if (dk_end_sec (uptr, i, DK_WDSC, st)) /* transfer done? */
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return SCPE_OK; /* err or cont */
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break;
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/* Must be done by bytes to get precise miscompare */
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case DKS_CHECK: /* write check */
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if (dk_inv_ad (&da)) { /* invalid addr? */
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chan_uen (dva); /* uend */
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return SCPE_OK;
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}
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for (i = 0, st = 0; (i < (DK_WDSC * 4)) && (st != CHS_ZBC); ) {
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st = chan_RdMemB (dva, &wd); /* read byte */
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if (CHS_IFERR (st)) { /* channel error? */
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dk_inc_ad (); /* da increments */
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return dk_chan_err (dva,st);
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}
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wd1 = (fbuf[da] >> (24 - ((i % 4) * 8))) & 0xFF; /* byte */
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if (wd != wd1) { /* check error? */
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dk_inc_ad (); /* da increments */
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chan_set_chf (dva, CHF_XMDE); /* set xmt err flag */
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chan_uen (dva); /* force uend */
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return SCPE_OK;
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}
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da = da + ((++i % 4) == 0); /* every 4th byte */
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}
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if (dk_end_sec (uptr, i, DK_WDSC * 4, st)) /* transfer done? */
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return SCPE_OK; /* err or cont */
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break;
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case DKS_READ: /* read */
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if (dk_inv_ad (&da)) { /* invalid addr? */
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chan_uen (dva); /* uend */
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return SCPE_OK;
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}
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for (i = 0, st = 0; (i < DK_WDSC) && (st != CHS_ZBC); da++, i++) {
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st = chan_WrMemW (dva, fbuf[da]); /* store in mem */
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if (CHS_IFERR (st)) { /* channel error? */
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dk_inc_ad (); /* da increments */
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return dk_chan_err (dva,st);
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}
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}
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if (dk_end_sec (uptr, i, DK_WDSC, st)) /* transfer done? */
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return SCPE_OK; /* err or cont */
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break;
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}
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dk_cmd = DKS_END; /* op done, next state */
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sim_activate (uptr, chan_ctl_time);
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return SCPE_OK;
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}
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/* Common read/write sector end routine
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case 1 - more to transfer, not end disk - reschedule, return TRUE
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case 2 - more to transfer, end disk - uend, return TRUE
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case 3 - transfer done, length error - uend, return TRUE
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case 4 - transfer done, no length error - return FALSE (sched end state)
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*/
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t_bool dk_end_sec (UNIT *uptr, uint32 lnt, uint32 exp, uint32 st)
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{
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uint32 un = uptr - dk_unit;
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uint32 dva = dk_dib.dva | un;
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if (st != CHS_ZBC) { /* end record? */
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if (dk_inc_ad ()) /* inc addr, ovf? */
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chan_uen (dva); /* uend */
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else sim_activate (uptr, dk_time * 16); /* no, next sector */
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return TRUE;
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}
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dk_inc_ad (); /* just incr addr */
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if ((lnt != exp) && /* length error? */
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chan_set_chf (dva, CHF_LNTE)) /* do we care? */
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return TRUE;
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return FALSE; /* cmd done */
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}
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/* DK status routine */
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uint32 dk_tio_status (uint32 un)
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{
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uint32 i, st;
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st = DVS_AUTO; /* flags */
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if (sim_is_active (&dk_unit[un])) /* active => busy */
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st |= DVS_DBUSY;
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else if ((dk_unit[un].flags & UNIT_ATT) == 0) /* not att => offl */
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st |= DVS_DOFFL;
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for (i = 0; i < DK_NUMDR; i++) { /* loop thru units */
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if (sim_is_active (&dk_unit[i])) /* active? */
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st |= (DVS_CBUSY | (CC2 << DVT_V_CC)); /* ctrl is busy */
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return st;
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}
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return DVS_AUTO;
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}
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uint32 dk_tdv_status (uint32 un)
|
|
{
|
|
return dk_flags | (dk_inv_ad (NULL)? DKV_BADS: 0);
|
|
}
|
|
|
|
/* Validate disk address */
|
|
|
|
t_bool dk_inv_ad (uint32 *da)
|
|
{
|
|
uint32 tk = DKA_GETTK (dk_ad);
|
|
uint32 sc = DKA_GETSC (dk_ad);
|
|
|
|
if (tk >= DK_TKUN) /* badtrk? */
|
|
return TRUE;
|
|
if (da) /* return word addr */
|
|
*da = ((tk * DK_SCTK) + sc) * DK_WDSC;
|
|
return FALSE;
|
|
}
|
|
|
|
/* Increment disk address */
|
|
|
|
t_bool dk_inc_ad (void)
|
|
{
|
|
uint32 tk = DKA_GETTK (dk_ad);
|
|
uint32 sc = DKA_GETSC (dk_ad);
|
|
|
|
sc = sc + 1; /* sector++ */
|
|
if (sc >= DK_SCTK) { /* overflow? */
|
|
sc = 0; /* wrap sector */
|
|
tk = tk + 1; /* track++ */
|
|
}
|
|
dk_ad = ((tk << DKA_V_TK) | /* rebuild dk_ad */
|
|
(sc << DKA_V_SC));
|
|
if (tk >= DK_TKUN) /* invalid addr? */
|
|
return TRUE;
|
|
return FALSE;
|
|
}
|
|
|
|
/* Channel error */
|
|
|
|
t_stat dk_chan_err (uint32 dva, uint32 st)
|
|
{
|
|
chan_uen (dva); /* uend */
|
|
if (st < CHS_ERR)
|
|
return st;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Reset routine */
|
|
|
|
t_stat dk_reset (DEVICE *dptr)
|
|
{
|
|
uint32 i;
|
|
|
|
for (i = 0; i < DK_NUMDR; i++) {
|
|
sim_cancel (&dk_unit[i]); /* stop dev thread */
|
|
dk_unit[i].UTRK = 0;
|
|
}
|
|
dk_cmd = 0;
|
|
dk_flags = 0;
|
|
dk_ad = 0;
|
|
chan_reset_dev (dk_dib.dva); /* clr int, active */
|
|
return SCPE_OK;
|
|
}
|