735 lines
34 KiB
C
735 lines
34 KiB
C
/* pdp11_ry.c: RX211/RXV21/RX02 floppy disk simulator
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Copyright (c) 1993-2013, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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ry RX211/RXV21/RX02 floppy disk
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23-Oct-13 RMS Revised for new boot setup routine
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03-Sep-13 RMS Added explicit void * cast
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15-May-06 RMS Fixed bug in autosize attach (David Gesswein)
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07-Jul-05 RMS Removed extraneous externs
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18-Feb-05 RMS Fixed bug in boot code (Graham Toal)
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30-Sep-04 RMS Revised Unibus interface
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21-Mar-04 RMS Added VAX support
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29-Dec-03 RMS Added RXV21 support
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19-May-03 RMS Revised for new conditional compilation scheme
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25-Apr-03 RMS Revised for extended file support
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14-Mar-03 RMS Fixed variable size interaction with save/restore
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03-Mar-03 RMS Fixed autosizing
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12-Oct-02 RMS Added autoconfigure support
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An RX02 diskette consists of 77 tracks, each with 26 sectors of 256B.
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Tracks are numbered 0-76, sectors 1-26.
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*/
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#if defined (VM_PDP10) /* PDP10 version */
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#include "pdp10_defs.h"
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#define DEV_DISI DEV_DIS
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#elif defined (VM_VAX) /* VAX version */
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#include "vax_defs.h"
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#define DEV_DISI 0
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#else /* PDP-11 version */
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#include "pdp11_defs.h"
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#define DEV_DISI DEV_DIS
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#endif
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#define RX_NUMTR 77 /* tracks/disk */
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#define RX_M_TRACK 0377
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#define RX_NUMSC 26 /* sectors/track */
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#define RX_M_SECTOR 0177
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#define RX_NUMBY 128
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#define RX_SIZE (RX_NUMTR * RX_NUMSC * RX_NUMBY)
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#define RY_NUMBY 256 /* bytes/sector */
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#define RY_SIZE (RX_NUMTR * RX_NUMSC * RY_NUMBY)
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#define RX_NUMDR 2 /* drives/controller */
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#define RX_M_NUMDR 01
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#define UNIT_V_DEN (UNIT_V_UF + 0) /* double density */
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#define UNIT_V_AUTO (UNIT_V_UF + 1) /* autosize */
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#define UNIT_DEN (1u << UNIT_V_DEN)
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#define UNIT_AUTO (1u << UNIT_V_AUTO)
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#define IDLE 0 /* idle state */
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#define RWDS 1 /* rw, sect next */
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#define RWDT 2 /* rw, track next */
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#define RWXFR 3 /* rw, transfer */
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#define FEWC 4 /* fill empty, wc next */
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#define FEBA 5 /* fill empty, ba next */
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#define FEXFR 6 /* fill empty, transfer */
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#define SDCNF 7 /* set dens, conf next */
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#define SDXFR 8 /* set dens, transfer */
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#define ESBA 9 /* ext sta, ba next */
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#define ESXFR 10 /* ext sta, transfer */
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#define CMD_COMPLETE 11 /* set done next */
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#define INIT_COMPLETE 12 /* init compl next */
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#define RYCS_V_FUNC 1 /* function */
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#define RYCS_M_FUNC 7
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#define RYCS_FILL 0 /* fill buffer */
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#define RYCS_EMPTY 1 /* empty buffer */
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#define RYCS_WRITE 2 /* write sector */
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#define RYCS_READ 3 /* read sector */
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#define RYCS_SDEN 4 /* set density */
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#define RYCS_RYES 5 /* read status */
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#define RYCS_WRDEL 6 /* write del data */
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#define RYCS_ESTAT 7 /* read ext status */
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#define RYCS_V_DRV 4 /* drive select */
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#define RYCS_V_DONE 5 /* done */
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#define RYCS_V_IE 6 /* int enable */
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#define RYCS_V_TR 7 /* xfer request */
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#define RYCS_V_DEN 8 /* density select */
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#define RYCS_V_RY 11 /* RX02 flag */
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#define RYCS_V_UAE 12 /* addr ext */
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#define RYCS_M_UAE 03
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#define RYCS_V_INIT 14 /* init */
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#define RYCS_V_ERR 15 /* error */
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#define RYCS_FUNC (RYCS_M_FUNC << RYCS_V_FUNC)
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#define RYCS_DRV (1u << RYCS_V_DRV)
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#define RYCS_DONE (1u << RYCS_V_DONE)
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#define RYCS_IE (1u << RYCS_V_IE)
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#define RYCS_TR (1u << RYCS_V_TR)
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#define RYCS_DEN (1u << RYCS_V_DEN)
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#define RYCS_RY (1u << RYCS_V_RY)
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#define RYCS_UAE (RYCS_M_UAE << RYCS_V_UAE)
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#define RYCS_INIT (1u << RYCS_V_INIT)
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#define RYCS_ERR (1u << RYCS_V_ERR)
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#define RYCS_IMP (RYCS_ERR+RYCS_UAE+RYCS_DEN+RYCS_TR+RYCS_IE+\
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RYCS_DONE+RYCS_DRV+RYCS_FUNC)
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#define RYCS_RW (RYCS_UAE+RYCS_DEN+RYCS_IE+RYCS_DRV+RYCS_FUNC)
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#define RYCS_GETFNC(x) (((x) >> RYCS_V_FUNC) & RYCS_M_FUNC)
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#define RYCS_GETUAE(x) (((x) >> RYCS_V_UAE) & RYCS_M_UAE)
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#define RYES_CRC 00001 /* CRC error NI */
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#define RYES_ID 00004 /* init done */
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#define RYES_ACLO 00010 /* ACLO NI */
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#define RYES_DERR 00020 /* density err */
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#define RYES_DDEN 00040 /* drive density */
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#define RYES_DD 00100 /* deleted data */
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#define RYES_DRDY 00200 /* drive ready */
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#define RYES_USEL 00400 /* unit selected */
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#define RYES_WCO 02000 /* wc overflow */
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#define RYES_NXM 04000 /* nxm */
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#define RYES_ERR (RYES_NXM|RYES_WCO|RYES_DERR|RYES_ACLO|RYES_CRC)
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#define TRACK u3 /* current track */
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#define CALC_DA(t,s,b) (((t) * RX_NUMSC) + ((s) - 1)) * b
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int32 ry_csr = 0; /* control/status */
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int32 ry_dbr = 0; /* data buffer */
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int32 ry_esr = 0; /* error status */
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uint8 ry_ecode = 0; /* error code */
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uint8 ry_track = 0; /* desired track */
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uint8 ry_sector = 0; /* desired sector */
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int32 ry_ba = 0; /* bus addr */
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uint8 ry_wc = 0; /* word count */
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int32 ry_state = IDLE; /* controller state */
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int32 ry_stopioe = 1; /* stop on error */
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int32 ry_cwait = 100; /* command time */
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int32 ry_swait = 10; /* seek, per track */
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int32 ry_xwait = 1; /* tr set time */
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uint8 rx2xb[RY_NUMBY] = { 0 }; /* sector buffer */
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t_stat ry_rd (int32 *data, int32 PA, int32 access);
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t_stat ry_wr (int32 data, int32 PA, int32 access);
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t_stat ry_svc (UNIT *uptr);
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t_stat ry_reset (DEVICE *dptr);
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t_stat ry_boot (int32 unitno, DEVICE *dptr);
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void ry_done (int32 esr_flags, uint8 new_ecode);
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t_stat ry_set_size (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat ry_attach (UNIT *uptr, CONST char *cptr);
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t_stat ry_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
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const char *ry_description (DEVICE *dptr);
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/* RY11 data structures
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ry_dev RY device descriptor
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ry_unit RY unit list
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ry_reg RY register list
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ry_mod RY modifier list
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*/
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#define IOLN_RY 004
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DIB ry_dib = {
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IOBA_AUTO, IOLN_RY, &ry_rd, &ry_wr,
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1, IVCL (RY), VEC_AUTO, { NULL }, IOLN_RY,
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};
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UNIT ry_unit[] = {
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{ UDATA (&ry_svc, UNIT_DEN+UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF,
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RY_SIZE) },
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{ UDATA (&ry_svc, UNIT_DEN+UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF,
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RY_SIZE) }
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};
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REG ry_reg[] = {
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{ GRDATAD (RYCS, ry_csr, DEV_RDX, 16, 0, "status") },
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{ GRDATAD (RYBA, ry_ba, DEV_RDX, 16, 0, "buffer address") },
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{ GRDATAD (RYWC, ry_wc, DEV_RDX, 8, 0, "word count") },
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{ GRDATAD (RYDB, ry_dbr, DEV_RDX, 16, 0, "data buffer") },
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{ GRDATAD (RYES, ry_esr, DEV_RDX, 12, 0, "error status") },
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{ GRDATAD (RYERR, ry_ecode, DEV_RDX, 8, 0, "error code") },
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{ GRDATAD (RYTA, ry_track, DEV_RDX, 8, 0, "current track") },
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{ GRDATAD (RYSA, ry_sector, DEV_RDX, 8, 0, "current sector") },
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{ DRDATAD (STAPTR, ry_state, 4, "controller state"), REG_RO },
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{ FLDATAD (INT, IREQ (RY), INT_V_RY, "interrupt pending flag") },
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{ FLDATAD (ERR, ry_csr, RYCS_V_ERR, "error flag") },
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{ FLDATAD (TR, ry_csr, RYCS_V_TR, "transfer ready flag ") },
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{ FLDATAD (IE, ry_csr, RYCS_V_IE, "interrupt enable flag ") },
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{ FLDATAD (DONE, ry_csr, RYCS_V_DONE, "device done flag") },
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{ DRDATAD (CTIME, ry_cwait, 24, "command completion time"), PV_LEFT },
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{ DRDATAD (STIME, ry_swait, 24, "seek time, per track"), PV_LEFT },
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{ DRDATAD (XTIME, ry_xwait, 24, "transfer ready delay"), PV_LEFT },
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{ BRDATAD (SBUF, rx2xb, 8, 8, RY_NUMBY, "sector buffer array") },
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{ FLDATAD (STOP_IOE, ry_stopioe, 0, "stop on I/O error") },
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{ URDATA (CAPAC, ry_unit[0].capac, 10, T_ADDR_W, 0,
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RX_NUMDR, REG_HRO | PV_LEFT) },
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{ GRDATA (DEVADDR, ry_dib.ba, DEV_RDX, 32, 0), REG_HRO },
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{ GRDATA (DEVVEC, ry_dib.vec, DEV_RDX, 16, 0), REG_HRO },
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{ NULL }
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};
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MTAB ry_mod[] = {
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{ MTAB_XTD|MTAB_VUN, 0, "write enabled", "WRITEENABLED",
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&set_writelock, &show_writelock, NULL, "Write enable floppy drive" },
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{ MTAB_XTD|MTAB_VUN, 1, NULL, "LOCKED",
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&set_writelock, NULL, NULL, "Write lock floppy drive" },
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{ (UNIT_DEN+UNIT_ATT), UNIT_ATT, "single density", NULL, NULL },
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{ (UNIT_DEN+UNIT_ATT), (UNIT_DEN+UNIT_ATT), "double density", NULL, NULL },
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{ (UNIT_AUTO+UNIT_DEN+UNIT_ATT), 0, "single density", NULL, NULL },
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{ (UNIT_AUTO+UNIT_DEN+UNIT_ATT), UNIT_DEN, "double density", NULL, NULL },
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{ (UNIT_AUTO+UNIT_ATT), UNIT_AUTO, "autosize", NULL, NULL },
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{ UNIT_AUTO, UNIT_AUTO, NULL, "AUTOSIZE",
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NULL, NULL, NULL, "set density based on file size at ATTACH" },
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{ (UNIT_AUTO+UNIT_DEN), 0, NULL, "SINGLE",
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&ry_set_size, NULL, NULL, "Set to Single density (256Kb)" },
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{ (UNIT_AUTO+UNIT_DEN), UNIT_DEN, NULL, "DOUBLE",
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&ry_set_size, NULL, NULL, "Set to Double density (512Kb)" },
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#if defined (VM_PDP11)
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{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 004, "ADDRESS", "ADDRESS",
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&set_addr, &show_addr, NULL, "Bus Address" },
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{ MTAB_XTD | MTAB_VDV, 0, NULL, "AUTOCONFIGURE",
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&set_addr_flt, NULL, NULL, "Enable autoconfiguration of address & vector" },
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{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "VECTOR", "VECTOR",
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&set_vec, &show_vec, NULL, "Interrupt vector" },
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#else
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{ MTAB_XTD|MTAB_VDV, 004, "ADDRESS", NULL,
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NULL, &show_addr, NULL, "Display Bus Address" },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
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NULL, &show_vec, NULL, "Display Interrupt vector" },
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#endif
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{ 0 }
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};
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DEVICE ry_dev = {
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"RY", ry_unit, ry_reg, ry_mod,
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RX_NUMDR, DEV_RDX, 20, 1, DEV_RDX, 8,
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NULL, NULL, &ry_reset,
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&ry_boot, &ry_attach, NULL,
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&ry_dib, DEV_DISABLE | DEV_DISI | DEV_UBUS | DEV_Q18, 0,
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NULL, NULL, NULL, &ry_help, NULL, NULL,
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&ry_description
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};
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/* I/O dispatch routine, I/O addresses 17777170 - 17777172
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17777170 floppy CSR
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17777172 floppy data register
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*/
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t_stat ry_rd (int32 *data, int32 PA, int32 access)
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{
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switch ((PA >> 1) & 1) { /* decode PA<1> */
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case 0: /* RYCS */
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ry_csr = (ry_csr & RYCS_IMP) | RYCS_RY; /* clear junk */
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*data = ry_csr;
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break;
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case 1: /* RYDB */
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*data = ry_dbr; /* return data */
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break;
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} /* end switch PA */
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return SCPE_OK;
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}
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t_stat ry_wr (int32 data, int32 PA, int32 access)
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{
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int32 drv;
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switch ((PA >> 1) & 1) { /* decode PA<1> */
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/* Writing RYCS, three cases:
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1. Writing INIT, reset device
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2. Idle and writing new function
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- clear error, done, transfer ready, int req
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- save int enable, function, drive
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- start new function
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3. Otherwise, write IE and update interrupts
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*/
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case 0: /* RYCS */
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ry_csr = (ry_csr & RYCS_IMP) | RYCS_RY; /* clear junk */
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if (access == WRITEB) data = (PA & 1)? /* write byte? */
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(ry_csr & 0377) | (data << 8): (ry_csr & ~0377) | data;
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if (data & RYCS_INIT) { /* initialize? */
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ry_reset (&ry_dev); /* reset device */
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return SCPE_OK; /* end if init */
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}
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if ((data & CSR_GO) && (ry_state == IDLE)) { /* new function? */
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ry_csr = (data & RYCS_RW) | RYCS_RY;
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drv = ((ry_csr & RYCS_DRV)? 1: 0); /* reselect drv */
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switch (RYCS_GETFNC (data)) {
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case RYCS_FILL: case RYCS_EMPTY:
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ry_state = FEWC; /* state = get wc */
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ry_csr = ry_csr | RYCS_TR; /* xfer is ready */
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break;
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case RYCS_SDEN:
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ry_state = SDCNF; /* state = get conf */
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ry_csr = ry_csr | RYCS_TR; /* xfer is ready */
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break;
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case RYCS_ESTAT:
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ry_state = ESBA; /* state = get ba */
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ry_csr = ry_csr | RYCS_TR; /* xfer is ready */
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break;
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case RYCS_READ: case RYCS_WRITE: case RYCS_WRDEL:
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ry_state = RWDS; /* state = get sector */
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ry_csr = ry_csr | RYCS_TR; /* xfer is ready */
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ry_esr = ry_esr & RYES_ID; /* clear errors */
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ry_ecode = 0;
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break;
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default:
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ry_state = CMD_COMPLETE; /* state = cmd compl */
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sim_activate (&ry_unit[drv], ry_cwait);
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break;
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} /* end switch func */
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return SCPE_OK;
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} /* end if GO */
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if ((data & RYCS_IE) == 0)
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CLR_INT (RY);
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else if ((ry_csr & (RYCS_DONE + RYCS_IE)) == RYCS_DONE)
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SET_INT (RY);
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ry_csr = (ry_csr & ~RYCS_RW) | (data & RYCS_RW);
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break; /* end case RYCS */
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/* Accessing RYDB, two cases:
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1. Write idle, write
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2. Write not idle and TR set, state dependent
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*/
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case 1: /* RYDB */
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if ((PA & 1) || ((ry_state != IDLE) && ((ry_csr & RYCS_TR) == 0)))
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return SCPE_OK; /* if ~IDLE, need tr */
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ry_dbr = data; /* save data */
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if (ry_state != IDLE) {
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drv = ((ry_csr & RYCS_DRV)? 1: 0); /* select drv */
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sim_activate (&ry_unit[drv], ry_xwait); /* sched event */
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ry_csr = ry_csr & ~RYCS_TR; /* clear xfer */
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}
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break; /* end case RYDB */
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} /* end switch PA */
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return SCPE_OK;
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}
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/* Unit service; the action to be taken depends on the transfer state:
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IDLE Should never get here
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FEWC Save word count, set TR, set FEBA
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FEBA Save bus address, set FEXFR
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FEXFR Fill/empty buffer
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RWDS Save sector, set TR, set RWDT
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RWDT Save track, set RWXFR
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RWXFR Read/write buffer
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SDCNF Check confirmation, set SDXFR
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SDXFR Erase disk
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CMD_COMPLETE copy requested data to ir, finish command
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INIT_COMPLETE read drive 0, track 1, sector 1 to buffer, finish command
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*/
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t_stat ry_svc (UNIT *uptr)
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{
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int32 i, t, func, bps;
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static uint8 estat[8];
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uint32 ba, da;
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int8 *fbuf = (int8 *) uptr->filebuf;
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func = RYCS_GETFNC (ry_csr); /* get function */
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bps = (ry_csr & RYCS_DEN)? RY_NUMBY: RX_NUMBY; /* get sector size */
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ba = (RYCS_GETUAE (ry_csr) << 16) | ry_ba; /* get mem addr */
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switch (ry_state) { /* case on state */
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case IDLE: /* idle */
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return SCPE_IERR;
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case FEWC: /* word count */
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ry_wc = ry_dbr & 0377; /* save WC */
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ry_csr = ry_csr | RYCS_TR; /* set TR */
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ry_state = FEBA; /* next state */
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return SCPE_OK;
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case FEBA: /* buffer address */
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ry_ba = ry_dbr; /* save buf addr */
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ry_state = FEXFR; /* next state */
|
|
sim_activate (uptr, ry_cwait); /* schedule xfer */
|
|
return SCPE_OK;
|
|
|
|
case FEXFR: /* transfer */
|
|
if ((ry_wc << 1) > bps) { /* wc too big? */
|
|
ry_done (RYES_WCO, 0230); /* error */
|
|
break;
|
|
}
|
|
if (func == RYCS_FILL) { /* fill? read */
|
|
for (i = 0; i < RY_NUMBY; i++)
|
|
rx2xb[i] = 0;
|
|
t = Map_ReadB (ba, ry_wc << 1, rx2xb);
|
|
}
|
|
else t = Map_WriteB (ba, ry_wc << 1, rx2xb);
|
|
ry_wc = (uint8)(t >> 1); /* adjust wc */
|
|
ry_done (t? RYES_NXM: 0, 0); /* done */
|
|
break;
|
|
|
|
case RWDS: /* wait for sector */
|
|
ry_sector = ry_dbr & RX_M_SECTOR; /* save sector */
|
|
ry_csr = ry_csr | RYCS_TR; /* set xfer */
|
|
ry_state = RWDT; /* advance state */
|
|
return SCPE_OK;
|
|
|
|
case RWDT: /* wait for track */
|
|
ry_track = ry_dbr & RX_M_TRACK; /* save track */
|
|
ry_state = RWXFR; /* next state */
|
|
sim_activate (uptr, /* sched xfer */
|
|
ry_swait * abs (ry_track - uptr->TRACK));
|
|
return SCPE_OK;
|
|
|
|
case RWXFR: /* read/write */
|
|
if ((uptr->flags & UNIT_BUF) == 0) { /* not buffered? */
|
|
ry_done (0, 0110); /* done, error */
|
|
return IORETURN (ry_stopioe, SCPE_UNATT);
|
|
}
|
|
if (ry_track >= RX_NUMTR) { /* bad track? */
|
|
ry_done (0, 0040); /* done, error */
|
|
break;
|
|
}
|
|
uptr->TRACK = ry_track; /* now on track */
|
|
if ((ry_sector == 0) || (ry_sector > RX_NUMSC)) { /* bad sect? */
|
|
ry_done (0, 0070); /* done, error */
|
|
break;
|
|
}
|
|
if (((uptr->flags & UNIT_DEN) != 0) ^
|
|
((ry_csr & RYCS_DEN) != 0)) { /* densities agree? */
|
|
ry_done (RYES_DERR, 0240); /* no, error */
|
|
break;
|
|
}
|
|
da = CALC_DA (ry_track, ry_sector, bps); /* get disk address */
|
|
if (func == RYCS_WRDEL) /* del data? */
|
|
ry_esr = ry_esr | RYES_DD;
|
|
if (func == RYCS_READ) { /* read? */
|
|
for (i = 0; i < bps; i++)
|
|
rx2xb[i] = fbuf[da + i];
|
|
}
|
|
else {
|
|
if (uptr->flags & UNIT_WPRT) { /* write and locked? */
|
|
ry_done (0, 0100); /* done, error */
|
|
break;
|
|
}
|
|
for (i = 0; i < bps; i++) /* write */
|
|
fbuf[da + i] = rx2xb[i];
|
|
da = da + bps;
|
|
if (da > uptr->hwmark)
|
|
uptr->hwmark = da;
|
|
}
|
|
ry_done (0, 0); /* done */
|
|
break;
|
|
|
|
case SDCNF: /* confirm set density */
|
|
if ((ry_dbr & 0377) != 0111) { /* confirmed? */
|
|
ry_done (0, 0250); /* no, error */
|
|
break;
|
|
}
|
|
ry_state = SDXFR; /* next state */
|
|
sim_activate (uptr, ry_cwait * 100); /* schedule operation */
|
|
break;
|
|
|
|
case SDXFR: /* erase disk */
|
|
for (i = 0; i < (int32) uptr->capac; i++)
|
|
fbuf[i] = 0;
|
|
uptr->hwmark = (uint32) uptr->capac;
|
|
if (ry_csr & RYCS_DEN)
|
|
uptr->flags = uptr->flags | UNIT_DEN;
|
|
else uptr->flags = uptr->flags & ~UNIT_DEN;
|
|
ry_done (0, 0);
|
|
break;
|
|
|
|
|
|
case ESBA:
|
|
ry_ba = ry_dbr; /* save WC */
|
|
ry_state = ESXFR; /* next state */
|
|
sim_activate (uptr, ry_cwait); /* schedule xfer */
|
|
return SCPE_OK;
|
|
|
|
case ESXFR:
|
|
estat[0] = ry_ecode; /* fill 8B status */
|
|
estat[1] = ry_wc;
|
|
estat[2] = (uint8)ry_unit[0].TRACK;
|
|
estat[3] = (uint8)ry_unit[1].TRACK;
|
|
estat[4] = ry_track;
|
|
estat[5] = ry_sector;
|
|
estat[6] = ((ry_csr & RYCS_DRV)? 0200: 0) |
|
|
((ry_unit[1].flags & UNIT_DEN)? 0100: 0) |
|
|
((uptr->flags & UNIT_ATT)? 0040: 0) |
|
|
((ry_unit[0].flags & UNIT_DEN)? 0020: 0) |
|
|
((ry_csr & RYCS_DEN)? 0001: 0);
|
|
estat[7] = (uint8)uptr->TRACK;
|
|
t = Map_WriteB (ba, 8, estat); /* DMA to memory */
|
|
ry_done (t? RYES_NXM: 0, 0); /* done */
|
|
break;
|
|
|
|
case CMD_COMPLETE: /* command complete */
|
|
ry_done (0, 0);
|
|
break;
|
|
|
|
case INIT_COMPLETE: /* init complete */
|
|
ry_unit[0].TRACK = 1; /* drive 0 to trk 1 */
|
|
ry_unit[1].TRACK = 0; /* drive 1 to trk 0 */
|
|
if ((uptr->flags & UNIT_BUF) == 0) { /* not buffered? */
|
|
ry_done (RYES_ID, 0010); /* init done, error */
|
|
break;
|
|
}
|
|
da = CALC_DA (1, 1, bps); /* track 1, sector 1 */
|
|
for (i = 0; i < bps; i++) /* read sector */
|
|
rx2xb[i] = fbuf[da + i];
|
|
ry_done (RYES_ID, 0); /* set done */
|
|
if ((ry_unit[1].flags & UNIT_ATT) == 0)
|
|
ry_ecode = 0020;
|
|
break;
|
|
} /* end case state */
|
|
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Command complete. Set done and put final value in interface register,
|
|
request interrupt if needed, return to IDLE state.
|
|
*/
|
|
|
|
void ry_done (int32 esr_flags, uint8 new_ecode)
|
|
{
|
|
int32 drv = (ry_csr & RYCS_DRV)? 1: 0;
|
|
|
|
ry_state = IDLE; /* now idle */
|
|
ry_csr = ry_csr | RYCS_DONE; /* set done */
|
|
if (ry_csr & CSR_IE) /* if ie, intr */
|
|
SET_INT (RY);
|
|
ry_esr = (ry_esr | esr_flags) & ~(RYES_USEL|RYES_DDEN|RYES_DRDY);
|
|
if (drv) /* updates RYES */
|
|
ry_esr = ry_esr | RYES_USEL;
|
|
if (ry_unit[drv].flags & UNIT_ATT) {
|
|
ry_esr = ry_esr | RYES_DRDY;
|
|
if (ry_unit[drv].flags & UNIT_DEN)
|
|
ry_esr = ry_esr | RYES_DDEN;
|
|
}
|
|
if ((new_ecode > 0) || (ry_esr & RYES_ERR)) /* test for error */
|
|
ry_csr = ry_csr | RYCS_ERR;
|
|
ry_ecode = new_ecode; /* update ecode */
|
|
ry_dbr = ry_esr; /* update RYDB */
|
|
return;
|
|
}
|
|
|
|
/* Device initialization. The RY is one of the few devices that schedules
|
|
an I/O transfer as part of its initialization.
|
|
*/
|
|
|
|
t_stat ry_reset (DEVICE *dptr)
|
|
{
|
|
ry_csr = ry_dbr = 0; /* clear registers */
|
|
ry_esr = ry_ecode = 0; /* clear error */
|
|
ry_ba = ry_wc = 0; /* clear wc, ba */
|
|
ry_track = ry_sector = 0; /* clear trk, sector */
|
|
ry_state = IDLE; /* ctrl idle */
|
|
CLR_INT (RY); /* clear int req */
|
|
sim_cancel (&ry_unit[1]); /* cancel drive 1 */
|
|
if (dptr->flags & UNIT_DIS) /* disabled? */
|
|
sim_cancel (&ry_unit[0]);
|
|
else if (ry_unit[0].flags & UNIT_BUF) { /* attached? */
|
|
ry_state = INIT_COMPLETE; /* yes, sched init */
|
|
sim_activate (&ry_unit[0], ry_swait * abs (1 - ry_unit[0].TRACK));
|
|
}
|
|
else ry_done (RYES_ID, 0010); /* no, error */
|
|
return auto_config (dptr->name, 1); /* run autoconfig */
|
|
}
|
|
|
|
/* Attach routine */
|
|
|
|
t_stat ry_attach (UNIT *uptr, CONST char *cptr)
|
|
{
|
|
uint32 sz;
|
|
|
|
if ((uptr->flags & UNIT_AUTO) && (sz = sim_fsize_name (cptr))) {
|
|
if (sz > RX_SIZE)
|
|
uptr->flags = uptr->flags | UNIT_DEN;
|
|
else uptr->flags = uptr->flags & ~UNIT_DEN;
|
|
}
|
|
uptr->capac = (uptr->flags & UNIT_DEN)? RY_SIZE: RX_SIZE;
|
|
return attach_unit (uptr, cptr);
|
|
}
|
|
|
|
/* Set size routine */
|
|
|
|
t_stat ry_set_size (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
|
|
{
|
|
if (uptr->flags & UNIT_ATT)
|
|
return SCPE_ALATT;
|
|
uptr->capac = val? RY_SIZE: RX_SIZE;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Device bootstrap */
|
|
|
|
#if defined (VM_PDP11)
|
|
|
|
#define BOOT_START 02000 /* start */
|
|
#define BOOT_ENTRY (BOOT_START + 002) /* entry */
|
|
#define BOOT_UNIT (BOOT_START + 010) /* unit number */
|
|
#define BOOT_CSR (BOOT_START + 026) /* CSR */
|
|
#define BOOT_LEN (sizeof (boot_rom) / sizeof (int16))
|
|
|
|
static const uint16 boot_rom[] = {
|
|
042131, /* "YD" */
|
|
0012706, BOOT_START, /* MOV #boot_start, SP */
|
|
0012700, 0000000, /* MOV #unit, R0 ; unit number */
|
|
0010003, /* MOV R0, R3 */
|
|
0006303, /* ASL R3 */
|
|
0006303, /* ASL R3 */
|
|
0006303, /* ASL R3 */
|
|
0006303, /* ASL R3 */
|
|
0012701, 0177170, /* MOV #RYCS, R1 ; csr */
|
|
0005002, /* CLR R2 ; ba */
|
|
0005004, /* CLR R4 ; density */
|
|
0012705, 0000001, /* MOV #1, R5 ; sector */
|
|
0005104, /* DN: COM R4 ; compl dens */
|
|
0042704, 0177377, /* BIC #177377, R4 ; clr rest */
|
|
0032711, 0000040, /* RD: BIT #40, (R1) ; ready? */
|
|
0001775, /* BEQ .-4 */
|
|
0012746, 0000007, /* MOV #READ+GO, -(SP) */
|
|
0050316, /* BIS R3, (SP) ; or unit */
|
|
0050416, /* BIS R4, (SP) ; or density */
|
|
0012611, /* MOV (SP)+, (R1) ; read & go */
|
|
0105711, /* TSTB (R1) ; xfr ready? */
|
|
0100376, /* BPL .-2 */
|
|
0010561, 0000002, /* MOV R5, 2(R1) ; sector */
|
|
0105711, /* TSTB (R1) ; xfr ready? */
|
|
0100376, /* BPL .-2 */
|
|
0012761, 0000001, 0000002, /* MOV #1, 2(R1) ; track */
|
|
0032711, 0000040, /* BIT #40, (R1) ; ready? */
|
|
0001775, /* BEQ .-4 */
|
|
0005711, /* TST (R1) ; error? */
|
|
0100003, /* BEQ OK */
|
|
0005704, /* TST R4 ; single? */
|
|
0001345, /* BNE DN ; no, try again */
|
|
0000000, /* HALT ; dead */
|
|
0012746, 0000003, /* OK: MOV #EMPTY+GO, -(SP); empty & go */
|
|
0050416, /* BIS R4, (SP) ; or density */
|
|
0012611, /* MOV (SP)+, (R1) ; read & go */
|
|
0105711, /* TSTB (R1) ; xfr, done? */
|
|
0001776, /* BPL .-2 */
|
|
0012746, 0000100, /* MOV #100, -(SP) ; assume sd */
|
|
0005704, /* TST R4 ; test dd */
|
|
0001401, /* BEQ .+4 */
|
|
0006316, /* ASL (SP) ; dd, double */
|
|
0011661, 0000002, /* MOV (SP), 2(R1) ; wc */
|
|
0105711, /* TSTB (R1) ; xfr, done? */
|
|
0001776, /* BPL .-2 */
|
|
0010261, 0000002, /* MOV R2, 2(R1) ; ba */
|
|
0032711, 0000040, /* BIT #40, (R1) ; ready? */
|
|
0001775, /* BEQ .-4 */
|
|
0061602, /* ADD (SP), R2 ; cvt wd to byte */
|
|
0062602, /* ADD (SP)+, R2 ; adv buf addr */
|
|
0122525, /* CMPB (R5)+, (R5)+ ; sect += 2 */
|
|
0020527, 0000007, /* CMP R5, #7 ; end? */
|
|
0101715, /* BLOS RD ; read next */
|
|
0005002, /* CLR R2 */
|
|
0005003, /* CLR R3 */
|
|
0012704, BOOT_START+020, /* MOV #START+20, R4 */
|
|
0005005, /* CLR R5 */
|
|
0005007 /* CLR R7 */
|
|
};
|
|
|
|
t_stat ry_boot (int32 unitno, DEVICE *dptr)
|
|
{
|
|
size_t i;
|
|
|
|
if ((ry_unit[unitno & RX_M_NUMDR].flags & UNIT_DEN) == 0)
|
|
return SCPE_NOFNC;
|
|
for (i = 0; i < BOOT_LEN; i++)
|
|
WrMemW (BOOT_START + (2 * i), boot_rom[i]);
|
|
WrMemW (BOOT_UNIT, unitno & RX_M_NUMDR);
|
|
WrMemW (BOOT_CSR, ry_dib.ba & DMASK);
|
|
cpu_set_boot (BOOT_ENTRY);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
#else
|
|
|
|
t_stat ry_boot (int32 unitno, DEVICE *dptr)
|
|
{
|
|
return SCPE_NOFNC;
|
|
}
|
|
|
|
#endif
|
|
|
|
t_stat ry_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
|
|
{
|
|
fprintf (st, "RX211/RX02 Floppy Disk\n\n");
|
|
fprintf (st, "RX211 options include the ability to set units write enabled or write locked,\n");
|
|
fprintf (st, "single or double density, or autosized:\n\n");
|
|
fprint_set_help (st, dptr);
|
|
fprint_show_help (st, dptr);
|
|
fprintf (st, "\n");
|
|
#if defined (VM_PDP11)
|
|
fprintf (st, "The RX211 supports the BOOT command.\n\n");
|
|
#endif
|
|
fprintf (st, "The RX211 is disabled in a Qbus system with more than 256KB of memory.\n\n");
|
|
fprint_reg_help (st, dptr);
|
|
fprintf (st, "\nError handling is as follows:\n\n");
|
|
fprintf (st, " error STOP_IOE processed as\n");
|
|
fprintf (st, " not attached 1 report error and stop\n");
|
|
fprintf (st, " 0 disk not ready\n\n");
|
|
fprintf (st, "RX02 data files are buffered in memory; therefore, end of file and OS I/O\n");
|
|
fprintf (st, "errors cannot occur.\n");
|
|
return SCPE_OK;
|
|
}
|
|
|
|
const char *ry_description (DEVICE *dptr)
|
|
{
|
|
return (UNIBUS) ? "RX211 floppy disk controller" :
|
|
"RXV21 floppy disk controller";
|
|
}
|