84bf5f4d14
This change updates the 3B2 README.md file, and fixes all line endings on 3B2 source files.
481 lines
15 KiB
C
481 lines
15 KiB
C
/* 3b2_dmac.c: AM9517 DMA Controller
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Copyright (c) 2021-2022, Seth J. Morabito
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Permission is hereby granted, free of charge, to any person
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obtaining a copy of this software and associated documentation
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files (the "Software"), to deal in the Software without
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restriction, including without limitation the rights to use, copy,
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modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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Except as contained in this notice, the name of the author shall
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not be used in advertising or otherwise to promote the sale, use or
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other dealings in this Software without prior written authorization
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from the author.
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*/
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#include "3b2_dmac.h"
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#if defined(REV2)
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#include "3b2_id.h"
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#endif
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#include "3b2_cpu.h"
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#include "3b2_if.h"
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#include "3b2_iu.h"
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#include "3b2_mem.h"
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#include "3b2_stddev.h"
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#include "3b2_csr.h"
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DMA_STATE dma_state;
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UNIT dmac_unit[] = {
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{ UDATA (NULL, 0, 0), 0, 0 },
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{ UDATA (NULL, 0, 0), 0, 1 },
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{ UDATA (NULL, 0, 0), 0, 2 },
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{ UDATA (NULL, 0, 0), 0, 3 },
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{ NULL }
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};
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REG dmac_reg[] = {
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{ NULL }
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};
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DEVICE dmac_dev = {
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"DMAC", dmac_unit, dmac_reg, NULL,
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1, 16, 8, 4, 16, 32,
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NULL, NULL, &dmac_reset,
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NULL, NULL, NULL, NULL,
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DEV_DEBUG, 0, sys_deb_tab
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};
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dmac_dma_handler device_dma_handlers[] = {
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#if defined(REV2)
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{DMA_ID_CHAN, IDBASE+ID_DATA_REG, &id_drq, dmac_generic_dma, id_after_dma},
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#endif
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{DMA_IF_CHAN, IFBASE+IF_DATA_REG, &if_state.drq, dmac_generic_dma, if_after_dma},
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{DMA_IUA_CHAN, IUBASE+IUA_DATA_REG, &iu_console.drq, iu_dma_console, NULL},
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{DMA_IUB_CHAN, IUBASE+IUB_DATA_REG, &iu_contty.drq, iu_dma_contty, NULL},
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{0, 0, NULL, NULL, NULL }
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};
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uint32 dma_address(uint8 channel, uint32 offset) {
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uint32 addr, page;
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if (DMA_DECR(channel)) {
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addr = (PHYS_MEM_BASE + (uint32)(dma_state.channels[channel].addr) - offset);
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} else {
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addr = (PHYS_MEM_BASE + (uint32)(dma_state.channels[channel].addr) + offset);
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}
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#if defined (REV3)
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page = (uint32)dma_state.channels[channel].page;
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#else
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/* In Rev 2, the top bit of the page address is a R/W bit, so
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we mask it here */
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page = (uint32)dma_state.channels[channel].page & 0x7f;
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#endif
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addr |= page << 16;
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return addr;
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}
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t_stat dmac_reset(DEVICE *dptr)
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{
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int i;
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memset(&dma_state, 0, sizeof(dma_state));
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for (i = 0; i < 4; i++) {
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dma_state.channels[i].page = 0;
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dma_state.channels[i].addr = 0;
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dma_state.channels[i].mode = 0;
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dma_state.channels[i].wcount = 0;
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dma_state.channels[i].addr_c = 0;
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dma_state.channels[i].wcount_c = -1;
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dma_state.channels[i].ptr = 0;
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}
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return SCPE_OK;
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}
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uint32 dmac_read(uint32 pa, size_t size)
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{
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uint8 reg, base, data;
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base = (uint8) (pa >> 12);
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reg = pa & 0xff;
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switch (base) {
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case DMA_C:
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switch (reg) {
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case 0: /* channel 0 current address reg */
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data = ((dma_state.channels[0].addr_c) >> (dma_state.bff * 8)) & 0xff;
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sim_debug(READ_MSG, &dmac_dev,
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"Reading Channel 0 Addr Reg: %08x\n",
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data);
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dma_state.bff ^= 1;
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break;
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case 1: /* channel 0 current address reg */
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data = ((dma_state.channels[0].wcount_c) >> (dma_state.bff * 8)) & 0xff;
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sim_debug(READ_MSG, &dmac_dev,
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"Reading Channel 0 Addr Count Reg: %08x\n",
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data);
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dma_state.bff ^= 1;
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break;
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case 2: /* channel 1 current address reg */
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data = ((dma_state.channels[1].addr_c) >> (dma_state.bff * 8)) & 0xff;
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sim_debug(READ_MSG, &dmac_dev,
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"Reading Channel 1 Addr Reg: %08x\n",
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data);
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dma_state.bff ^= 1;
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break;
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case 3: /* channel 1 current address reg */
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data = ((dma_state.channels[1].wcount_c) >> (dma_state.bff * 8)) & 0xff;
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sim_debug(READ_MSG, &dmac_dev,
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"Reading Channel 1 Addr Count Reg: %08x\n",
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data);
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dma_state.bff ^= 1;
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break;
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case 4: /* channel 2 current address reg */
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data = ((dma_state.channels[2].addr_c) >> (dma_state.bff * 8)) & 0xff;
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sim_debug(READ_MSG, &dmac_dev,
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"Reading Channel 2 Addr Reg: %08x\n",
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data);
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dma_state.bff ^= 1;
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break;
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case 5: /* channel 2 current address reg */
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data = ((dma_state.channels[2].wcount_c) >> (dma_state.bff * 8)) & 0xff;
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sim_debug(READ_MSG, &dmac_dev,
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"Reading Channel 2 Addr Count Reg: %08x\n",
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data);
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dma_state.bff ^= 1;
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break;
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case 6: /* channel 3 current address reg */
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data = ((dma_state.channels[3].addr_c) >> (dma_state.bff * 8)) & 0xff;
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sim_debug(READ_MSG, &dmac_dev,
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"Reading Channel 3 Addr Reg: %08x\n",
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data);
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dma_state.bff ^= 1;
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break;
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case 7: /* channel 3 current address reg */
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data = ((dma_state.channels[3].wcount_c) >> (dma_state.bff * 8)) & 0xff;
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sim_debug(READ_MSG, &dmac_dev,
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"Reading Channel 3 Addr Count Reg: %08x\n",
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data);
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dma_state.bff ^= 1;
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break;
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case 8:
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data = dma_state.status;
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sim_debug(READ_MSG, &dmac_dev,
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"Reading DMAC Status %08x\n",
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data);
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dma_state.status = 0;
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break;
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default:
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sim_debug(READ_MSG, &dmac_dev,
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"DMAC READ %lu B @ %08x\n",
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size, pa);
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data = 0;
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}
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return data;
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default:
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sim_debug(READ_MSG, &dmac_dev,
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"[BASE: %08x] DMAC READ %lu B @ %08x\n",
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base, size, pa);
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return 0;
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}
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}
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/*
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* Program the DMAC
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*/
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void dmac_program(uint8 reg, uint8 val)
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{
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uint8 channel_id, i, chan_num;
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dma_channel *channel;
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#if defined(REV3)
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/* TODO: More general DMA interrupt clearing */
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CPU_CLR_INT(INT_UART_DMA);
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CLR_CSR(CSRDMA);
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#endif
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if (reg < 8) {
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switch (reg) {
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case 0:
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case 1:
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chan_num = 0;
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break;
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case 2:
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case 3:
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chan_num = 1;
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break;
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case 4:
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case 5:
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chan_num = 2;
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break;
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case 6:
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case 7:
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chan_num = 3;
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break;
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default:
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chan_num = 0;
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break;
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}
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channel = &dma_state.channels[chan_num];
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switch (reg & 1) {
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case 0: /* Address */
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channel->addr &= ~(0xff << dma_state.bff * 8);
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channel->addr |= (val & 0xff) << (dma_state.bff * 8);
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channel->addr_c = channel->addr;
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sim_debug(WRITE_MSG, &dmac_dev,
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"Set address channel %d byte %d = %08x\n",
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chan_num, dma_state.bff, channel->addr);
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break;
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case 1: /* Word Count */
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channel->wcount &= ~(0xff << dma_state.bff * 8);
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channel->wcount |= (val & 0xff) << (dma_state.bff * 8);
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channel->wcount_c = channel->wcount;
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channel->ptr = 0;
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sim_debug(WRITE_MSG, &dmac_dev,
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"Set word count channel %d byte %d = %08x\n",
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chan_num, dma_state.bff, channel->wcount);
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break;
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}
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/* Toggle the byte flip-flop */
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dma_state.bff ^= 1;
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/* Handled. */
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return;
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}
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/* If it hasn't been handled, it must be one of the following
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registers. */
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switch (reg) {
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case 8: /* Command */
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dma_state.command = val;
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sim_debug(WRITE_MSG, &dmac_dev,
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"Command: val=%02x\n",
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val);
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break;
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case 9: /* Request */
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sim_debug(WRITE_MSG, &dmac_dev,
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"Request set: val=%02x\n",
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val);
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dma_state.request = val;
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break;
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case 10: /* Write Single Mask Register Bit */
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channel_id = val & 3;
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/* "Clear or Set" is bit 2 */
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if ((val >> 2) & 1) {
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dma_state.mask |= (1 << channel_id);
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} else {
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dma_state.mask &= ~(1 << channel_id);
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/* Set the appropriate DRQ */
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/* *dmac_drq_handlers[channel_id].drq = TRUE; */
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}
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sim_debug(WRITE_MSG, &dmac_dev,
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"Write Single Mask Register Bit. channel=%d set/clear=%02x\n",
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channel_id, (val >> 2) & 1);
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break;
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case 11: /* Mode */
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channel_id = val & 3;
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sim_debug(WRITE_MSG, &dmac_dev,
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"Mode Set. channel=%d val=%02x\n",
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channel_id, val);
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dma_state.channels[channel_id].mode = val;
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break;
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case 12: /* Clear Byte Pointer Flip/Flop */
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dma_state.bff = 0;
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break;
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case 13: /* Master Clear */
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dma_state.bff = 0;
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dma_state.command = 0;
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dma_state.status = 0;
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for (i = 0; i < 4; i++) {
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dma_state.channels[i].page = 0;
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dma_state.channels[i].addr = 0;
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dma_state.channels[i].wcount = 0;
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dma_state.channels[i].addr_c = 0;
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dma_state.channels[i].wcount_c = -1;
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dma_state.channels[i].ptr = 0;
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}
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break;
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case 15: /* Write All Mask Register Bits */
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sim_debug(WRITE_MSG, &dmac_dev,
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"Write DMAC mask (all bits). Val=%02x\n",
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val);
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dma_state.mask = val & 0xf;
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break;
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case 16: /* Clear DMAC Interrupt */
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sim_debug(WRITE_MSG, &dmac_dev,
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"Clear DMA Interrupt in DMAC. val=%02x\n",
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val);
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break;
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default:
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sim_debug(WRITE_MSG, &dmac_dev,
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"Unhandled DMAC write. reg=%x val=%02x\n",
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reg, val);
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break;
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}
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}
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void dmac_page_update(uint8 base, uint8 reg, uint8 val)
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{
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uint8 shift = 0;
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/* Sanity check */
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if (reg > 3) {
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return;
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}
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#if defined(REV2)
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/* In Rev2 systems, the actual register is a 32-bit,
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byte-addressed register, so that address 4x000 is the highest
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byte, 4x003 is the lowest byte. */
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shift = -(reg - 3) * 8;
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#endif
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switch (base) {
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#if defined (REV2)
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case DMA_ID:
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sim_debug(WRITE_MSG, &dmac_dev, "Set page channel 0 = %x\n", val);
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dma_state.channels[DMA_ID_CHAN].page &= ~(0xff << shift);
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dma_state.channels[DMA_ID_CHAN].page |= ((uint16)val << shift);
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break;
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#endif
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case DMA_IF:
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sim_debug(WRITE_MSG, &dmac_dev, "Set page channel 1 = %x\n", val);
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dma_state.channels[DMA_IF_CHAN].page &= ~(0xff << shift);
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dma_state.channels[DMA_IF_CHAN].page |= ((uint16)val << shift);
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break;
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case DMA_IUA:
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sim_debug(WRITE_MSG, &dmac_dev, "Set page channel 2 = %x\n", val);
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dma_state.channels[DMA_IUA_CHAN].page &= ~(0xff << shift);
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dma_state.channels[DMA_IUA_CHAN].page |= ((uint16)val << shift);
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break;
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case DMA_IUB:
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sim_debug(WRITE_MSG, &dmac_dev, "Set page channel 3 = %x\n", val);
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dma_state.channels[DMA_IUB_CHAN].page &= ~(0xff << shift);
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dma_state.channels[DMA_IUB_CHAN].page |= ((uint16)val << shift);
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break;
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}
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}
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void dmac_write(uint32 pa, uint32 val, size_t size)
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{
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uint8 reg, base;
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base = (uint8) (pa >> 12);
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reg = pa & 0xff;
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switch (base) {
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case DMA_C:
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dmac_program(reg, (uint8) val);
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break;
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#if defined (REV2)
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case DMA_ID:
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#endif
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case DMA_IUA:
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case DMA_IUB:
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case DMA_IF:
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dmac_page_update(base, reg, (uint8) val);
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break;
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}
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}
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void dmac_generic_dma(uint8 channel, uint32 service_address)
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{
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uint8 data;
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int32 i;
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uint32 addr;
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dma_channel *chan = &dma_state.channels[channel];
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i = chan->wcount_c;
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/* TODO: This assumes every transfer is a block mode, which is not
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guaranteed to be valid, but is likely safe? */
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switch (DMA_XFER(channel)) {
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case DMA_XFER_VERIFY:
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sim_debug(EXECUTE_MSG, &dmac_dev,
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"[dmac_generic_dma channel=%d] unhandled VERIFY request.\n",
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channel);
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break;
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case DMA_XFER_WRITE:
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sim_debug(EXECUTE_MSG, &dmac_dev,
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"[dmac_generic_dma channel=%d] write: %d bytes to %08x from %08x (page=%04x addr=%08x)\n",
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channel,
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chan->wcount + 1,
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dma_address(channel, 0),
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service_address,
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dma_state.channels[channel].page,
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dma_state.channels[channel].addr);
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for (; i >= 0; i--) {
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chan->wcount_c--;
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addr = dma_address(channel, chan->ptr++);
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chan->addr_c = addr;
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data = pread_b(service_address, BUS_PER);
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write_b(addr, data, BUS_PER);
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}
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break;
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case DMA_XFER_READ:
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sim_debug(EXECUTE_MSG, &dmac_dev,
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"[dmac_generic_dma channel=%d] read: %d bytes from %08x to %08x\n",
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channel,
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chan->wcount + 1,
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dma_address(channel, 0),
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service_address);
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for (; i >= 0; i--) {
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chan->wcount_c = i;
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addr = dma_address(channel, chan->ptr++);
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chan->addr_c = addr;
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data = pread_b(addr, BUS_PER);
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write_b(service_address, data, BUS_PER);
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}
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break;
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}
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/* End of Process must set the channel's mask bit */
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dma_state.mask |= (1 << channel);
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dma_state.status |= (1 << channel);
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}
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/*
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* Service pending DRQs
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*/
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void dmac_service_drqs()
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{
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volatile dmac_dma_handler *h;
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for (h = &device_dma_handlers[0]; h->drq != NULL; h++) {
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/* Only trigger if the channel has a DRQ set and its channel's
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mask bit is 0 */
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if (*h->drq && ((dma_state.mask >> h->channel) & 0x1) == 0) {
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h->dma_handler(h->channel, h->service_address);
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/* Each handler is responsible for clearing its own DRQ line! */
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if (h->after_dma_callback != NULL) {
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h->after_dma_callback();
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}
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}
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}
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}
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