84bf5f4d14
This change updates the 3B2 README.md file, and fixes all line endings on 3B2 source files.
234 lines
8.1 KiB
C
234 lines
8.1 KiB
C
/* 3b2_iu.h: SCN2681A Dual UART
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Copyright (c) 2017-2022, Seth J. Morabito
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Permission is hereby granted, free of charge, to any person
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obtaining a copy of this software and associated documentation
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files (the "Software"), to deal in the Software without
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restriction, including without limitation the rights to use, copy,
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modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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Except as contained in this notice, the name of the author shall
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not be used in advertising or otherwise to promote the sale, use or
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other dealings in this Software without prior written authorization
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from the author.
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*/
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#ifndef __3B2_IU_H__
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#define __3B2_IU_H__
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#include "3b2_defs.h"
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#define CMD_ERX 0x01 /* Enable receiver */
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#define CMD_DRX 0x02 /* Disable receiver */
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#define CMD_ETX 0x04 /* Enable transmitter */
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#define CMD_DTX 0x08 /* Disable transmitter */
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#define CMD_MISC_SHIFT 4 /* Command */
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#define CMD_MISC_MASK 0x7
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#define IU_SPEED_REGS 2 /* Two speed select registers, */
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#define IU_SPEEDS 16 /* with 16 speeds each */
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#define IU_PARITY_ODD 0
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#define IU_PARITY_EVEN 1
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#define IU_PARITY_NONE 2
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#define STS_RXR 0x01 /* Receiver ready */
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#define STS_FFL 0x02 /* FIFO full */
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#define STS_TXR 0x04 /* Transmitter ready */
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#define STS_TXE 0x08 /* Transmitter empty */
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#define STS_OER 0x10 /* Overrun error */
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#define STS_PER 0x20 /* Parity error */
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#define STS_FER 0x40 /* Framing error */
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#define STS_RXB 0x80 /* Received break */
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#define ISTS_TXRA 0x01 /* Transmitter ready A */
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#define ISTS_RXRA 0x02 /* Receiver ready A */
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#define ISTS_DBA 0x04 /* Delta Break A */
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#define ISTS_CRI 0x08 /* Counter ready */
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#define ISTS_TXRB 0x10 /* Transmitter ready B */
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#define ISTS_RXRB 0x20 /* Receiver ready B */
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#define ISTS_DBB 0x40 /* Delta Break B */
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#define ISTS_IPC 0x80 /* Interrupt port change */
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#define MODE_V_CHM 6 /* Channel mode */
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#define MODE_M_CHM 0x3
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/* Transmitter State bits */
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#define T_HOLD 1
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#define T_XMIT 2
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/* Used by the DMAC */
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#define IUA_DATA_REG 3
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#define IUB_DATA_REG 11
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/* Registers - Read */
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#define SRA 1
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#define RHRA 3
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#define IPCR 4
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#define ISR 5
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#define CTU 6
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#define CTL 7
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#define SRB 9
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#define RHRB 11
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#define INPRT 13
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#define START_CTR 14
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#define STOP_CTR 15
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/* Registers - Write */
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#define CSRA 1
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#define CRA 2
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#define THRA 3
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#define ACR 4
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#define IMR 5
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#define CTUR 6
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#define CTLR 7
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#define CSRB 9
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#define CRB 10
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#define THRB 11
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#define OPCR 13
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#define SOPR 14
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#define ROPR 15
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/* Registers - R/W */
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#define MR12A 0
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#define MR12B 8
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/* Port configuration */
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#define TX_EN 1
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#define RX_EN 2
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/* Control Register commands */
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#define CR_RST_MR 1
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#define CR_RST_RX 2
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#define CR_RST_TX 3
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#define CR_RST_ERR 4
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#define CR_RST_BRK 5
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#define CR_START_BRK 6
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#define CR_STOP_BRK 7
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/* IMR bits */
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#define IMR_TXRA 0x01
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#define IMR_RXRA 0x02
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#define IMR_CTR 0x08
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#define IMR_TXRB 0x10
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#define IMR_RXRB 0x20
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/* Power-off bit */
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#define IU_KILLPWR 0x04
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#define PORT_A 0
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#define PORT_B 1
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#define IU_MODE(x) ((x & UM_MASK) >> UM_SHIFT)
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#define IUBASE 0x49000
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#define IUSIZE 0x100
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#define IU_BUF_SIZE 3
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/* Data Carrier Detect inputs and input change bits */
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#if defined(REV3)
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#define IU_DCDB_CH 0x80
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#define IU_DCDA_CH 0x40
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#define IU_DCDB 0x08
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#define IU_DCDA 0x04
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#else
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#define IU_DCDB_CH 0x20
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#define IU_DCDA_CH 0x10
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#define IU_DCDB 0x02
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#define IU_DCDA 0x01
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#endif
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/* Default baud rate generator (9600 baud) */
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#define BRG_DEFAULT 11
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/* The 2681 DUART includes a 16-bit timer/counter that can be used to
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* trigger an interrupt after a certain amount of time has passed.
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*
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* The 2681 uses a crystal with a frequency of 3.686400 MHz, and the
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* timer/counter uses this frequency divided by 16, giving a final
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* timer/counter frequency of 230,400 Hz. There are therefore 4.34
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* microseconds of wall time per tick of the timer.
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*
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* The multiplier defined below is a default that can be adjusted to
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* make IU timing faster, but less accurate, if desired */
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#define IU_TIMER_MULTIPLIER 4
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typedef struct iu_port {
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uint8 cmd; /* Command */
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uint8 mode[2]; /* Two mode buffers */
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uint8 modep; /* Point to mode[0] or mode[1] */
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uint8 conf; /* Configuration bits */
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uint8 sr; /* Status Register */
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uint8 thr; /* Transmit Holding Register */
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uint8 txr; /* Transmit Shift Register */
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uint8 rxr; /* Receive Shift Register */
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uint8 rxbuf[IU_BUF_SIZE]; /* Receive Holding Register (3 bytes) */
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uint8 w_p; /* Receive Buffer Write Pointer */
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uint8 r_p; /* Receive Buffer Read Pointer */
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uint8 tx_state; /* Transmitting state flags (HOLD, XMIT) */
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t_bool dma; /* DMA currently active */
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t_bool drq; /* DMA request enabled */
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t_bool rxr_full; /* Receive Shift Register is full */
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} IU_PORT;
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typedef struct iu_state {
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uint8 isr; /* Interrupt Status Register */
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uint8 imr; /* Interrupt Mask Register */
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uint8 acr; /* Aux. Control Register */
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uint8 opcr; /* Output Port Configuration */
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uint8 inprt; /* Input Port Data */
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uint8 ipcr; /* Input Port Change Register */
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} IU_STATE;
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typedef struct iu_timer_state {
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uint16 c_set;
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t_bool c_en;
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} IU_TIMER_STATE;
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/* Function prototypes */
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t_stat contty_attach(UNIT *uptr, CONST char *cptr);
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t_stat contty_detach(UNIT *uptr);
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t_stat tti_reset(DEVICE *dptr);
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t_stat contty_reset(DEVICE *dptr);
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t_stat iu_timer_reset(DEVICE *dptr);
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t_stat iu_timer_set_mult(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat iu_timer_show_mult(FILE *st, UNIT *uptr, int val, CONST void *desc);
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t_stat iu_svc_tti(UNIT *uptr);
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t_stat iu_svc_tto(UNIT *uptr);
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t_stat iu_svc_contty(UNIT *uptr);
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t_stat iu_svc_contty_xmt(UNIT *uptr);
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t_stat iu_svc_timer(UNIT *uptr);
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uint32 iu_read(uint32 pa, size_t size);
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void iu_write(uint32 pa, uint32 val, size_t size);
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void iua_drq_handled();
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void iub_drq_handled();
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void iu_txrdy_a_irq();
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void iu_txrdy_b_irq();
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void iu_dma_console(uint8 channel, uint32 service_address);
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void iu_dma_contty(uint8 channel, uint32 service_address);
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void increment_modep_a();
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void increment_modep_b();
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extern IU_PORT iu_console;
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extern IU_PORT iu_contty;
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extern t_bool iu_increment_a;
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extern t_bool iu_increment_b;
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#endif
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