470 lines
24 KiB
C
470 lines
24 KiB
C
/* pcbus.c: PC bus simulator
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Copyright (c) 2016, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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MODIFICATIONS:
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11 Jul 16 - Original file.
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NOTES:
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This software was written by Bill Beech, Jul 2016, to allow emulation of PC XT
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Computer Systems.
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*/
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#include "system_defs.h"
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int32 mbirq = 0; /* set no interrupts */
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/* function prototypes */
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t_stat xtbus_svc(UNIT *uptr);
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t_stat xtbus_reset(DEVICE *dptr);
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void set_irq(int32 int_num);
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void clr_irq(int32 int_num);
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uint8 nulldev(t_bool io, uint8 data, uint8 devnum);
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uint16 reg_dev(uint8 (*routine)(t_bool io, uint8 data, uint8 devnum), uint16 port, uint8 devnum);
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void dump_dev_table(void);
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t_stat xtbus_reset (DEVICE *dptr);
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uint8 xtbus_get_mbyte(uint32 addr);
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void xtbus_put_mbyte(uint32 addr, uint8 val);
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/* external function prototypes */
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extern uint8 RAM_get_mbyte(uint32 addr);
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extern void RAM_put_mbyte(uint32 addr, uint8 val);
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extern t_stat SBC_reset(DEVICE *dptr); /* reset the PC XT simulator */
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extern void set_cpuint(int32 int_num);
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/* external globals */
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extern int32 int_req; /* i8088 INT signal */
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extern uint16 port; //port called in dev_table[port]
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/* Standard SIMH Device Data Structures */
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UNIT xtbus_unit = {
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UDATA (&xtbus_svc, 0, 0), 20
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};
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REG xtbus_reg[] = {
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{ HRDATA (MBIRQ, mbirq, 32) },
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};
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DEBTAB xtbus_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "LEV1", DEBUG_level1 },
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{ "LEV2", DEBUG_level2 },
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{ NULL }
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};
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DEVICE xtbus_dev = {
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"PCBUS", //name
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&xtbus_unit, //units
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xtbus_reg, //registers
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NULL, //modifiers
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1, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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&xtbus_reset, //reset
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NULL, //boot
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NULL, //attach
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NULL, //detach
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NULL, //ctxt
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DEV_DEBUG, //flags
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0, //dctrl
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xtbus_debug, //debflags
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NULL, //msize
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NULL //lname
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};
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/* Service routines to handle simulator functions */
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/* service routine - actually does the simulated interrupts */
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t_stat xtbus_svc(UNIT *uptr)
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{
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switch (mbirq) {
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case INT_1:
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set_cpuint(INT_R);
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sim_printf("xtbus_svc: mbirq=%04X int_req=%04X\n", mbirq, int_req);
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break;
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default:
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//sim_printf("xtbus_svc: default mbirq=%04X\n", mbirq);
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break;
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}
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sim_activate (&xtbus_unit, xtbus_unit.wait); /* continue poll */
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat xtbus_reset(DEVICE *dptr)
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{
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SBC_reset(NULL);
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sim_printf(" Xtbus: Reset\n");
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sim_activate (&xtbus_unit, xtbus_unit.wait); /* activate unit */
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return SCPE_OK;
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}
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void set_irq(int32 int_num)
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{
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mbirq |= int_num;
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sim_printf("set_irq: int_num=%04X mbirq=%04X\n", int_num, mbirq);
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}
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void clr_irq(int32 int_num)
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{
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mbirq &= ~int_num;
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sim_printf("clr_irq: int_num=%04X mbirq=%04X\n", int_num, mbirq);
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}
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/* This is the I/O configuration table. There are 1024 possible
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device addresses, if a device is plugged to a port it's routine
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address is here, 'nulldev' means no device has been registered.
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The actual 808X can address 65,536 I/O ports but the IBM only uses
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the first 1024. */
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struct idev {
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uint8 (*routine)(t_bool io, uint8 data, uint8 devnum);
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uint8 port;
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uint8 devnum;
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};
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struct idev dev_table[1024] = {
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 000H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 004H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 008H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 00CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 010H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 014H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 018H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 01CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 020H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 024H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 028H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 02CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 030H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 034H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 038H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 03CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 040H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 044H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 048H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 04CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 050H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 054H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 058H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 05CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 060H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 064H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 068H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 06CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 070H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 074H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 078H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 07CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 080H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 084H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 088H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 08CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 090H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 094H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 098H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 09CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A0H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A4H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A8H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A0H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B0H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B4H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B8H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B0H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0C0H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0C4H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0C8H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0CCH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0D0H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0D4H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0D8H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0DCH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0E0H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0E4H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0E8H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0ECH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0F0H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0F4H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0F8H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0FCH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 100H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 104H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 108H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 10CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 110H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 114H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 118H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 11CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 120H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 124H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 128H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 12CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 130H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 134H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 138H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 13CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 140H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 144H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 148H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 14CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 150H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 154H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 158H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 15CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 160H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 164H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 168H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 16CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 170H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 174H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 178H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 17CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 180H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 184H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 188H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 18CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 190H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 194H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 198H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 19CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1A0H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1A4H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1A8H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1A0H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1B0H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1B4H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1B8H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1B0H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1C0H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1C4H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1C8H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1CCH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1D0H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1D4H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1D8H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1DCH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1E0H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1E4H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1E8H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1ECH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1F0H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1F4H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1F8H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1FCH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 200H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 204H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 208H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 20CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 210H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 214H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 218H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 21CH */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 220H */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 224H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 228H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 22CH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 230H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 234H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 238H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 23CH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 240H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 244H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 248H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 24CH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 250H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 254H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 258H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 25CH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 260H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 264H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 268H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 26CH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 270H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 274H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 278H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 27CH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 280H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 284H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 288H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 28CH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 290H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 294H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 298H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 29CH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2A0H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2A4H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2A8H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2A0H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2B0H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2B4H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2B8H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2B0H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2C0H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2C4H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2C8H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2CCH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2D0H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2D4H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2D8H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2DCH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2E0H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2E4H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2E8H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2ECH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2F0H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2F4H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2F8H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2FCH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 300H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 304H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 308H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 30CH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 310H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 314H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 318H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 31CH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 320H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 324H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 328H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 32CH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 330H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 334H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 338H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 33CH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 340H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 344H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 348H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 34CH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 350H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 354H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 358H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 35CH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 360H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 364H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 368H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 36CH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 370H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 374H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 378H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 37CH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 380H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 384H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 388H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 38CH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 390H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 394H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 398H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 39CH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3A0H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3A4H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3A8H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3A0H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3B0H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3B4H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3B8H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3B0H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3C0H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3C4H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3C8H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3CCH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3D0H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3D4H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3D8H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3DCH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3E0H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3E4H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3E8H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3ECH */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3F0H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3F4H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3F8H */
|
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev} /* 3FCH */
|
|
};
|
|
|
|
uint8 nulldev(t_bool io, uint8 data, uint8 devnum)
|
|
{
|
|
sim_printf("xtbus: I/O Port %03X is not assigned io=%d data=%02X\n",
|
|
port, io, data);
|
|
if (io == 0) /* if we got here, no valid I/O device */
|
|
return 0xFF;
|
|
return 0;
|
|
}
|
|
|
|
uint16 reg_dev(uint8 (*routine)(t_bool io, uint8 data, uint8 devnum), uint16 port, uint8 devnum)
|
|
{
|
|
if (dev_table[port].routine != &nulldev) { /* port already assigned */
|
|
sim_printf("xtbus: I/O Port %03X is already assigned\n", port);
|
|
} else {
|
|
sim_printf("Port %03X is assigned\n", port);
|
|
dev_table[port].routine = routine;
|
|
}
|
|
//dump_dev_table();
|
|
return port;
|
|
}
|
|
|
|
void dump_dev_table(void)
|
|
{
|
|
int i;
|
|
|
|
for (i=0; i<1024; i++) {
|
|
if (dev_table[i].routine != &nulldev) { /* assigned port */
|
|
sim_printf("Port %03X is assigned\n", i);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* get a byte from bus */
|
|
|
|
uint8 xtbus_get_mbyte(uint32 addr)
|
|
{
|
|
return RAM_get_mbyte(addr);
|
|
}
|
|
|
|
/* put a byte to bus */
|
|
|
|
void xtbus_put_mbyte(uint32 addr, uint8 val)
|
|
{
|
|
RAM_put_mbyte(addr, val);
|
|
}
|
|
|
|
/* end of pcbus.c */
|
|
|