756 lines
22 KiB
C
756 lines
22 KiB
C
/* 3b2_iu.c: SCN2681A Dual UART Implementation
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Copyright (c) 2017, Seth J. Morabito
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Permission is hereby granted, free of charge, to any person
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obtaining a copy of this software and associated documentation
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files (the "Software"), to deal in the Software without
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restriction, including without limitation the rights to use, copy,
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modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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Except as contained in this notice, the name of the author shall
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not be used in advertising or otherwise to promote the sale, use or
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other dealings in this Software without prior written authorization
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from the author.
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*/
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#include "3b2_iu.h"
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/*
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* The 3B2/400 has two on-board serial ports, labeled CONSOLE and
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* CONTTY. The CONSOLE port is (naturally) the system console. The
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* CONTTY port serves as a secondary serial port for an additional
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* terminal.
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*
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* These lines are driven by an SCN2681A Dual UART, with two receivers
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* and two transmitters.
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*
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* In addition to the two TX/RX ports, the SCN27681A also has one
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* programmable timer.
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*
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* The SCN2681A UART is represented here by five devices:
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*
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* - Console TTI (Input, port A)
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* - Console TTO (Output, port A)
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* - Contty TTI (Input, port B)
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* - Contty TTO (Output, port B)
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* - IU Timer
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*/
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/*
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* Registers
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*/
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/* The IU state shared between A and B */
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IU_STATE iu_state;
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/* The tx/rx state for ports A and B */
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IU_PORT iu_port_a;
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IU_PORT iu_port_b;
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/* The timer state */
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IU_TIMER_STATE iu_timer_state;
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/* Flags for incrementing mode pointers */
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t_bool iu_increment_a = FALSE;
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t_bool iu_increment_b = FALSE;
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extern uint16 csr_data;
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BITFIELD sr_bits[] = {
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BIT(RXRDY),
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BIT(FFULL),
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BIT(TXRDY),
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BIT(TXEMT),
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BIT(OVRN_E),
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BIT(PRTY_E),
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BIT(FRM_E),
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BIT(BRK),
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ENDBITS
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};
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BITFIELD isr_bits[] = {
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BIT(TXRDYA),
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BIT(RXRDY_FFA),
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BIT(DLTA_BRKA),
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BIT(CTR_RDY),
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BIT(TXRDYB),
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BIT(RXRDY_FFB),
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BIT(DLTA_BRKB),
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BIT(IPC),
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ENDBITS
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};
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BITFIELD acr_bits[] = {
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BIT(BRG_SET),
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BITFFMT(TMR_MODE,3,%d),
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BIT(DLTA_IP3),
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BIT(DLTA_IP2),
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BIT(DLTA_IP1),
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BIT(DLTA_IP0),
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ENDBITS
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};
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BITFIELD conf_bits[] = {
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BIT(TX_EN),
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BIT(RX_EN),
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ENDBITS
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};
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/* TTI (Port A) data structures */
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REG tti_a_reg[] = {
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{ HRDATADF(STAT, iu_port_a.stat, 8, "Status", sr_bits) },
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{ HRDATADF(CONF, iu_port_a.conf, 8, "Config", conf_bits) },
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{ BRDATAD(DATA, iu_port_a.rxbuf, 16, 8, IU_BUF_SIZE, "Data") },
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{ NULL }
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};
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UNIT tti_a_unit = { UDATA(&iu_svc_tti_a, UNIT_IDLE, 0), TMLN_SPD_9600_BPS };
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DEVICE tti_a_dev = {
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"TTIA", &tti_a_unit, tti_a_reg, NULL,
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1, 8, 32, 1, 8, 8,
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NULL, NULL, &tti_a_reset,
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NULL, NULL, NULL, NULL,
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DEV_DEBUG, 0, sys_deb_tab
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};
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/* TTO (Port A) data structures */
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REG tto_a_reg[] = {
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{ HRDATADF(STAT, iu_port_a.stat, 8, "Status", sr_bits) },
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{ HRDATADF(ISTAT, iu_state.istat, 8, "Interrupt Status", isr_bits) },
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{ HRDATAD(IMR, iu_state.imr, 8, "Interrupt Mask") },
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{ HRDATADF(ACR, iu_state.acr, 8, "Auxiliary Control Register", acr_bits) },
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{ HRDATAD(DATA, iu_port_a.txbuf, 8, "Data") },
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{ NULL }
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};
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UNIT tto_a_unit = { UDATA(&iu_svc_tto_a, TT_MODE_8B, 0), SERIAL_OUT_WAIT };
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DEVICE tto_a_dev = {
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"TTOA", &tto_a_unit, tto_a_reg, NULL,
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1, 8, 32, 1, 8, 8,
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NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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DEV_DEBUG, 0, sys_deb_tab
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};
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/* TTI (Port B) data structures */
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REG tti_b_reg[] = {
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{ HRDATADF(STAT, iu_port_b.stat, 8, "Status", sr_bits) },
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{ HRDATADF(CONF, iu_port_b.conf, 8, "Config", conf_bits) },
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{ BRDATAD(DATA, iu_port_b.rxbuf, 16, 8, IU_BUF_SIZE, "Data") },
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{ NULL }
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};
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UNIT tti_b_unit = { UDATA(&iu_svc_tti_b, UNIT_IDLE, 0), TMLN_SPD_9600_BPS };
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DEVICE tti_b_dev = {
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"TTIB", &tti_b_unit, tti_b_reg, NULL,
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1, 8, 32, 1, 8, 8,
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NULL, NULL, &tti_b_reset,
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NULL, NULL, NULL, NULL,
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DEV_DEBUG, 0, sys_deb_tab
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};
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/* TTO (Port B) data structures */
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REG tto_b_reg[] = {
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{ HRDATADF(STAT, iu_port_b.stat, 8, "Status", sr_bits) },
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{ HRDATADF(ISTAT, iu_state.istat, 8, "Interrupt Status", isr_bits) },
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{ HRDATAD(IMR, iu_state.imr, 8, "Interrupt Mask") },
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{ HRDATADF(ACR, iu_state.acr, 8, "Auxiliary Control Register", acr_bits) },
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{ HRDATAD(DATA, iu_port_b.txbuf, 8, "Data") },
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{ NULL }
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};
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UNIT tto_b_unit = { UDATA(&iu_svc_tto_b, TT_MODE_8B, 0), SERIAL_OUT_WAIT };
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DEVICE tto_b_dev = {
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"TTOB", &tto_b_unit, tto_b_reg, NULL,
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1, 8, 32, 1, 8, 8,
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NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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DEV_DEBUG, 0, sys_deb_tab
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};
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/* IU Timer data structures */
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REG iu_timer_reg[] = {
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{ HRDATAD(CTR_SET, iu_timer_state.c_set, 16, "Counter Setting") },
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{ NULL }
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};
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UNIT iu_timer_unit = { UDATA(&iu_svc_timer, 0, 0) };
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DEVICE iu_timer_dev = {
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"IUTIMER", &iu_timer_unit, iu_timer_reg, NULL,
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1, 8, 32, 1, 8, 8,
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NULL, NULL, &iu_timer_reset,
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NULL, NULL, NULL, NULL,
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DEV_DEBUG, 0, sys_deb_tab
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};
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void increment_modep_a()
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{
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iu_increment_a = FALSE;
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iu_port_a.modep++;
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if (iu_port_a.modep > 1) {
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iu_port_a.modep = 0;
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}
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}
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void increment_modep_b()
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{
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iu_increment_b = FALSE;
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iu_port_b.modep++;
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if (iu_port_b.modep > 1) {
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iu_port_b.modep = 0;
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}
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}
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void iu_txrdy_a_irq() {
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if ((iu_state.imr & ISTS_TAI) &&
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(iu_port_a.conf & TX_EN) &&
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(iu_port_a.stat & STS_TXR)) {
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sim_debug(EXECUTE_MSG, &tto_a_dev,
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"Firing IU TTY IRQ 13 ON TX/State Change: PORT A\n");
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csr_data |= CSRUART;
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}
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}
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void iu_txrdy_b_irq() {
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if ((iu_state.imr & ISTS_TBI) &&
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(iu_port_b.conf & TX_EN) &&
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(iu_port_b.stat & STS_TXR)) {
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sim_debug(EXECUTE_MSG, &tto_b_dev,
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"Firing IU TTY IRQ 13 ON TX/State Change: PORT B\n");
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csr_data |= CSRUART;
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}
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}
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t_stat tti_a_reset(DEVICE *dptr)
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{
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memset(&iu_state, 0, sizeof(IU_STATE));
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memset(&iu_port_a, 0, sizeof(IU_PORT));
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/* Start the TTI A polling loop */
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if (!sim_is_active(&tti_a_unit)) {
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sim_activate(&tti_a_unit, tti_a_unit.wait);
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}
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return SCPE_OK;
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}
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t_stat tti_b_reset(DEVICE *dtpr)
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{
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memset(&iu_state, 0, sizeof(IU_STATE));
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memset(&iu_port_b, 0, sizeof(IU_PORT));
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/* Start the TTI B polling loop */
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if (!sim_is_active(&tti_b_unit)) {
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sim_activate(&tti_b_unit, tti_b_unit.wait);
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}
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return SCPE_OK;
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}
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t_stat iu_timer_reset(DEVICE *dptr)
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{
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memset(&iu_timer_state, 0, sizeof(IU_TIMER_STATE));
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return SCPE_OK;
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}
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/* Service routines */
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t_stat iu_svc_tti_a(UNIT *uptr)
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{
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int32 temp;
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sim_clock_coschedule_tmr_abs(uptr, TMR_CLK, 2);
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/* TODO:
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- If there has been a change on IP0-IP3, set the corresponding
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bits in IPCR, if configured to do so. We'll need to figure out
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how these are wired (DCD pin, etc?)
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- Update the Output Port pins (which are logically inverted)
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based on the contents of the OPR, OPCR, MR, and CR registers.
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*/
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if ((temp = sim_poll_kbd()) < SCPE_KFLAG) {
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return temp;
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}
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sim_debug(READ_MSG, &tti_a_dev,
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">>> TTIA: Receive %02x (%c)\n",
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temp & 0xff, temp & 0xff);
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if (iu_port_a.conf & RX_EN) {
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if ((iu_port_a.stat & STS_FFL) == 0) {
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iu_port_a.rxbuf[iu_port_a.w_p] = (temp & 0xff);
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iu_port_a.w_p = (iu_port_a.w_p + 1) % IU_BUF_SIZE;
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if (iu_port_a.w_p == iu_port_b.w_p) {
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sim_debug(READ_MSG, &tti_a_dev,
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">>> FIFO FULL ON KEYBOARD READ!!!! <<<\n");
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iu_port_a.stat |= STS_FFL;
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}
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}
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iu_port_a.stat |= STS_RXR;
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iu_state.istat |= ISTS_RAI;
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if (iu_state.imr & 0x02) {
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sim_debug(EXECUTE_MSG, &tti_a_dev,
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"Firing IRQ 13 ON TTI A RECEIVE (%c)\n",
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(temp & 0xff));
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csr_data |= CSRUART;
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}
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}
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return SCPE_OK;
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}
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t_stat iu_svc_tti_b(UNIT *uptr)
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{
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sim_clock_coschedule_tmr_abs(uptr, TMR_CLK, 2);
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/* TODO: Handle TTIB as a terminal */
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return SCPE_OK;
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}
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t_stat iu_svc_tto_a(UNIT *uptr)
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{
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iu_txrdy_a_irq();
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return SCPE_OK;
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}
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t_stat iu_svc_tto_b(UNIT *uptr)
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{
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iu_txrdy_b_irq();
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return SCPE_OK;
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}
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t_stat iu_svc_timer(UNIT *uptr)
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{
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iu_state.istat |= ISTS_CRI;
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if (iu_state.imr & 0x08) {
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csr_data |= CSRUART;
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}
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return SCPE_OK;
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}
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/*
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* Reg | Name (Read) | Name (Write)
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* -----+-------------------------+----------------------------
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* 0 | Mode Register 1/2 A | Mode Register 1/2 A
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* 1 | Status Register A | Clock Select Register A
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* 2 | BRG Test | Command Register A
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* 3 | Rx Holding Register A | Tx Holding Register A
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* 4 | Input Port Change Reg. | Aux. Control Register
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* 5 | Interrupt Status Reg. | Interrupt Mask Register
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* 6 | Counter/Timer Upper Val | C/T Upper Preset Val.
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* 7 | Counter/Timer Lower Val | C/T Lower Preset Val.
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* 8 | Mode Register B | Mode Register B
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* 9 | Status Register B | Clock Select Register B
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* 10 | 1X/16X Test | Command Register B
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* 11 | Rx Holding Register B | Tx Holding Register B
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* 12 | *Reserved* | *Reserved*
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* 13 | Input Ports IP0 to IP6 | Output Port Conf. Reg.
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* 14 | Start Counter Command | Set Output Port Bits Cmd.
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* 15 | Stop Counter Command | Reset Output Port Bits Cmd.
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*/
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uint32 iu_read(uint32 pa, size_t size)
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{
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uint8 reg, modep;
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uint32 data, delay;
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reg = (uint8) (pa - IUBASE);
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switch (reg) {
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case MR12A:
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modep = iu_port_a.modep;
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data = iu_port_a.mode[modep];
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iu_increment_a = TRUE;
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break;
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case SRA:
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data = iu_port_a.stat;
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break;
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case RHRA:
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data = iu_port_a.rxbuf[iu_port_a.r_p];
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iu_port_a.r_p = (iu_port_a.r_p + 1) % IU_BUF_SIZE;
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sim_debug(READ_MSG, &tti_a_dev,
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"[%08x] RHRA = %02x (%c)\n",
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R[NUM_PC], (data & 0xff), (data & 0xff));
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iu_port_a.stat &= ~(STS_RXR|STS_FFL);
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iu_state.istat &= ~ISTS_RAI;
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csr_data &= ~CSRUART;
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break;
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case IPCR:
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data = iu_state.ipcr;
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/* Reading the port resets the upper four bits */
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iu_state.ipcr &= 0x0f;
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csr_data &= ~CSRUART;
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break;
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case ISR:
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data = iu_state.istat;
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break;
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case CTU:
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data = (iu_timer_state.c_set >> 8) & 0xff;
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break;
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case CTL:
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data = iu_timer_state.c_set & 0xff;
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break;
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case MR12B:
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modep = iu_port_b.modep;
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data = iu_port_b.mode[modep];
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iu_increment_b = TRUE;
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break;
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case SRB:
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data = iu_port_b.stat;
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sim_debug(READ_MSG, &tti_b_dev,
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"[%08x] SRB = %02x\n",
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R[NUM_PC], (data & 0xff));
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break;
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case RHRB:
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data = iu_port_b.rxbuf[iu_port_b.r_p];
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iu_port_b.r_p = (iu_port_b.r_p + 1) % IU_BUF_SIZE;
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sim_debug(READ_MSG, &tti_b_dev,
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"[%08x] RHRB = %02x (%c)\n",
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R[NUM_PC], (data & 0xff), (data & 0xff));
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iu_port_b.stat &= ~(STS_RXR|STS_FFL);
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iu_state.istat &= ~ISTS_RBI;
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break;
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case INPRT:
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/* TODO: Correct behavior for DCD on contty */
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/* For now, this enables DCD/DTR on console only */
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data = 0x8e;
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break;
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case START_CTR:
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data = 0;
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iu_state.istat &= ~ISTS_CRI;
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delay = (uint32) (IU_TIMER_STP * iu_timer_state.c_set);
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sim_activate_abs(&iu_timer_unit, (int32) DELAY_US(delay));
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sim_debug(READ_MSG, &iu_timer_dev,
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"[%08x] Activating IU timer to fire in %04x steps\n",
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R[NUM_PC], iu_timer_state.c_set);
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break;
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case STOP_CTR:
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data = 0;
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iu_state.istat &= ~ISTS_CRI;
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csr_data &= ~CSRUART;
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sim_cancel(&iu_timer_unit);
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sim_debug(READ_MSG, &iu_timer_dev,
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"[%08x] Cancelling IU timer\n",
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R[NUM_PC]);
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break;
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case 17: /* Clear DMAC interrupt */
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data = 0;
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iu_port_a.drq = FALSE;
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iu_port_b.drq = FALSE;
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csr_data &= ~CSRDMA;
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break;
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default:
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data = 0;
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break;
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}
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return data;
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}
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void iu_write(uint32 pa, uint32 val, size_t size)
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{
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uint8 reg;
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uint8 modep;
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reg = (uint8) (pa - IUBASE);
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switch (reg) {
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case MR12A:
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modep = iu_port_a.modep;
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iu_port_a.mode[modep] = val & 0xff;
|
|
iu_increment_a = TRUE;
|
|
break;
|
|
case CSRA:
|
|
/* Set baud rate - not implemented */
|
|
break;
|
|
case CRA: /* Command A */
|
|
sim_debug(WRITE_MSG, &tti_a_dev,
|
|
"[%08x] CRA = %02x\n",
|
|
R[NUM_PC], (val & 0xff));
|
|
iu_w_cmd(PORT_A, (uint8) val);
|
|
break;
|
|
case THRA: /* TX/RX Buf A */
|
|
sim_debug(WRITE_MSG, &tto_a_dev,
|
|
"[%08x] THRA = %02x (%c)\n",
|
|
R[NUM_PC], (val & 0xff), (val & 0xff));
|
|
/* Loopback mode */
|
|
if ((iu_port_a.mode[1] & 0xc0) == 0x80) {
|
|
iu_port_a.txbuf = (uint8) val;
|
|
|
|
/* This is also a Receive */
|
|
if ((iu_port_a.stat & STS_FFL) == 0) {
|
|
iu_port_a.rxbuf[iu_port_a.w_p] = (uint8) val;
|
|
iu_port_a.w_p = (iu_port_a.w_p + 1) % IU_BUF_SIZE;
|
|
if (iu_port_a.w_p == iu_port_b.r_p) {
|
|
sim_debug(WRITE_MSG, &tto_a_dev,
|
|
">>> FIFO FULL ON LOOPBACK THRA! <<<");
|
|
iu_port_a.stat |= STS_FFL;
|
|
}
|
|
}
|
|
|
|
iu_port_a.stat |= STS_RXR;
|
|
iu_state.istat |= ISTS_RAI;
|
|
} else {
|
|
iu_tx(PORT_A, (uint8) val);
|
|
}
|
|
csr_data &= ~CSRUART;
|
|
break;
|
|
case ACR: /* Auxiliary Control Register */
|
|
iu_state.acr = (uint8) val;
|
|
break;
|
|
case IMR:
|
|
sim_debug(WRITE_MSG, &tti_a_dev,
|
|
"[%08x] IMR = %02x\n",
|
|
R[NUM_PC], (val & 0xff));
|
|
iu_state.imr = (uint8) val;
|
|
csr_data &= ~CSRUART;
|
|
/* Possibly cause an interrupt */
|
|
iu_txrdy_a_irq();
|
|
iu_txrdy_b_irq();
|
|
break;
|
|
case CTUR: /* Counter/Timer Upper Preset Value */
|
|
/* Clear out high byte */
|
|
iu_timer_state.c_set &= 0x00ff;
|
|
/* Set high byte */
|
|
iu_timer_state.c_set |= (val & 0xff) << 8;
|
|
break;
|
|
case CTLR: /* Counter/Timer Lower Preset Value */
|
|
/* Clear out low byte */
|
|
iu_timer_state.c_set &= 0xff00;
|
|
/* Set low byte */
|
|
iu_timer_state.c_set |= (val & 0xff);
|
|
break;
|
|
case MR12B:
|
|
modep = iu_port_b.modep;
|
|
iu_port_b.mode[modep] = val & 0xff;
|
|
iu_increment_b = TRUE;
|
|
break;
|
|
case CRB: /* Command B */
|
|
sim_debug(WRITE_MSG, &tti_b_dev,
|
|
"[%08x] CRB = %02x\n",
|
|
R[NUM_PC], (val & 0xff));
|
|
iu_w_cmd(PORT_B, (uint8) val);
|
|
break;
|
|
case CSRB:
|
|
break;
|
|
case THRB: /* TX/RX Buf B */
|
|
sim_debug(WRITE_MSG, &tto_b_dev,
|
|
"[%08x] THRB = %02x (%c)\n",
|
|
R[NUM_PC], (val & 0xff), (val & 0xff));
|
|
/* Loopback mode */
|
|
if ((iu_port_b.mode[1] & 0xc0) == 0x80) {
|
|
iu_port_a.txbuf = (uint8) val;
|
|
|
|
/* This is also a Receive */
|
|
if ((iu_port_b.stat & STS_FFL) == 0) {
|
|
iu_port_b.rxbuf[iu_port_b.w_p] = (uint8) val;
|
|
iu_port_b.w_p = (iu_port_b.w_p + 1) % IU_BUF_SIZE;
|
|
if (iu_port_b.w_p == iu_port_b.r_p) {
|
|
sim_debug(WRITE_MSG, &tto_b_dev,
|
|
">>> FIFO FULL ON LOOPBACK THRB! <<<");
|
|
iu_port_b.stat |= STS_FFL;
|
|
}
|
|
}
|
|
|
|
iu_port_b.stat |= STS_RXR;
|
|
iu_state.istat |= ISTS_RBI;
|
|
} else {
|
|
iu_tx(PORT_B, (uint8) val);
|
|
}
|
|
break;
|
|
case OPCR:
|
|
iu_state.opcr = (uint8) val;
|
|
break;
|
|
case SOPR:
|
|
break;
|
|
case ROPR:
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
void iua_drq_handled()
|
|
{
|
|
sim_debug(EXECUTE_MSG, &tto_a_dev,
|
|
"Firing IU IRQ 13 on DRQ (A) Hanlded\n");
|
|
csr_data |= CSRDMA;
|
|
}
|
|
|
|
void iub_drq_handled()
|
|
{
|
|
sim_debug(EXECUTE_MSG, &tto_a_dev,
|
|
"Firing IU IRQ 13 on DRQ (B) Hanlded\n");
|
|
csr_data |= CSRDMA;
|
|
}
|
|
|
|
static SIM_INLINE void iu_tx(uint8 portno, uint8 val)
|
|
{
|
|
IU_PORT *p;
|
|
UNIT *uptr;
|
|
|
|
if (portno == 0) {
|
|
p = &iu_port_a;
|
|
uptr = &tto_a_unit;
|
|
} else {
|
|
p = &iu_port_b;
|
|
uptr = &tto_b_unit;
|
|
}
|
|
|
|
p->txbuf = val;
|
|
|
|
if (p->conf & TX_EN) {
|
|
p->stat &= ~(STS_TXR|STS_TXE);
|
|
iu_state.istat &= ~(1 << (portno*4));
|
|
|
|
if (portno == PORT_A) {
|
|
/* Write the character to the SIMH console */
|
|
sim_putchar(val);
|
|
}
|
|
|
|
/* The buffer is now empty, we've transmitted, so set TXR */
|
|
p->stat |= STS_TXR;
|
|
iu_state.istat |= (1 << (portno*4));
|
|
|
|
/* Possibly cause an interrupt */
|
|
sim_activate_abs(uptr, uptr->wait);
|
|
}
|
|
}
|
|
|
|
static SIM_INLINE void iu_w_cmd(uint8 portno, uint8 cmd)
|
|
{
|
|
|
|
IU_PORT *p;
|
|
|
|
if (portno == 0) {
|
|
p = &iu_port_a;
|
|
} else {
|
|
p = &iu_port_b;
|
|
}
|
|
|
|
/* Enable or disable transmitter */
|
|
/* Disable always wins, if both are set */
|
|
if (cmd & CMD_DTX) {
|
|
p->conf &= ~TX_EN;
|
|
p->stat &= ~STS_TXR;
|
|
p->stat &= ~STS_TXE;
|
|
p->drq = FALSE;
|
|
} else if (cmd & CMD_ETX) {
|
|
p->conf |= TX_EN;
|
|
/* TXE and TXR are always set by an ENABLE */
|
|
p->stat |= STS_TXR;
|
|
p->stat |= STS_TXE;
|
|
p->drq = TRUE;
|
|
iu_state.istat |= 1 << (portno*4);
|
|
if (portno == 0) {
|
|
iu_txrdy_a_irq();
|
|
} else {
|
|
iu_txrdy_b_irq();
|
|
}
|
|
}
|
|
|
|
/* Enable or disable receiver. */
|
|
/* Disable always wins, if both are set */
|
|
if (cmd & CMD_DRX) {
|
|
p->conf &= ~RX_EN;
|
|
p->stat &= ~STS_RXR;
|
|
} else if (cmd & CMD_ERX) {
|
|
p->conf |= RX_EN;
|
|
}
|
|
|
|
/* Command register bits 6-4 have special meaning */
|
|
switch ((cmd >> CMD_MISC_SHIFT) & CMD_MISC_MASK) {
|
|
case 1:
|
|
/* Causes the Channel A MR pointer to point to MR1. */
|
|
p->modep = 0;
|
|
break;
|
|
case 2:
|
|
/* Reset receiver. Resets the Channel's receiver as if a
|
|
hardware reset had been applied. The receiver is disabled
|
|
and the FIFO is flushed. */
|
|
p->stat &= ~STS_RXR;
|
|
p->conf &= ~RX_EN;
|
|
p->w_p = 0;
|
|
p->r_p = 0;
|
|
break;
|
|
case 3:
|
|
/* Reset transmitter. Resets the Channel's transmitter as if a
|
|
hardware reset had been applied. */
|
|
p->stat &= ~STS_TXR;
|
|
p->stat &= ~STS_TXE;
|
|
p->conf &= ~TX_EN;
|
|
p->w_p = 0;
|
|
p->r_p = 0;
|
|
break;
|
|
case 4:
|
|
/* Reset error status. Clears the Channel's Received Break,
|
|
Parity Error, and Overrun Error bits in the status register
|
|
(SRA[7:4]). Used in character mode to clear OE status
|
|
(although RB, PE and FE bits will also be cleared) and in
|
|
block mode to clear all error status after a block of data
|
|
has been received. */
|
|
p->stat &= ~(STS_FER|STS_PER|STS_OER);
|
|
break;
|
|
case 5:
|
|
/* Reset Channel's break change interrupt. Causes the Channel
|
|
A break detect change bit in the interrupt status register
|
|
(ISR[2] for Chan. A, ISR[6] for Chan. B) to be cleared to
|
|
zero. */
|
|
iu_state.istat &= ~(1 << (2 + portno*4));
|
|
break;
|
|
case 6:
|
|
/* Start break. Forces the TxDA output LOW (spacing). If the
|
|
transmitter is empty the start of the break condition will
|
|
be delayed up to two bit times. If the transmitter is
|
|
active the break begins when transmission of the character
|
|
is completed. If a character is in the THR, the start of
|
|
the break will be delayed until that character, or any
|
|
other loaded subsequently are transmitted. The transmitter
|
|
must be enabled for this command to be accepted. */
|
|
/* Not Implemented */
|
|
break;
|
|
case 7:
|
|
/* Stop break. The TxDA line will go HIGH (marking) within two
|
|
bit times. TxDA will remain HIGH for one bit time before
|
|
the next character, if any, is transmitted. */
|
|
/* Not Implemented */
|
|
break;
|
|
}
|
|
}
|