26aa6de663
RESTRICTION: The PDP-15 FPP is only partially debugged. Do NOT enable this feature for normal operations. WARNING: The core simulator files (scp.c, sim_*.c) have been reorganized. Unzip V3.2-0 to an empty directory before attempting to compile the source. IMPORTANT: If you are compiling for UNIX, please read the notes for Ethernet very carefully. You may need to download a new version of the pcap library, or make changes to the makefile, to get Ethernet support to work. 1. New Features in 3.2-0 1.1 SCP and libraries - Added SHOW <device> RADIX command. - Added SHOW <device> MODIFIERS command. - Added SHOW <device> NAMES command. - Added SET/SHOW <device> DEBUG command. - Added sim_vm_parse_addr and sim_vm_fprint_addr optional interfaces. - Added REG_VMAD flag. - Split SCP into separate libraries for easier modification. - Added more room to the device and unit flag fields. - Changed terminal multiplexor library to support unlimited. number of async lines. 1.2 All DECtapes - Added STOP_EOR flag to enable end-of-reel error stop - Added device debug support. 1.3 Nova and Eclipse - Added QTY and ALM multiplexors (Bruce Ray). 1.4 LGP-30 - Added LGP-30/LGP-21 simulator. 1.5 PDP-11 - Added format, address increment inhibit, transfer overrun detection to RK. - Added device debug support to HK, RP, TM, TQ, TS. - Added DEUNA/DELUA (XU) support (Dave Hittner). - Add DZ per-line logging. 1.6 18b PDP's - Added support for 1-4 (PDP-9)/1-16 (PDP-15) additional terminals. 1.7 PDP-10 - Added DEUNA/DELUA (XU) support (Dave Hittner). 1.8 VAX - Added extended memory to 512MB (Mark Pizzolato). - Added RXV21 support. 2. Bugs Fixed in 3.2-0 2.1 SCP - Fixed double logging of SHOW BREAK (found by Mark Pizzolato). - Fixed implementation of REG_VMIO. 2.2 Nova and Eclipse - Fixed device enable/disable support (found by Bruce Ray). 2.3 PDP-1 - Fixed bug in LOAD (found by Mark Crispin). 2.4 PDP-10 - Fixed bug in floating point unpack. - Fixed bug in FIXR (found by Phil Stone, fixed by Chris Smith). 2.6 PDP-11 - Fixed bug in RQ interrupt control (found by Tom Evans). 2.6 PDP-18B - Fixed bug in PDP-15 XVM g_mode implementation. - Fixed bug in PDP-15 indexed address calculation. - Fixed bug in PDP-15 autoindexed address calculation. - Fixed bugs in FPP-15 instruction decode. - Fixed clock response to CAF. - Fixed bug in hardware read-in mode bootstrap. - Fixed PDP-15 XVM instruction decoding errors. 2.7 VAX - Fixed PC read fault in EXTxV. - Fixed PC write fault in INSV.
582 lines
19 KiB
C
582 lines
19 KiB
C
/* pdp11_defs.h: PDP-11 simulator definitions
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Copyright (c) 1993-2004, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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The author gratefully acknowledges the help of Max Burnet, Megan Gentry,
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and John Wilson in resolving questions about the PDP-11
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25-Jan-04 RMS Removed local debug logging support
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22-Dec-03 RMS Added second DEUNA/DELUA support
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18-Oct-03 RMS Added DECtape off reel message
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19-May-03 RMS Revised for new conditional compilation
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05-Apr-03 RMS Fixed bug in MMR1 update (found by Tim Stark)
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28-Feb-03 RMS Added TM logging support
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19-Jan-03 RMS Changed mode definitions for Apple Dev Kit conflict
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11-Nov-02 RMS Changed log definitions to be VAX compatible
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10-Oct-02 RMS Added vector information to DIB
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Changed DZ11 vector to Unibus standard
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Added DEQNA/DELQA, DEUNA/DELUA support
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Added multiple RQDX3, autoconfigure support
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12-Sep-02 RMS Added TMSCP, KW11P,and RX211 support
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28-Apr-02 RMS Clarified PDF ACF mnemonics
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22-Apr-02 RMS Added HTRAP, BPOK maint register flags, MT_MAXFR
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06-Mar-02 RMS Changed system type to KDJ11A
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20-Jan-02 RMS Added multiboard DZ11 support
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09-Nov-01 RMS Added bus map support
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07-Nov-01 RMS Added RQDX3 support
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26-Oct-01 RMS Added symbolic definitions for IO page
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19-Oct-01 RMS Added DZ definitions
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15-Oct-01 RMS Added logging capabilities
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07-Sep-01 RMS Revised for multilevel interrupts
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01-Jun-01 RMS Added DZ11 support
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23-Apr-01 RMS Added RK611 support
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05-Apr-01 RMS Added TS11/TSV05 support
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10-Feb-01 RMS Added DECtape support
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*/
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#ifndef _PDP11_DEFS_H
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#define _PDP11_DEFS_H 0
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#ifndef VM_PDP11
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#define VM_PDP11 0
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#endif
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#include "sim_defs.h" /* simulator defns */
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#include <setjmp.h>
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/* Architectural constants */
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#define STKLIM 0400 /* stack limit */
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#define VASIZE 0200000 /* 2**16 */
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#define VAMASK (VASIZE - 1) /* 2**16 - 1 */
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#define INIMEMSIZE 001000000 /* 2**18 */
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#define UNIMEMSIZE 001000000 /* 2**18 */
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#define UNIMASK (UNIMEMSIZE - 1) /* 2**18 - 1 */
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#define IOPAGEBASE 017760000 /* 2**22 - 2**13 */
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#define MAXMEMSIZE 020000000 /* 2**22 */
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#define PAMASK (MAXMEMSIZE - 1) /* 2**22 - 1 */
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#define MEMSIZE (cpu_unit.capac)
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#define ADDR_IS_MEM(x) (((t_addr) (x)) < MEMSIZE)
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#define DMASK 0177777
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/* Protection modes */
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#define MD_KER 0
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#define MD_SUP 1
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#define MD_UND 2
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#define MD_USR 3
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/* I/O access modes */
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#define READ 0
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#define READC 1 /* read console */
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#define WRITE 2
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#define WRITEC 3 /* write console */
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#define WRITEB 4
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/* PSW */
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#define PSW_V_C 0 /* condition codes */
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#define PSW_V_V 1
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#define PSW_V_Z 2
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#define PSW_V_N 3
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#define PSW_V_TBIT 4 /* trace trap */
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#define PSW_V_IPL 5 /* int priority */
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#define PSW_V_RS 11 /* register set */
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#define PSW_V_PM 12 /* previous mode */
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#define PSW_V_CM 14 /* current mode */
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#define PSW_RW 0174357 /* read/write bits */
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/* FPS */
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#define FPS_V_C 0 /* condition codes */
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#define FPS_V_V 1
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#define FPS_V_Z 2
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#define FPS_V_N 3
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#define FPS_V_T 5 /* truncate */
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#define FPS_V_L 6 /* long */
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#define FPS_V_D 7 /* double */
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#define FPS_V_IC 8 /* ic err int */
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#define FPS_V_IV 9 /* overflo err int */
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#define FPS_V_IU 10 /* underflo err int */
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#define FPS_V_IUV 11 /* undef var err int */
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#define FPS_V_ID 14 /* int disable */
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#define FPS_V_ER 15 /* error */
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/* PIRQ */
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#define PIRQ_PIR1 0001000
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#define PIRQ_PIR2 0002000
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#define PIRQ_PIR3 0004000
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#define PIRQ_PIR4 0010000
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#define PIRQ_PIR5 0020000
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#define PIRQ_PIR6 0040000
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#define PIRQ_PIR7 0100000
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#define PIRQ_IMP 0177356 /* implemented bits */
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#define PIRQ_RW 0177000 /* read/write bits */
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/* MMR0 */
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#define MMR0_MME 0000001 /* mem mgt enable */
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#define MMR0_V_PAGE 1 /* offset to pageno */
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#define MMR0_M_PAGE 077 /* mask for pageno */
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#define MMR0_PAGE (MMR0_M_PAGE << MMR0_V_PAGE)
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#define MMR0_RO 0020000 /* read only error */
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#define MMR0_PL 0040000 /* page lnt error */
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#define MMR0_NR 0100000 /* no access error */
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#define MMR0_FREEZE 0160000 /* if set, no update */
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#define MMR0_IMP 0160177 /* implemented bits */
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#define MMR0_RW 0160001 /* read/write bits */
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/* MMR3 */
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#define MMR3_UDS 001 /* user dspace enbl */
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#define MMR3_SDS 002 /* super dspace enbl */
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#define MMR3_KDS 004 /* krnl dspace enbl */
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#define MMR3_CSM 010 /* CSM enable */
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#define MMR3_M22E 020 /* 22b mem mgt enbl */
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#define MMR3_BME 040 /* DMA bus map enbl */
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#define MMR3_IMP 077 /* implemented bits */
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#define MMR3_RW 077 /* read/write bits */
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/* PDR */
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#define PDR_PRD 0000002 /* page readable */
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#define PDR_PWR 0000004 /* page writeable */
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#define PDR_ED 0000010 /* expansion dir */
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#define PDR_W 0000100 /* written flag */
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#define PDR_PLF 0077400 /* page lnt field */
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#define PDR_IMP 0177516 /* implemented bits */
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#define PDR_RW 0177416 /* read/write bits */
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/* Virtual address */
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#define VA_DF 0017777 /* displacement */
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#define VA_BN 0017700 /* block number */
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#define VA_V_APF 13 /* offset to APF */
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#define VA_V_DS 16 /* offset to space */
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#define VA_V_MODE 17 /* offset to mode */
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#define VA_DS (1u << VA_V_DS) /* data space flag */
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/* Unibus map (if present) */
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#define UBM_LNT_LW 32 /* size in LW */
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#define UBM_V_PN 13 /* page number */
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#define UBM_M_PN 037
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#define UBM_V_OFF 0 /* offset */
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#define UBM_M_OFF 017777
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#define UBM_GETPN(x) (((x) >> UBM_V_PN) & UBM_M_PN)
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#define UBM_GETOFF(x) ((x) & UBM_M_OFF)
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/* CPUERR */
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#define CPUE_RED 0004 /* red stack */
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#define CPUE_YEL 0010 /* yellow stack */
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#define CPUE_TMO 0020 /* IO page nxm */
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#define CPUE_NXM 0040 /* memory nxm */
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#define CPUE_ODD 0100 /* odd address */
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#define CPUE_HALT 0200 /* HALT not kernel */
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#define CPUE_IMP 0374 /* implemented bits */
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/* Maintenance register */
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#define MAINT_V_UQ 9 /* Q/U flag */
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#define MAINT_Q (0 << MAINT_V_UQ) /* Qbus */
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#define MAINT_U (1 << MAINT_V_UQ)
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#define MAINT_V_FPA 8 /* FPA flag */
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#define MAINT_NOFPA (0 << MAINT_V_FPA)
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#define MAINT_FPA (1 << MAINT_V_FPA)
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#define MAINT_V_TYP 4 /* system type */
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#define MAINT_KDJ (1 << MAINT_V_TYP) /* KDJ11A */
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#define MAINT_V_HTRAP 3 /* trap 4 on HALT */
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#define MAINT_HTRAP (1 << MAINT_V_HTRAP)
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#define MAINT_V_BPOK 0 /* power OK */
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#define MAINT_BPOK (1 << MAINT_V_BPOK)
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/* Floating point accumulators */
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struct fpac {
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unsigned int32 l; /* low 32b */
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unsigned int32 h; /* high 32b */
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};
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typedef struct fpac fpac_t;
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/* Device CSRs */
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#define CSR_V_GO 0 /* go */
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#define CSR_V_IE 6 /* interrupt enable */
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#define CSR_V_DONE 7 /* done */
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#define CSR_V_BUSY 11 /* busy */
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#define CSR_V_ERR 15 /* error */
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#define CSR_GO (1u << CSR_V_GO)
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#define CSR_IE (1u << CSR_V_IE)
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#define CSR_DONE (1u << CSR_V_DONE)
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#define CSR_BUSY (1u << CSR_V_BUSY)
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#define CSR_ERR (1u << CSR_V_ERR)
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/* Trap masks, descending priority order, following J-11
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An interrupt summary bit is kept with traps, to minimize overhead
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*/
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#define TRAP_V_RED 0 /* red stk abort 4 */
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#define TRAP_V_ODD 1 /* odd address 4 */
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#define TRAP_V_MME 2 /* mem mgt 250 */
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#define TRAP_V_NXM 3 /* nx memory 4 */
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#define TRAP_V_PAR 4 /* parity err 114 */
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#define TRAP_V_PRV 5 /* priv inst 4 */
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#define TRAP_V_ILL 6 /* illegal inst 10 */
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#define TRAP_V_BPT 7 /* BPT 14 */
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#define TRAP_V_IOT 8 /* IOT 20 */
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#define TRAP_V_EMT 9 /* EMT 30 */
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#define TRAP_V_TRAP 10 /* TRAP 34 */
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#define TRAP_V_TRC 11 /* T bit 14 */
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#define TRAP_V_YEL 12 /* stack 4 */
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#define TRAP_V_PWRFL 13 /* power fail 24 */
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#define TRAP_V_FPE 14 /* fpe 244 */
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#define TRAP_V_MAX 15 /* intr = max trp # */
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#define TRAP_RED (1u << TRAP_V_RED)
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#define TRAP_ODD (1u << TRAP_V_ODD)
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#define TRAP_MME (1u << TRAP_V_MME)
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#define TRAP_NXM (1u << TRAP_V_NXM)
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#define TRAP_PAR (1u << TRAP_V_PAR)
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#define TRAP_PRV (1u << TRAP_V_PRV)
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#define TRAP_ILL (1u << TRAP_V_ILL)
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#define TRAP_BPT (1u << TRAP_V_BPT)
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#define TRAP_IOT (1u << TRAP_V_IOT)
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#define TRAP_EMT (1u << TRAP_V_EMT)
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#define TRAP_TRAP (1u << TRAP_V_TRAP)
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#define TRAP_TRC (1u << TRAP_V_TRC)
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#define TRAP_YEL (1u << TRAP_V_YEL)
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#define TRAP_PWRFL (1u << TRAP_V_PWRFL)
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#define TRAP_FPE (1u << TRAP_V_FPE)
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#define TRAP_INT (1u << TRAP_V_MAX)
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#define TRAP_ALL ((1u << TRAP_V_MAX) - 1) /* all traps */
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#define VEC_RED 0004 /* trap vectors */
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#define VEC_ODD 0004
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#define VEC_MME 0250
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#define VEC_NXM 0004
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#define VEC_PAR 0114
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#define VEC_PRV 0004
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#define VEC_ILL 0010
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#define VEC_BPT 0014
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#define VEC_IOT 0020
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#define VEC_EMT 0030
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#define VEC_TRAP 0034
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#define VEC_TRC 0014
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#define VEC_YEL 0004
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#define VEC_PWRFL 0024
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#define VEC_FPE 0244
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/* Simulator stop codes; codes 1:TRAP_V_MAX correspond to traps 0:TRAPMAX-1 */
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#define STOP_HALT (TRAP_V_MAX + 1) /* HALT instruction */
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#define STOP_IBKPT (TRAP_V_MAX + 2) /* instruction bkpt */
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#define STOP_WAIT (TRAP_V_MAX + 3) /* wait, no events */
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#define STOP_VECABORT (TRAP_V_MAX + 4) /* abort vector read */
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#define STOP_SPABORT (TRAP_V_MAX + 5) /* abort trap push */
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#define STOP_RQ (TRAP_V_MAX + 6) /* RQDX3 panic */
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#define STOP_SANITY (TRAP_V_MAX + 7) /* sanity timer exp */
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#define STOP_DTOFF (TRAP_V_MAX + 8) /* DECtape off reel */
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#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
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/* Timers */
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#define TMR_CLK 0 /* line clock */
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#define TMR_PCLK 1 /* KW11P */
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/* IO parameters */
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#define DZ_MUXES 4 /* max # of muxes */
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#define DZ_LINES 8 /* lines per mux */
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#define MT_MAXFR (1 << 16) /* magtape max rec */
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#define AUTO_LNT 34 /* autoconfig ranks */
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#define DIB_MAX 100 /* max DIBs */
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#define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */
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#define DEV_V_QBUS (DEV_V_UF + 1) /* Qbus */
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#define DEV_V_Q18 (DEV_V_UF + 2) /* Qbus with <= 256KB */
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#define DEV_V_FLTA (DEV_V_UF + 3) /* flt addr */
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#define DEV_UBUS (1u << DEV_V_UBUS)
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#define DEV_QBUS (1u << DEV_V_QBUS)
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#define DEV_Q18 (1u << DEV_V_Q18)
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#define DEV_FLTA (1u << DEV_V_FLTA)
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#define UNIBUS (cpu_18b || cpu_ubm) /* T if 18b */
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#define MAP 1 /* mapped */
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#define NOMAP 0 /* not mapped */
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#define DEV_RDX 8 /* default device radix */
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/* Device information block */
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#define VEC_DEVMAX 4 /* max device vec */
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struct pdp_dib {
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uint32 ba; /* base addr */
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uint32 lnt; /* length */
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t_stat (*rd)(int32 *dat, int32 ad, int32 md);
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t_stat (*wr)(int32 dat, int32 ad, int32 md);
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int32 vnum; /* vectors: number */
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int32 vloc; /* locator */
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int32 vec; /* value */
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int32 (*ack[VEC_DEVMAX])(void); /* ack routines */
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};
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typedef struct pdp_dib DIB;
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/* I/O page layout - XUB, RQB,RQC,RQD float based on number of DZ's */
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#define IOBA_DZ (IOPAGEBASE + 000100) /* DZ11 */
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#define IOLN_DZ 010
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#define IOBA_XUB (IOPAGEBASE + 000330 + (020 * (DZ_MUXES / 2)))
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#define IOLN_XUB 010
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#define IOBA_RQB (IOPAGEBASE + 000334 + (020 * (DZ_MUXES / 2)))
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#define IOLN_RQB 004
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#define IOBA_RQC (IOPAGEBASE + IOBA_RQB + IOLN_RQB)
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#define IOLN_RQC 004
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#define IOBA_RQD (IOPAGEBASE + IOBA_RQC + IOLN_RQC)
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#define IOLN_RQD 004
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#define IOBA_UBM (IOPAGEBASE + 010200) /* Unibus map */
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#define IOLN_UBM (UBM_LNT_LW * sizeof (int32))
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#define IOBA_RQ (IOPAGEBASE + 012150) /* RQDX3 */
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#define IOLN_RQ 004
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#define IOBA_APR (IOPAGEBASE + 012200) /* APRs */
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#define IOLN_APR 0200
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#define IOBA_MMR3 (IOPAGEBASE + 012516) /* MMR3 */
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#define IOLN_MMR3 002
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#define IOBA_TM (IOPAGEBASE + 012520) /* TM11 */
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#define IOLN_TM 014
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#define IOBA_TS (IOPAGEBASE + 012520) /* TS11 */
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#define IOLN_TS 004
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#define IOBA_PCLK (IOPAGEBASE + 012540) /* KW11P */
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#define IOLN_PCLK 006
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#define IOBA_RL (IOPAGEBASE + 014400) /* RL11 */
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#define IOLN_RL 012
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#define IOBA_XQ (IOPAGEBASE + 014440) /* DEQNA/DELQA */
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#define IOLN_XQ 020
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#define IOBA_XQB (IOPAGEBASE + 014460) /* 2nd DEQNA/DELQA */
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#define IOLN_XQB 020
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#define IOBA_TQ (IOPAGEBASE + 014500) /* TMSCP */
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#define IOLN_TQ 004
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#define IOBA_XU (IOPAGEBASE + 014510) /* DEUNA/DELUA */
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#define IOLN_XU 010
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#define IOBA_RP (IOPAGEBASE + 016700) /* RP/RM */
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#define IOLN_RP 054
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#define IOBA_RX (IOPAGEBASE + 017170) /* RX11 */
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#define IOLN_RX 004
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#define IOBA_RY (IOPAGEBASE + 017170) /* RY11 */
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#define IOLN_RY 004
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#define IOBA_TC (IOPAGEBASE + 017340) /* TC11 */
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#define IOLN_TC 012
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#define IOBA_RK (IOPAGEBASE + 017400) /* RK11 */
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#define IOLN_RK 020
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#define IOBA_HK (IOPAGEBASE + 017440) /* RK611 */
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#define IOLN_HK 040
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#define IOBA_LPT (IOPAGEBASE + 017514) /* LP11 */
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#define IOLN_LPT 004
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#define IOBA_CLK (IOPAGEBASE + 017546) /* KW11L */
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#define IOLN_CLK 002
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#define IOBA_PTR (IOPAGEBASE + 017550) /* PC11 reader */
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#define IOLN_PTR 004
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#define IOBA_PTP (IOPAGEBASE + 017554) /* PC11 punch */
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#define IOLN_PTP 004
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#define IOBA_TTI (IOPAGEBASE + 017560) /* DL11 rcv */
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#define IOLN_TTI 004
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#define IOBA_TTO (IOPAGEBASE + 017564) /* DL11 xmt */
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#define IOLN_TTO 004
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#define IOBA_SRMM (IOPAGEBASE + 017570) /* SR, MMR0-2 */
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#define IOLN_SRMM 010
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#define IOBA_APR1 (IOPAGEBASE + 017600) /* APRs */
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#define IOLN_APR1 0100
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#define IOBA_CPU (IOPAGEBASE + 017740) /* CPU reg */
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#define IOLN_CPU 040
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/* Interrupt assignments; within each level, priority is right to left */
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#define IPL_HLVL 8 /* # int levels */
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#define INT_V_PIR7 0 /* BR7 */
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#define INT_V_CLK 0 /* BR6 */
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#define INT_V_PCLK 1
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#define INT_V_DTA 2
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#define INT_V_PIR6 3
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#define INT_V_RK 0 /* BR5 */
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#define INT_V_RL 1
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#define INT_V_RX 2
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#define INT_V_TM 3
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#define INT_V_RP 4
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#define INT_V_TS 5
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#define INT_V_HK 6
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#define INT_V_RQ 7
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#define INT_V_DZRX 8
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#define INT_V_DZTX 9
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#define INT_V_TQ 10
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#define INT_V_RY 11
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#define INT_V_XQ 12
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#define INT_V_XU 13
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#define INT_V_PIR5 14
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#define INT_V_TTI 0 /* BR4 */
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#define INT_V_TTO 1
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#define INT_V_PTR 2
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#define INT_V_PTP 3
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#define INT_V_LPT 4
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#define INT_V_PIR4 5
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#define INT_V_PIR3 0 /* BR3 */
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#define INT_V_PIR2 0 /* BR2 */
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#define INT_V_PIR1 0 /* BR1 */
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#define INT_PIR7 (1u << INT_V_PIR7)
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#define INT_CLK (1u << INT_V_CLK)
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#define INT_PCLK (1u << INT_V_PCLK)
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#define INT_DTA (1u << INT_V_DTA)
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#define INT_PIR6 (1u << INT_V_PIR6)
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#define INT_RK (1u << INT_V_RK)
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#define INT_RL (1u << INT_V_RL)
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#define INT_RX (1u << INT_V_RX)
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#define INT_TM (1u << INT_V_TM)
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#define INT_RP (1u << INT_V_RP)
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#define INT_TS (1u << INT_V_TS)
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#define INT_HK (1u << INT_V_HK)
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#define INT_RQ (1u << INT_V_RQ)
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#define INT_DZRX (1u << INT_V_DZRX)
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#define INT_DZTX (1u << INT_V_DZTX)
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#define INT_TQ (1u << INT_V_TQ)
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#define INT_RY (1u << INT_V_RY)
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#define INT_XQ (1u << INT_V_XQ)
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#define INT_XU (1u << INT_V_XU)
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#define INT_PIR5 (1u << INT_V_PIR5)
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#define INT_PTR (1u << INT_V_PTR)
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#define INT_PTP (1u << INT_V_PTP)
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#define INT_TTI (1u << INT_V_TTI)
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#define INT_TTO (1u << INT_V_TTO)
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#define INT_LPT (1u << INT_V_LPT)
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#define INT_PIR4 (1u << INT_V_PIR4)
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#define INT_PIR3 (1u << INT_V_PIR3)
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#define INT_PIR2 (1u << INT_V_PIR2)
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#define INT_PIR1 (1u << INT_V_PIR1)
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#define IPL_CLK 6 /* int pri levels */
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#define IPL_PCLK 6
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#define IPL_DTA 6
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#define IPL_RK 5
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#define IPL_RL 5
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#define IPL_RX 5
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#define IPL_TM 5
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#define IPL_RP 5
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#define IPL_TS 5
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#define IPL_HK 5
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#define IPL_RQ 5
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#define IPL_DZRX 5
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#define IPL_DZTX 5
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#define IPL_TQ 5
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#define IPL_RY 5
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#define IPL_XQ 5
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#define IPL_XU 5
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#define IPL_PTR 4
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#define IPL_PTP 4
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#define IPL_TTI 4
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#define IPL_TTO 4
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#define IPL_LPT 4
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#define IPL_PIR7 7
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#define IPL_PIR6 6
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#define IPL_PIR5 5
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#define IPL_PIR4 4
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#define IPL_PIR3 3
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#define IPL_PIR2 2
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#define IPL_PIR1 1
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/* Device vectors */
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#define VEC_Q 0000 /* vector base */
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#define VEC_PIRQ 0240
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#define VEC_TTI 0060
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#define VEC_TTO 0064
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#define VEC_PTR 0070
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#define VEC_PTP 0074
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#define VEC_CLK 0100
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#define VEC_PCLK 0104
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#define VEC_XQ 0120
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#define VEC_XU 0120
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#define VEC_RQ 0154
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#define VEC_RL 0160
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#define VEC_LPT 0200
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#define VEC_HK 0210
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#define VEC_RK 0220
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#define VEC_DTA 0214
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#define VEC_TM 0224
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#define VEC_TS 0224
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#define VEC_RP 0254
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#define VEC_TQ 0260
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#define VEC_RX 0264
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#define VEC_RY 0264
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#define VEC_DZRX 0300
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#define VEC_DZTX 0304
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/* Autoconfigure ranks */
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|
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#define RANK_DZ 8
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#define RANK_RL 14
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#define RANK_RX 18
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#define RANK_XU 25
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#define RANK_RQ 26
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#define RANK_TQ 30
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/* Interrupt macros */
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#define IVCL(dv) ((IPL_##dv * 32) + INT_V_##dv)
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#define IREQ(dv) int_req[IPL_##dv]
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#define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv)
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#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
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|
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/* CPU and FPU macros */
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|
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#define update_MM ((MMR0 & MMR0_FREEZE) == 0)
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#define setTRAP(name) trap_req = trap_req | (name)
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#define setCPUERR(name) CPUERR = CPUERR | (name)
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#define ABORT(val) longjmp (save_env, (val))
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#define SP R[6]
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#define PC R[7]
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|
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/* Function prototypes */
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t_bool Map_Addr (uint32 qa, uint32 *ma);
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int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf, t_bool map);
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int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf, t_bool map);
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int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf, t_bool map);
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int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf, t_bool map);
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t_stat set_addr (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat show_addr (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat set_addr_flt (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat set_vec (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat show_vec (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat auto_config (uint32 rank, uint32 num);
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#endif
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