1238 lines
43 KiB
C
1238 lines
43 KiB
C
/* pdp10_ksio.c: PDP-10 KS10 I/O subsystem simulator
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Copyright (c) 1993-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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uba Unibus adapters
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22-Sep-05 RMS Fixed declarations (from Sterling Garwood)
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25-Jan-04 RMS Added stub floating address routine
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12-Mar-03 RMS Added logical name support
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10-Oct-02 RMS Revised for dynamic table generation
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Added SHOW IOSPACE routine
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29-Sep-02 RMS Added variable vector, central map support
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25-Jan-02 RMS Revised for multiple DZ11's
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06-Jan-02 RMS Revised enable/disable support
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23-Sep-01 RMS New IO page address constants
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07-Sep-01 RMS Revised device disable mechanism
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25-Aug-01 RMS Enabled DZ11
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21-Aug-01 RMS Updated DZ11 disable
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01-Jun-01 RMS Updated DZ11 vectors
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12-May-01 RMS Fixed typo
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The KS10 uses the PDP-11 Unibus for its I/O, via adapters. While
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nominally four adapters are supported, in practice only 1 and 3
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are implemented. The disks are placed on adapter 1, the rest of
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the I/O devices on adapter 3.
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In theory, we should maintain completely separate Unibuses, with
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distinct PI systems. In practice, this simulator has so few devices
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that we can get away with a single PI system, masking for which
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devices are on adapter 1, and which on adapter 3. The Unibus
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implementation is modeled on the Qbus in the PDP-11 simulator and
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is described there.
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The I/O subsystem is programmed by I/O instructions which create
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Unibus operations (read, read pause, write, write byte). DMA is
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the responsibility of the I/O device simulators, which also implement
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Unibus to physical memory mapping.
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The priority interrupt subsystem (and other privileged functions)
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is programmed by I/O instructions with internal devices codes
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(opcodes 700-702). These are dispatched here, although many are
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handled in the memory management unit or elsewhere.
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The ITS instructions are significantly different from the TOPS-10/20
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instructions. They do not use the extended address calculation but
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instead provide instruction variants (Q for Unibus adapter 1, I for
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Unibus adapter 3) which insert the Unibus adapter number into the
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effective address.
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*/
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#include "pdp10_defs.h"
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#include <setjmp.h>
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#include "sim_sock.h"
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#include "sim_tmxr.h"
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#define AUTO_MAXC 32 /* Maximum number of controllers */
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#define AUTO_CSRBASE 0010
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#define AUTO_CSRMAX 04000
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#define AUTO_VECBASE 0300
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#define XBA_MBZ 0400000 /* ba mbz */
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#define eaRB (ea & ~1)
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#define GETBYTE(ea,x) ((((ea) & 1)? (x) >> 8: (x)) & 0377)
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#define UBNXM_FAIL(pa,op) \
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n = iocmap[GET_IOUBA (pa)]; \
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if (n >= 0) \
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ubcs[n] = ubcs[n] | UBCS_TMO | UBCS_NXD; \
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pager_word = PF_HARD | PF_VIRT | PF_IO | \
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((op == WRITEB)? PF_BYTE: 0) | \
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(TSTF (F_USR)? PF_USER: 0) | (pa); \
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ABORT (PAGE_FAIL)
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/* Unibus adapter data */
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int32 ubcs[UBANUM] = { 0 }; /* status registers */
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int32 ubmap[UBANUM][UMAP_MEMSIZE] = { 0 }; /* Unibus maps */
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int32 int_req = 0; /* interrupt requests */
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int32 autcon_enb = 1; /* auto configure enabled */
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/* Map IO controller numbers to Unibus adapters: -1 = non-existent */
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static int iocmap[IO_N_UBA] = { /* map I/O ext to UBA # */
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-1, 0, -1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
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};
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static const int32 ubabr76[UBANUM] = {
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INT_UB1 & (INT_IPL7 | INT_IPL6), INT_UB3 & (INT_IPL7 | INT_IPL6)
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};
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static const int32 ubabr54[UBANUM] = {
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INT_UB1 & (INT_IPL5 | INT_IPL4), INT_UB3 & (INT_IPL5 | INT_IPL4)
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};
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static const int32 ubashf[4] = { 18, 26, 0, 8 };
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extern d10 *M; /* main memory */
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extern d10 *ac_cur;
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extern d10 pager_word;
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extern int32 flags;
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extern const int32 pi_l2bit[8];
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extern UNIT cpu_unit;
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extern FILE *sim_log;
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extern jmp_buf save_env;
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extern DEVICE *sim_devices[];
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extern int32 pi_eval (void);
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extern int32 rp_inta (void);
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extern int32 tu_inta (void);
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extern int32 lp20_inta (void);
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extern int32 dz_rxinta (void);
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extern int32 dz_txinta (void);
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t_stat ubmap_rd (int32 *data, int32 addr, int32 access);
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t_stat ubmap_wr (int32 data, int32 addr, int32 access);
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t_stat ubs_rd (int32 *data, int32 addr, int32 access);
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t_stat ubs_wr (int32 data, int32 addr, int32 access);
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t_stat rd_zro (int32 *data, int32 addr, int32 access);
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t_stat wr_nop (int32 data, int32 addr, int32 access);
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t_stat uba_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
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t_stat uba_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
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t_stat uba_reset (DEVICE *dptr);
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d10 ReadIO (a10 ea);
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void WriteIO (a10 ea, d10 val, int32 mode);
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/* Unibus adapter data structures
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uba_dev UBA device descriptor
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uba_unit UBA units
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uba_reg UBA register list
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*/
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DIB ubmp1_dib = { IOBA_UBMAP1, IOLN_UBMAP1, &ubmap_rd, &ubmap_wr, 0 };
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DIB ubmp3_dib = { IOBA_UBMAP3, IOLN_UBMAP3, &ubmap_rd, &ubmap_wr, 0 };
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DIB ubcs1_dib = { IOBA_UBCS1, IOLN_UBCS1, &ubs_rd, &ubs_wr, 0 };
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DIB ubcs3_dib = { IOBA_UBCS3, IOLN_UBCS3, &ubs_rd, &ubs_wr, 0 };
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DIB ubmn1_dib = { IOBA_UBMNT1, IOLN_UBMNT1, &rd_zro, &wr_nop, 0 };
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DIB ubmn3_dib = { IOBA_UBMNT3, IOLN_UBMNT3, &rd_zro, &wr_nop, 0 };
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DIB msys_dib = { 00100000, 1, &rd_zro, &wr_nop, 0 };
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UNIT uba_unit[] = {
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{ UDATA (NULL, UNIT_FIX, UMAP_MEMSIZE) },
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{ UDATA (NULL, UNIT_FIX, UMAP_MEMSIZE) }
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};
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REG uba_reg[] = {
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{ ORDATA (INTREQ, int_req, 32), REG_RO },
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{ ORDATA (UB1CS, ubcs[0], 18) },
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{ ORDATA (UB3CS, ubcs[1], 18) },
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{ NULL }
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};
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DEVICE uba_dev = {
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"UBA", uba_unit, uba_reg, NULL,
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UBANUM, 8, UMAP_ASIZE, 1, 8, 32,
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&uba_ex, &uba_dep, &uba_reset,
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NULL, NULL, NULL,
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NULL, 0
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};
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/* PDP-11 I/O structures */
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DIB *dib_tab[DIB_MAX]; /* run-time DIBs */
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int32 (*int_ack[32])(void); /* int ack routines */
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int32 int_vec[32]; /* int vectors */
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DIB *std_dib[] = { /* standard DIBs */
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&ubmp1_dib,
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&ubmp3_dib,
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&ubcs1_dib,
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&ubcs3_dib,
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&ubmn1_dib,
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&ubmn3_dib,
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&msys_dib,
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NULL
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};
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/* IO 710 (DEC) TIOE - test I/O word, skip if zero
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(ITS) IORDI - read word from Unibus 3
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returns TRUE if skip, FALSE otherwise
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*/
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t_bool io710 (int32 ac, a10 ea)
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{
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d10 val;
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if (Q_ITS) /* IORDI */
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AC(ac) = ReadIO (IO_UBA3 | ea);
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else { /* TIOE */
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val = ReadIO (ea); /* read word */
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if ((AC(ac) & val) == 0)
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return TRUE;
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}
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return FALSE;
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}
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/* IO 711 (DEC) TION - test I/O word, skip if non-zero
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(ITS) IORDQ - read word from Unibus 1
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returns TRUE if skip, FALSE otherwise
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*/
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t_bool io711 (int32 ac, a10 ea)
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{
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d10 val;
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if (Q_ITS) /* IORDQ */
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AC(ac) = ReadIO (IO_UBA1 | ea);
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else { /* TION */
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val = ReadIO (ea); /* read word */
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if ((AC(ac) & val) != 0)
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return TRUE;
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}
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return FALSE;
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}
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/* IO 712 (DEC) RDIO - read I/O word, addr in ea
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(ITS) IORD - read I/O word, addr in M[ea]
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*/
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d10 io712 (a10 ea)
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{
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return ReadIO (ea); /* RDIO, IORD */
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}
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/* IO 713 (DEC) WRIO - write I/O word, addr in ea
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(ITS) IOWR - write I/O word, addr in M[ea]
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*/
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void io713 (d10 val, a10 ea)
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{
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WriteIO (ea, val & 0177777, WRITE); /* WRIO, IOWR */
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return;
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}
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/* IO 714 (DEC) BSIO - set bit in I/O address
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(ITS) IOWRI - write word to Unibus 3
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*/
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void io714 (d10 val, a10 ea)
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{
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d10 temp;
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val = val & 0177777;
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if (Q_ITS) /* IOWRI */
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WriteIO (IO_UBA3 | ea, val, WRITE);
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else {
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temp = ReadIO (ea); /* BSIO */
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temp = temp | val;
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WriteIO (ea, temp, WRITE);
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}
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return;
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}
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/* IO 715 (DEC) BCIO - clear bit in I/O address
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(ITS) IOWRQ - write word to Unibus 1
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*/
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void io715 (d10 val, a10 ea)
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{
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d10 temp;
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val = val & 0177777;
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if (Q_ITS) /* IOWRQ */
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WriteIO (IO_UBA1 | ea, val, WRITE);
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else {
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temp = ReadIO (ea); /* BCIO */
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temp = temp & ~val;
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WriteIO (ea, temp, WRITE);
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}
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return;
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}
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/* IO 720 (DEC) TIOEB - test I/O byte, skip if zero
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(ITS) IORDBI - read byte from Unibus 3
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returns TRUE if skip, FALSE otherwise
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*/
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t_bool io720 (int32 ac, a10 ea)
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{
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d10 val;
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if (Q_ITS) { /* IORDBI */
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val = ReadIO (IO_UBA3 | eaRB);
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AC(ac) = GETBYTE (ea, val);
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}
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else { /* TIOEB */
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val = ReadIO (eaRB);
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val = GETBYTE (ea, val);
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if ((AC(ac) & val) == 0)
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return TRUE;
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}
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return FALSE;
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}
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/* IO 721 (DEC) TIONB - test I/O word, skip if non-zero
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(ITS) IORDBQ - read word from Unibus 1
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returns TRUE if skip, FALSE otherwise
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*/
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t_bool io721 (int32 ac, a10 ea)
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{
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d10 val;
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if (Q_ITS) { /* IORDBQ */
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val = ReadIO (IO_UBA1 | eaRB);
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AC(ac) = GETBYTE (ea, val);
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}
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else { /* TIONB */
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val = ReadIO (eaRB);
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val = GETBYTE (ea, val);
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if ((AC(ac) & val) != 0)
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return TRUE;
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}
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return FALSE;
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}
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/* IO 722 (DEC) RDIOB - read I/O byte, addr in ea
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(ITS) IORDB - read I/O byte, addr in M[ea]
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*/
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d10 io722 (a10 ea)
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{
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d10 val;
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val = ReadIO (eaRB); /* RDIOB, IORDB */
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return GETBYTE (ea, val);
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}
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/* IO 723 (DEC) WRIOB - write I/O byte, addr in ea
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(ITS) IOWRB - write I/O byte, addr in M[ea]
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*/
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void io723 (d10 val, a10 ea)
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{
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WriteIO (ea, val & 0377, WRITEB); /* WRIOB, IOWRB */
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return;
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}
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/* IO 724 (DEC) BSIOB - set bit in I/O byte address
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(ITS) IOWRBI - write byte to Unibus 3
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*/
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void io724 (d10 val, a10 ea)
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{
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d10 temp;
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val = val & 0377;
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if (Q_ITS) /* IOWRBI */
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WriteIO (IO_UBA3 | ea, val, WRITEB);
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else {
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temp = ReadIO (eaRB); /* BSIOB */
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temp = GETBYTE (ea, temp);
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temp = temp | val;
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WriteIO (ea, temp, WRITEB);
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}
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return;
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}
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/* IO 725 (DEC) BCIOB - clear bit in I/O byte address
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(ITS) IOWRBQ - write byte to Unibus 1
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*/
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void io725 (d10 val, a10 ea)
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{
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d10 temp;
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val = val & 0377;
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if (Q_ITS) /* IOWRBQ */
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WriteIO (IO_UBA1 | ea, val, WRITEB);
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else {
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temp = ReadIO (eaRB); /* BCIOB */
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temp = GETBYTE (ea, temp);
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temp = temp & ~val;
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WriteIO (ea, temp, WRITEB);
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}
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return;
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}
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/* Read and write I/O devices.
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These routines are the linkage between the 64b world of the main
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simulator and the 32b world of the device simulators.
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*/
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d10 ReadIO (a10 ea)
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{
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uint32 pa = (uint32) ea;
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int32 i, n, val;
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DIB *dibp;
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for (i = 0; (dibp = dib_tab[i]); i++ ) {
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if ((pa >= dibp->ba) &&
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(pa < (dibp->ba + dibp->lnt))) {
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dibp->rd (&val, pa, READ);
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pi_eval ();
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return ((d10) val);
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}
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}
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UBNXM_FAIL (pa, READ);
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}
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void WriteIO (a10 ea, d10 val, int32 mode)
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{
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uint32 pa = (uint32) ea;
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int32 i, n;
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DIB *dibp;
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for (i = 0; (dibp = dib_tab[i]); i++ ) {
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if ((pa >= dibp->ba) &&
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(pa < (dibp->ba + dibp->lnt))) {
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dibp->wr ((int32) val, pa, mode);
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pi_eval ();
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return;
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}
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}
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UBNXM_FAIL (pa, mode);
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}
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/* Mapped read and write routines - used by standard Unibus devices on Unibus 1 */
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a10 Map_Addr10 (a10 ba, int32 ub)
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{
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a10 pa10;
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int32 vpn = PAG_GETVPN (ba >> 2); /* get PDP-10 page number */
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if ((vpn >= UMAP_MEMSIZE) || (ba & XBA_MBZ) || /* invalid map? */
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((ubmap[ub][vpn] & UMAP_VLD) == 0))
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return -1;
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pa10 = (ubmap[ub][vpn] + PAG_GETOFF (ba >> 2)) & PAMASK;
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return pa10;
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}
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int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf)
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{
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uint32 lim;
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a10 pa10;
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lim = ba + bc;
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for ( ; ba < lim; ba++) { /* by bytes */
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pa10 = Map_Addr10 (ba, 1); /* map addr */
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if ((pa10 < 0) || MEM_ADDR_NXM (pa10)) { /* inv map or NXM? */
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ubcs[1] = ubcs[1] | UBCS_TMO; /* UBA times out */
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return (lim - ba); /* return bc */
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}
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*buf++ = (uint8) ((M[pa10] >> ubashf[ba & 3]) & 0377);
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}
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return 0;
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}
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int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf)
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{
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uint32 lim;
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a10 pa10;
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ba = ba & ~01; /* align start */
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lim = ba + (bc & ~01);
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for ( ; ba < lim; ba = ba + 2) { /* by words */
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pa10 = Map_Addr10 (ba, 1); /* map addr */
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if ((pa10 < 0) || MEM_ADDR_NXM (pa10)) { /* inv map or NXM? */
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ubcs[1] = ubcs[1] | UBCS_TMO; /* UBA times out */
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return (lim - ba); /* return bc */
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}
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*buf++ = (uint16) ((M[pa10] >> ((ba & 2)? 0: 18)) & 0177777);
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}
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return 0;
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}
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int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf)
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{
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uint32 lim;
|
|
a10 pa10;
|
|
d10 mask;
|
|
|
|
lim = ba + bc;
|
|
for ( ; ba < lim; ba++) { /* by bytes */
|
|
pa10 = Map_Addr10 (ba, 1); /* map addr */
|
|
if ((pa10 < 0) || MEM_ADDR_NXM (pa10)) { /* inv map or NXM? */
|
|
ubcs[1] = ubcs[1] | UBCS_TMO; /* UBA times out */
|
|
return (lim - ba); /* return bc */
|
|
}
|
|
mask = 0377;
|
|
M[pa10] = (M[pa10] & ~(mask << ubashf[ba & 3])) |
|
|
(((d10) *buf++) << ubashf[ba & 3]);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf)
|
|
{
|
|
uint32 lim;
|
|
a10 pa10;
|
|
d10 val;
|
|
|
|
ba = ba & ~01; /* align start */
|
|
lim = ba + (bc & ~01);
|
|
for ( ; ba < lim; ba++) { /* by bytes */
|
|
pa10 = Map_Addr10 (ba, 1); /* map addr */
|
|
if ((pa10 < 0) || MEM_ADDR_NXM (pa10)) { /* inv map or NXM? */
|
|
ubcs[1] = ubcs[1] | UBCS_TMO; /* UBA times out */
|
|
return (lim - ba); /* return bc */
|
|
}
|
|
val = *buf++; /* get data */
|
|
if (ba & 2)
|
|
M[pa10] = (M[pa10] & 0777777600000) | val;
|
|
else M[pa10] = (M[pa10] & 0600000777777) | (val << 18);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* Evaluate Unibus priority interrupts */
|
|
|
|
int32 pi_ub_eval ()
|
|
{
|
|
int32 i, lvl;
|
|
|
|
for (i = lvl = 0; i < UBANUM; i++) {
|
|
if (int_req & ubabr76[i])
|
|
lvl = lvl | pi_l2bit[UBCS_GET_HI (ubcs[i])];
|
|
if (int_req & ubabr54[i])
|
|
lvl = lvl | pi_l2bit[UBCS_GET_LO (ubcs[i])];
|
|
}
|
|
return lvl;
|
|
}
|
|
|
|
/* Return Unibus device vector
|
|
|
|
Takes as input the request level calculated by pi_eval
|
|
If there is an interrupting Unibus device at that level, return its vector,
|
|
otherwise, returns 0
|
|
*/
|
|
|
|
int32 pi_ub_vec (int32 rlvl, int32 *uba)
|
|
{
|
|
int32 i, masked_irq;
|
|
|
|
for (i = masked_irq = 0; i < UBANUM; i++) {
|
|
if ((rlvl == UBCS_GET_HI (ubcs[i])) && /* req on hi level? */
|
|
(masked_irq = int_req & ubabr76[i]))
|
|
break;
|
|
if ((rlvl == UBCS_GET_LO (ubcs[i])) && /* req on lo level? */
|
|
(masked_irq = int_req & ubabr54[i]))
|
|
break;
|
|
}
|
|
*uba = (i << 1) + 1; /* store uba # */
|
|
for (i = 0; (i < 32) && masked_irq; i++) { /* find hi pri req */
|
|
if ((masked_irq >> i) & 1) {
|
|
int_req = int_req & ~(1u << i); /* clear req */
|
|
if (int_ack[i])
|
|
return int_ack[i]();
|
|
return int_vec[i]; /* return vector */
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* Unibus adapter map routines */
|
|
|
|
t_stat ubmap_rd (int32 *val, int32 pa, int32 mode)
|
|
{
|
|
int32 n = iocmap[GET_IOUBA (pa)];
|
|
|
|
if (n < 0)
|
|
ABORT (STOP_ILLIOC);
|
|
*val = ubmap[n][pa & UMAP_AMASK];
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat ubmap_wr (int32 val, int32 pa, int32 mode)
|
|
{
|
|
int32 n = iocmap[GET_IOUBA (pa)];
|
|
|
|
if (n < 0)
|
|
ABORT (STOP_ILLIOC);
|
|
ubmap[n][pa & UMAP_AMASK] = UMAP_POSFL (val) | UMAP_POSPN (val);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Unibus adapter control/status routines */
|
|
|
|
t_stat ubs_rd (int32 *val, int32 pa, int32 mode)
|
|
{
|
|
int32 n = iocmap[GET_IOUBA (pa)];
|
|
|
|
if (n < 0)
|
|
ABORT (STOP_ILLIOC);
|
|
if (int_req & ubabr76[n])
|
|
ubcs[n] = ubcs[n] | UBCS_HI;
|
|
if (int_req & ubabr54[n])
|
|
ubcs[n] = ubcs[n] | UBCS_LO;
|
|
*val = ubcs[n] = ubcs[n] & ~UBCS_RDZ;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat ubs_wr (int32 val, int32 pa, int32 mode)
|
|
{
|
|
int32 n = iocmap[GET_IOUBA (pa)];
|
|
|
|
if (n < 0)
|
|
ABORT (STOP_ILLIOC);
|
|
if (val & UBCS_INI) {
|
|
reset_all (5); /* start after UBA */
|
|
ubcs[n] = val & UBCS_DXF;
|
|
}
|
|
else ubcs[n] = val & UBCS_RDW;
|
|
if (int_req & ubabr76[n])
|
|
ubcs[n] = ubcs[n] | UBCS_HI;
|
|
if (int_req & ubabr54[n])
|
|
ubcs[n] = ubcs[n] | UBCS_LO;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Unibus adapter read zero/write ignore routines */
|
|
|
|
t_stat rd_zro (int32 *val, int32 pa, int32 mode)
|
|
{
|
|
*val = 0;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat wr_nop (int32 val, int32 pa, int32 mode)
|
|
{
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Simulator interface routines */
|
|
|
|
t_stat uba_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw)
|
|
{
|
|
int32 uba = uptr - uba_unit;
|
|
|
|
if (addr >= UMAP_MEMSIZE)
|
|
return SCPE_NXM;
|
|
*vptr = ubmap[uba][addr];
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat uba_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw)
|
|
{
|
|
int32 uba = uptr - uba_unit;
|
|
|
|
if (addr >= UMAP_MEMSIZE)
|
|
return SCPE_NXM;
|
|
ubmap[uba][addr] = (int32) val & UMAP_MASK;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat uba_reset (DEVICE *dptr)
|
|
{
|
|
int32 i, uba;
|
|
|
|
int_req = 0;
|
|
for (uba = 0; uba < UBANUM; uba++) {
|
|
ubcs[uba] = 0;
|
|
for (i = 0; i < UMAP_MEMSIZE; i++)
|
|
ubmap[uba][i] = 0;
|
|
}
|
|
pi_eval ();
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Change device address */
|
|
|
|
t_stat set_addr (UNIT *uptr, int32 val, char *cptr, void *desc)
|
|
{
|
|
DEVICE *dptr;
|
|
DIB *dibp;
|
|
uint32 newba;
|
|
t_stat r;
|
|
|
|
if (cptr == NULL)
|
|
return SCPE_ARG;
|
|
if ((val == 0) || (uptr == NULL))
|
|
return SCPE_IERR;
|
|
dptr = find_dev_from_unit (uptr);
|
|
if (dptr == NULL)
|
|
return SCPE_IERR;
|
|
dibp = (DIB *) dptr->ctxt;
|
|
if (dibp == NULL)
|
|
return SCPE_IERR;
|
|
newba = (uint32) get_uint (cptr, 8, PAMASK, &r); /* get new */
|
|
if ((r != SCPE_OK) || (newba == dibp->ba))
|
|
return r;
|
|
if (GET_IOUBA (newba) != GET_IOUBA (dibp->ba))
|
|
return SCPE_ARG;
|
|
if (newba % ((uint32) val)) /* check modulus */
|
|
return SCPE_ARG;
|
|
dibp->ba = newba; /* store */
|
|
autcon_enb = 0; /* autoconfig off */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Show device address */
|
|
|
|
t_stat show_addr (FILE *st, UNIT *uptr, int32 val, void *desc)
|
|
{
|
|
DEVICE *dptr;
|
|
DIB *dibp;
|
|
|
|
if (uptr == NULL)
|
|
return SCPE_IERR;
|
|
dptr = find_dev_from_unit (uptr);
|
|
if (dptr == NULL)
|
|
return SCPE_IERR;
|
|
dibp = (DIB *) dptr->ctxt;
|
|
if (dibp == NULL)
|
|
return SCPE_IERR;
|
|
if (((dibp->ba>>IO_V_UBA) != 1) &&
|
|
((dibp->ba>>IO_V_UBA) != 3))
|
|
return SCPE_IERR;
|
|
fprintf (st, "address=%07o", dibp->ba);
|
|
if (dibp->lnt > 1)
|
|
fprintf (st, "-%07o", dibp->ba + dibp->lnt - 1);
|
|
if ((dibp->ba & ((1 << IO_V_UBA) - 1)) < AUTO_CSRBASE + AUTO_CSRMAX)
|
|
fprintf (st, "*");
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Change device vector */
|
|
|
|
t_stat set_vec (UNIT *uptr, int32 arg, char *cptr, void *desc)
|
|
{
|
|
DEVICE *dptr;
|
|
DIB *dibp;
|
|
uint32 newvec;
|
|
t_stat r;
|
|
|
|
if (cptr == NULL)
|
|
return SCPE_ARG;
|
|
if (uptr == NULL)
|
|
return SCPE_IERR;
|
|
dptr = find_dev_from_unit (uptr);
|
|
if (dptr == NULL)
|
|
return SCPE_IERR;
|
|
dibp = (DIB *) dptr->ctxt;
|
|
if (dibp == NULL)
|
|
return SCPE_IERR;
|
|
newvec = (uint32) get_uint (cptr, 8, VEC_Q + 01000, &r);
|
|
if ((r != SCPE_OK) || (newvec == VEC_Q) ||
|
|
((newvec + (dibp->vnum * 4)) >= (VEC_Q + 01000)) ||
|
|
(newvec & ((dibp->vnum > 1)? 07: 03)))
|
|
return SCPE_ARG;
|
|
dibp->vec = newvec;
|
|
autcon_enb = 0; /* autoconfig off */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Show device vector */
|
|
|
|
t_stat show_vec (FILE *st, UNIT *uptr, int32 arg, void *desc)
|
|
{
|
|
DEVICE *dptr;
|
|
DIB *dibp;
|
|
uint32 vec, numvec;
|
|
|
|
if (uptr == NULL)
|
|
return SCPE_IERR;
|
|
dptr = find_dev_from_unit (uptr);
|
|
if (dptr == NULL)
|
|
return SCPE_IERR;
|
|
dibp = (DIB *) dptr->ctxt;
|
|
if (dibp == NULL)
|
|
return SCPE_IERR;
|
|
vec = dibp->vec;
|
|
if (arg)
|
|
numvec = arg;
|
|
else numvec = dibp->vnum;
|
|
if (vec == 0)
|
|
fprintf (st, "no vector");
|
|
else {
|
|
fprintf (st, "vector=%o", vec);
|
|
if (numvec > 1)
|
|
fprintf (st, "-%o", vec + (4 * (numvec - 1)));
|
|
}
|
|
if (vec >= AUTO_VECBASE)
|
|
fprintf (st, "*");
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Show vector for terminal multiplexor */
|
|
|
|
t_stat show_vec_mux (FILE *st, UNIT *uptr, int32 arg, void *desc)
|
|
{
|
|
TMXR *mp = (TMXR *) desc;
|
|
|
|
if ((mp == NULL) || (arg == 0))
|
|
return SCPE_IERR;
|
|
return show_vec (st, uptr, ((mp->lines * 2) / arg), desc);
|
|
}
|
|
|
|
/* Test for conflict in device addresses */
|
|
|
|
t_bool dev_conflict (DIB *curr)
|
|
{
|
|
uint32 i, end;
|
|
DEVICE *dptr;
|
|
DIB *dibp;
|
|
|
|
end = curr->ba + curr->lnt - 1; /* get end */
|
|
for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */
|
|
dibp = (DIB *) dptr->ctxt; /* get DIB */
|
|
if ((dibp == NULL) || (dibp == curr) ||
|
|
(dptr->flags & DEV_DIS))
|
|
continue;
|
|
if (((curr->ba >= dibp->ba) && /* overlap start? */
|
|
(curr->ba < (dibp->ba + dibp->lnt))) ||
|
|
((end >= dibp->ba) && /* overlap end? */
|
|
(end < (dibp->ba + dibp->lnt)))) {
|
|
printf ("Device %s address conflict at %08o\n",
|
|
sim_dname (dptr), dibp->ba);
|
|
if (sim_log)
|
|
fprintf (sim_log, "Device %s address conflict at %08o\n",
|
|
sim_dname (dptr), dibp->ba);
|
|
return TRUE;
|
|
}
|
|
}
|
|
return FALSE;
|
|
}
|
|
|
|
/* Build interrupt tables */
|
|
|
|
void build_int_vec (int32 vloc, int32 ivec, int32 (*iack)(void) )
|
|
{
|
|
if (iack != NULL)
|
|
int_ack[vloc] = iack;
|
|
else int_vec[vloc] = ivec;
|
|
return;
|
|
}
|
|
|
|
/* Build dib_tab from device list */
|
|
|
|
t_bool build_dib_tab (void)
|
|
{
|
|
int32 i, j, k;
|
|
DEVICE *dptr;
|
|
DIB *dibp;
|
|
|
|
for (i = 0; i < 32; i++) { /* clear intr tables */
|
|
int_vec[i] = 0;
|
|
int_ack[i] = NULL;
|
|
}
|
|
for (i = j = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */
|
|
dibp = (DIB *) dptr->ctxt; /* get DIB */
|
|
if (dibp && !(dptr->flags & DEV_DIS)) { /* defined, enabled? */
|
|
if (dibp->vnum > VEC_DEVMAX)
|
|
return SCPE_IERR;
|
|
for (k = 0; k < dibp->vnum; k++) /* loop thru vec */
|
|
build_int_vec (dibp->vloc + k, /* add vector */
|
|
dibp->vec + (k * 4), dibp->ack[k]);
|
|
if (dibp->lnt != 0) { /* I/O addresses? */
|
|
dib_tab[j++] = dibp; /* add DIB to dib_tab */
|
|
if (j >= DIB_MAX) /* too many? */
|
|
return SCPE_IERR;
|
|
}
|
|
} /* end if enabled */
|
|
} /* end for */
|
|
for (i = 0; (dibp = std_dib[i]) != NULL; i++) { /* loop thru std */
|
|
dib_tab[j++] = dibp; /* add to dib_tab */
|
|
if (j >= DIB_MAX) /* too many? */
|
|
return SCPE_IERR;
|
|
}
|
|
dib_tab[j] = NULL; /* end with NULL */
|
|
for (i = 0; (dibp = dib_tab[i]) != NULL; i++) { /* test built dib_tab */
|
|
if (dev_conflict (dibp)) /* for conflicts */
|
|
return SCPE_STOP;
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Show dib_tab */
|
|
|
|
t_stat show_iospace (FILE *st, UNIT *uptr, int32 val, void *desc)
|
|
{
|
|
int32 i, j, done = 0;
|
|
DEVICE *dptr;
|
|
DIB *dibt;
|
|
|
|
build_dib_tab (); /* build table */
|
|
while (done == 0) { /* sort ascending */
|
|
done = 1; /* assume done */
|
|
for (i = 0; dib_tab[i + 1] != NULL; i++) { /* check table */
|
|
if (dib_tab[i]->ba > dib_tab[i + 1]->ba) { /* out of order? */
|
|
dibt = dib_tab[i]; /* interchange */
|
|
dib_tab[i] = dib_tab[i + 1];
|
|
dib_tab[i + 1] = dibt;
|
|
done = 0; /* not done */
|
|
}
|
|
}
|
|
} /* end while */
|
|
for (i = 0; dib_tab[i] != NULL; i++) { /* print table */
|
|
for (j = 0, dptr = NULL; sim_devices[j] != NULL; j++) {
|
|
if (((DIB*) sim_devices[j]->ctxt) == dib_tab[i]) {
|
|
dptr = sim_devices[j];
|
|
break;
|
|
}
|
|
}
|
|
fprintf (st, "%07o - %07o\t%s\n", dib_tab[i]->ba,
|
|
dib_tab[i]->ba + dib_tab[i]->lnt - 1,
|
|
dptr? sim_dname (dptr): "CPU");
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Autoconfiguration
|
|
|
|
The table reflects the MicroVAX 3900 microcode, with one field addition - the
|
|
number of controllers field handles devices where multiple instances
|
|
are simulated through a single DEVICE structure (e.g., DZ, VH, DL, DC).
|
|
|
|
The table has been reviewed, extended and updated to reflect the contents of
|
|
the auto configure table in VMS sysgen (V5.5-2)
|
|
|
|
A minus number of vectors indicates a field that should be calculated
|
|
but not placed in the DIB (RQ, TQ dynamic vectors)
|
|
|
|
An amod value of 0 indicates that all addresses are FIXED
|
|
An vmod value of 0 indicates that all vectors are FIXED */
|
|
|
|
|
|
typedef struct {
|
|
char *dnam[AUTO_MAXC];
|
|
int32 numc;
|
|
int32 numv;
|
|
uint32 amod;
|
|
uint32 vmod;
|
|
uint32 fixa[AUTO_MAXC];
|
|
uint32 fixv[AUTO_MAXC];
|
|
} AUTO_CON;
|
|
|
|
AUTO_CON auto_tab[] = {/*c #v am vm fxa fxv */
|
|
{ { "QBA" }, 1, 0, 0, 0,
|
|
{017500} }, /* doorbell - fx CSR, no VEC */
|
|
{ { "MCTL" }, 1, 0, 0, 0,
|
|
{012100} }, /* MSV11-P - fx CSR, no VEC */
|
|
{ { "KE" }, 1, 0, 0, 0,
|
|
{017300} }, /* KE11-A - fx CSR, no VEC */
|
|
{ { "KG" }, 1, 0, 0, 0,
|
|
{010700} }, /* KG11-A - fx CSR, no VEC */
|
|
{ { "RHA", "RHB" }, 1, 1, 0, 0,
|
|
{016700, 012440}, {0254, 0224} }, /* RH11/RH70 - fx CSR, fx VEC */
|
|
{ { "CLK" }, 1, 1, 0, 0,
|
|
{017546}, {0100} }, /* KW11L - fx CSR, fx VEC */
|
|
{ { "PCLK" }, 1, 1, 0, 0,
|
|
{012540}, {0104} }, /* KW11P - fx CSR, fx VEC */
|
|
{ { "PTR" }, 1, 1, 0, 0,
|
|
{017550}, {0070} }, /* PC11 reader - fx CSR, fx VEC */
|
|
{ { "PTP" }, 1, 1, 0, 0,
|
|
{017554}, {0074} }, /* PC11 punch - fx CSR, fx VEC */
|
|
{ { "RK" }, 1, 1, 0, 0,
|
|
{017400}, {0220} }, /* RK11 - fx CSR, fx VEC */
|
|
{ { "TM" }, 1, 1, 0, 0,
|
|
{012520}, {0224} }, /* TM11 - fx CSR, fx VEC */
|
|
{ { "RC" }, 1, 1, 0, 0,
|
|
{017440}, {0210} }, /* RC11 - fx CSR, fx VEC */
|
|
{ { "RF" }, 1, 1, 0, 0,
|
|
{017460}, {0204} }, /* RF11 - fx CSR, fx VEC */
|
|
{ { "CR" }, 1, 1, 0, 0,
|
|
{017160}, {0230} }, /* CR11 - fx CSR, fx VEC */
|
|
{ { "HK" }, 1, 1, 0, 0,
|
|
{017440}, {0210} }, /* RK611 - fx CSR, fx VEC */
|
|
{ { "LPT" }, 1, 1, 0, 0,
|
|
{017514, 004004, 004014, 004024, 004034},
|
|
{0200, 0170, 0174, 0270, 0274} }, /* LP11 - fx CSR, fx VEC */
|
|
{ { "RB" }, 1, 1, 0, 0,
|
|
{015606}, {0250} }, /* RB730 - fx CSR, fx VEC */
|
|
{ { "RL" }, 1, 1, 0, 0,
|
|
{014400}, {0160} }, /* RL11 - fx CSR, fx VEC */
|
|
{ { "RL" }, 1, 1, 0, 0,
|
|
{014400}, {0160} }, /* RL11 - fx CSR, fx VEC */
|
|
{ { "DCI" }, 1, 2, 0, 8,
|
|
{014000, 014010, 014020, 014030,
|
|
014040, 014050, 014060, 014070,
|
|
014100, 014110, 014120, 014130,
|
|
014140, 014150, 014160, 014170,
|
|
014200, 014210, 014220, 014230,
|
|
014240, 014250, 014260, 014270,
|
|
014300, 014310, 014320, 014330,
|
|
014340, 014350, 014360, 014370} }, /* DC11 - fx CSRs */
|
|
{ { NULL }, 1, 2, 0, 8,
|
|
{016500, 016510, 016520, 016530,
|
|
016540, 016550, 016560, 016570,
|
|
016600, 016610, 016620, 016630,
|
|
016640, 016650, 016660, 016670} }, /* TU58 - fx CSRs */
|
|
{ { NULL }, 1, 1, 0, 4,
|
|
{015200, 015210, 015220, 015230,
|
|
015240, 015250, 015260, 015270,
|
|
015300, 015310, 015320, 015330,
|
|
015340, 015350, 015360, 015370} }, /* DN11 - fx CSRs */
|
|
{ { NULL }, 1, 1, 0, 4,
|
|
{010500, 010510, 010520, 010530,
|
|
010540, 010550, 010560, 010570,
|
|
010600, 010610, 010620, 010630,
|
|
010640, 010650, 010660, 010670} }, /* DM11B - fx CSRs */
|
|
{ { NULL }, 1, 2, 0, 8,
|
|
{007600, 007570, 007560, 007550,
|
|
007540, 007530, 007520, 007510,
|
|
007500, 007470, 007460, 007450,
|
|
007440, 007430, 007420, 007410} }, /* DR11C - fx CSRs */
|
|
{ { NULL }, 1, 1, 0, 8,
|
|
{012600, 012604, 012610, 012614,
|
|
012620, 012624, 012620, 012624} }, /* PR611 - fx CSRs */
|
|
{ { NULL }, 1, 1, 0, 8,
|
|
{017420, 017422, 017424, 017426,
|
|
017430, 017432, 017434, 017436} }, /* DT11 - fx CSRs */
|
|
{ { NULL }, 1, 2, 0, 8,
|
|
{016200, 016240} }, /* DX11 */
|
|
{ { "DLI" }, 1, 2, 0, 8,
|
|
{016500, 016510, 016520, 016530,
|
|
016540, 016550, 016560, 016570,
|
|
016600, 016610, 016620, 016630,
|
|
016740, 016750, 016760, 016770} }, /* KL11/DL11/DLV11 - fx CSRs */
|
|
{ { NULL }, 1, 2, 0, 8, { 0 } }, /* DLV11J - fx CSRs */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* DJ11 */
|
|
{ { NULL }, 1, 2, 16, 8 }, /* DH11 */
|
|
{ { NULL }, 1, 4, 0, 8,
|
|
{012000, 012010, 012020, 012030} }, /* GT40 */
|
|
{ { NULL }, 1, 2, 0, 8,
|
|
{010400} }, /* LPS11 */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* DQ11 */
|
|
{ { NULL }, 1, 2, 0, 8,
|
|
{012400} }, /* KW11W */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* DU11 */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* DUP11 */
|
|
{ { NULL }, 1, 3, 0, 8,
|
|
{015000, 015040, 015100, 015140, }}, /* DV11 */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* LK11A */
|
|
{ { "DMC0", "DMC1", "DMC2", "DMC3" },
|
|
1, 2, 8, 8 }, /* DMC11 */
|
|
{ { "DZ" }, 1, 2, 8, 8 }, /* DZ11 */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* KMC11 */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* LPP11 */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* VMV21 */
|
|
{ { NULL }, 1, 2, 16, 8 }, /* VMV31 */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* DWR70 */
|
|
{ { "RL", "RLB"}, 1, 1, 8, 4,
|
|
{014400}, {0160} }, /* RL11 */
|
|
{ { "TS", "TSB", "TSC", "TSD"},
|
|
1, 1, 0, 4, /* TS11 */
|
|
{012520, 012524, 012530, 012534},
|
|
{0224} },
|
|
{ { NULL }, 1, 2, 16, 8,
|
|
{010460} }, /* LPA11K */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* KW11C */
|
|
{ { NULL }, 1, 1, 8, 8 }, /* reserved */
|
|
{ { "RX", "RY" }, 1, 1, 8, 4,
|
|
{017170} , {0264} }, /* RX11/RX211 */
|
|
{ { NULL }, 1, 1, 8, 4 }, /* DR11W */
|
|
{ { NULL }, 1, 1, 8, 4,
|
|
{012410, 012410}, {0124} }, /* DR11B - fx CSRs,vec */
|
|
{ { "DMP" }, 1, 2, 8, 8 }, /* DMP11 */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* DPV11 */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* ISB11 */
|
|
{ { NULL }, 1, 2, 16, 8 }, /* DMV11 */
|
|
{ { "XU", "XUB" }, 1, 1, 8, 4,
|
|
{014510}, {0120} }, /* DEUNA */
|
|
{ { "XQ", "XQB" }, 1, -1, 0, 4,
|
|
{014440, 014460, 014520, 014540}, {0120} }, /* DEQNA */
|
|
{ { "RQ", "RQB", "RQC", "RQD" },
|
|
1, -1, 4, 4, /* RQDX3 */
|
|
{012150}, {0154} },
|
|
{ { NULL }, 1, 8, 32, 4 }, /* DMF32 */
|
|
{ { NULL }, 1, 3, 16, 8 }, /* KMS11 */
|
|
{ { NULL }, 1, 2, 0, 8,
|
|
{004200, 004240, 004300, 004340} }, /* PLC11 */
|
|
{ { NULL }, 1, 1, 16, 4 }, /* VS100 */
|
|
{ { "TQ", "TQB" }, 1, -1, 4, 4,
|
|
{014500}, {0260} }, /* TQK50 */
|
|
{ { NULL }, 1, 2, 16, 8 }, /* KMV11 */
|
|
{ { NULL }, 1, 2, 0, 8,
|
|
{004400, 004440, 004500, 004540} }, /* KTC32 */
|
|
{ { NULL }, 1, 2, 0, 8,
|
|
{004100} }, /* IEQ11 */
|
|
{ { "VH" }, 1, 2, 16, 8 }, /* DHU11/DHQ11 */
|
|
{ { NULL }, 1, 6, 32, 4 }, /* DMZ32 */
|
|
{ { NULL }, 1, 6, 32, 4 }, /* CP132 */
|
|
{ { "TC" }, 1, 1, 0, 0,
|
|
{017340}, {0214} }, /* TC11 */
|
|
{ { "TA" }, 1, 1, 0, 0,
|
|
{017500}, {0260} }, /* TA11 */
|
|
{ { NULL }, 1, 2, 64, 8,
|
|
{017200} }, /* QVSS - fx CSR */
|
|
{ { NULL }, 1, 1, 8, 4 }, /* VS31 */
|
|
{ { NULL }, 1, 1, 0, 4,
|
|
{016200} }, /* LNV11 - fx CSR */
|
|
{ { NULL }, 1, 1, 16, 4 }, /* LNV21/QPSS */
|
|
{ { NULL }, 1, 1, 8, 4,
|
|
{012570} }, /* QTA - fx CSR */
|
|
{ { NULL }, 1, 1, 8, 4 }, /* DSV11 */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* CSAM */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* ADV11C */
|
|
{ { NULL }, 1, 0, 8, 8,
|
|
{010440} }, /* AAV11/AAV11C */
|
|
{ { NULL }, 1, 2, 8, 8,
|
|
{016400}, {0140} }, /* AXV11C - fx CSR,vec */
|
|
{ { NULL }, 1, 2, 4, 8,
|
|
{010420} }, /* KWV11C - fx CSR */
|
|
{ { NULL }, 1, 2, 8, 8,
|
|
{016410} }, /* ADV11D - fx CSR */
|
|
{ { NULL }, 1, 2, 8, 8,
|
|
{016420} }, /* AAV11D - fx CSR */
|
|
{ { "QDSS" }, 1, 3, 0, 16,
|
|
{017400, 017402, 017404, 017406,
|
|
017410, 017412, 017414, 017416} }, /* VCB02 - QDSS - fx CSR */
|
|
{ { NULL }, 1, 16, 0, 4,
|
|
{004160, 004140, 004120} }, /* DRV11J - fx CSR */
|
|
{ { NULL }, 1, 2, 16, 8 }, /* DRQ3B */
|
|
{ { NULL }, 1, 1, 8, 4 }, /* VSV24 */
|
|
{ { NULL }, 1, 1, 8, 4 }, /* VSV21 */
|
|
{ { NULL }, 1, 1, 8, 4 }, /* IBQ01 */
|
|
{ { NULL }, 1, 1, 8, 8 }, /* IDV11A */
|
|
{ { NULL }, 1, 0, 8, 8 }, /* IDV11B */
|
|
{ { NULL }, 1, 0, 8, 8 }, /* IDV11C */
|
|
{ { NULL }, 1, 1, 8, 8 }, /* IDV11D */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* IAV11A */
|
|
{ { NULL }, 1, 0, 8, 8 }, /* IAV11B */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* MIRA */
|
|
{ { NULL }, 1, 2, 16, 8 }, /* IEQ11 */
|
|
{ { NULL }, 1, 2, 32, 8 }, /* ADQ32 */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* DTC04, DECvoice */
|
|
{ { NULL }, 1, 1, 32, 4 }, /* DESNA */
|
|
{ { NULL }, 1, 2, 4, 8 }, /* IGQ11 */
|
|
{ { NULL }, 1, 2, 32, 8 }, /* KMV1F */
|
|
{ { NULL }, 1, 1, 8, 4 }, /* DIV32 */
|
|
{ { NULL }, 1, 2, 4, 8 }, /* DTCN5, DECvoice */
|
|
{ { NULL }, 1, 2, 4, 8 }, /* DTC05, DECvoice */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* KWV32 (DSV11) */
|
|
{ { NULL }, 1, 1, 64, 4 }, /* QZA */
|
|
{ { NULL }, -1 } /* end table */
|
|
};
|
|
|
|
#if !defined(DEV_NEXUS)
|
|
#if defined(DEV_MBUS)
|
|
#define DEV_NEXUS DEV_MBUS
|
|
#else
|
|
#define DEV_NEXUS 0
|
|
#endif
|
|
#endif
|
|
t_stat auto_config (char *name, int32 nctrl)
|
|
{
|
|
uint32 csr = IOPAGEBASE + AUTO_CSRBASE;
|
|
uint32 vec = VEC_Q + AUTO_VECBASE;
|
|
AUTO_CON *autp;
|
|
DEVICE *dptr;
|
|
DIB *dibp;
|
|
uint32 j, vmask, amask;
|
|
|
|
if (autcon_enb == 0) /* enabled? */
|
|
return SCPE_OK;
|
|
if (name) { /* updating? */
|
|
if (nctrl < 0)
|
|
return SCPE_ARG;
|
|
for (autp = auto_tab; autp->numc >= 0; autp++) {
|
|
for (j = 0; (j < AUTO_MAXC) && autp->dnam[j]; j++) {
|
|
if (strcmp (name, autp->dnam[j]) == 0)
|
|
autp->numc = nctrl;
|
|
}
|
|
}
|
|
}
|
|
for (autp = auto_tab; autp->numc >= 0; autp++) { /* loop thru table */
|
|
if (autp->amod) { /* floating csr? */
|
|
amask = autp->amod - 1;
|
|
csr = (csr + amask) & ~amask; /* align csr */
|
|
}
|
|
for (j = 0; (j < AUTO_MAXC) && autp->dnam[j]; j++) {
|
|
if (autp->dnam[j] == NULL) /* no device? */
|
|
break;
|
|
dptr = find_dev (autp->dnam[j]); /* find ctrl */
|
|
if ((dptr == NULL) || /* enabled, not nexus? */
|
|
(dptr->flags & DEV_DIS) ||
|
|
(dptr->flags & DEV_NEXUS) )
|
|
continue;
|
|
dibp = (DIB *) dptr->ctxt; /* get DIB */
|
|
if (dibp == NULL) /* not there??? */
|
|
return SCPE_IERR;
|
|
if (autp->fixa[j]) /* fixed csr avail? */
|
|
dibp->ba = IOPAGEBASE + autp->fixa[j]; /* use it */
|
|
else { /* no fixed left */
|
|
dibp->ba = csr; /* set CSR */
|
|
csr += (autp->numc * autp->amod); /* next CSR */
|
|
} /* end else */
|
|
if (autp->numv) { /* vec needed? */
|
|
if (autp->fixv[j]) { /* fixed vec avail? */
|
|
if (autp->numv > 0)
|
|
dibp->vec = VEC_Q + autp->fixv[j]; /* use it */
|
|
}
|
|
else { /* no fixed left */
|
|
uint32 numv = abs (autp->numv); /* get num vec */
|
|
vmask = autp->vmod - 1;
|
|
vec = (vec + vmask) & ~vmask; /* align vector */
|
|
if (autp->numv > 0)
|
|
dibp->vec = vec; /* set vector */
|
|
vec += (autp->numc * numv * 4);
|
|
} /* end else */
|
|
} /* end vec needed */
|
|
} /* end for j */
|
|
if (autp->amod) /* flt CSR? gap */
|
|
csr = csr + 2;
|
|
} /* end for i */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
|
|
/* Set address floating */
|
|
|
|
t_stat set_addr_flt (UNIT *uptr, int32 val, char *cptr, void *desc)
|
|
{
|
|
DEVICE *dptr;
|
|
|
|
if (cptr != NULL)
|
|
return SCPE_ARG;
|
|
if (uptr == NULL)
|
|
return SCPE_IERR;
|
|
dptr = find_dev_from_unit (uptr);
|
|
if (dptr == NULL)
|
|
return SCPE_IERR;
|
|
return auto_config (NULL, 0); /* autoconfigure */
|
|
}
|
|
|