WARNING: V2.10 has reorganized and renamed some of the definition files for the PDP-10, PDP-11, and VAX. Be sure to delete all previous source files before you unpack the Zip archive, or unpack it into a new directory structure. WARNING: V2.10 has a new, more comprehensive save file format. Restoring save files from previous releases will cause 'invalid register' errors and loss of CPU option flags, device enable/ disable flags, unit online/offline flags, and unit writelock flags. WARNING: If you are using Visual Studio .NET through the IDE, be sure to turn off the /Wp64 flag in the project settings, or dozens of spurious errors will be generated. WARNING: Compiling Ethernet support under Windows requires extra steps; see the Ethernet readme file. Ethernet support is currently available only for Windows, Linux, NetBSD, and OpenBSD. 1. New Features 1.1 SCP and Libraries - The VT emulation package has been replaced by the capability to remote the console to a Telnet session. Telnet clients typically have more complete and robust VT100 emulation. - Simulated devices may now have statically allocated buffers, in addition to dynamically allocated buffers or disk-based data stores. - The DO command now takes substitutable arguments (max 9). In command files, %n represents substitutable argument n. - The initial command line is now interpreted as the command name and substitutable arguments for a DO command. This is backward compatible to prior versions. - The initial command line parses switches. -Q is interpreted as quiet mode; informational messages are suppressed. - The HELP command now takes an optional argument. HELP <cmd> types help on the specified command. - Hooks have been added for implementing GUI-based consoles, as well as simulator-specific command extensions. A few internal data structures and definitions have changed. - Two new routines (tmxr_open_master, tmxr_close_master) have been added to sim_tmxr.c. The calling sequence for sim_accept_conn has been changed in sim_sock.c. - The calling sequence for the VM boot routine has been modified to add an additional parameter. - SAVE now saves, and GET now restores, controller and unit flags. - Library sim_ether.c has been added for Ethernet support. 1.2 VAX - Non-volatile RAM (NVR) can behave either like a memory or like a disk-based peripheral. If unattached, it behaves like memory and is saved and restored by SAVE and RESTORE, respectively. If attached, its contents are loaded from disk by ATTACH and written back to disk at DETACH and EXIT. - SHOW <device> VECTOR displays the device's interrupt vector. A few devices allow the vector to be changed with SET <device> VECTOR=nnn. - SHOW CPU IOSPACE displays the I/O space address map. - The TK50 (TMSCP tape) has been added. - The DEQNA/DELQA (Qbus Ethernet controllers) have been added. - Autoconfiguration support has been added. - The paper tape reader has been removed from vax_stddev.c and now references a common implementation file, dec_pt.h. - Examine and deposit switches now work on all devices, not just the CPU. - Device address conflicts are not detected until simulation starts. 1.3 PDP-11 - SHOW <device> VECTOR displays the device's interrupt vector. Most devices allow the vector to be changed with SET <device> VECTOR=nnn. - SHOW CPU IOSPACE displays the I/O space address map. - The TK50 (TMSCP tape), RK611/RK06/RK07 (cartridge disk), RX211 (double density floppy), and KW11P programmable clock have been added. - The DEQNA/DELQA (Qbus Ethernet controllers) have been added. - Autoconfiguration support has been added. - The paper tape reader has been removed from pdp11_stddev.c and now references a common implementation file, dec_pt.h. - Device bootstraps now use the actual CSR specified by the SET ADDRESS command, rather than just the default CSR. Note that PDP-11 operating systems may NOT support booting with non-standard addresses. - Specifying more than 256KB of memory, or changing the bus configuration, causes all peripherals that are not compatible with the current bus configuration to be disabled. - Device address conflicts are not detected until simulation starts. 1.4 PDP-10 - SHOW <device> VECTOR displays the device's interrupt vector. A few devices allow the vector to be changed with SET <device> VECTOR=nnn. - SHOW CPU IOSPACE displays the I/O space address map. - The RX211 (double density floppy) has been added; it is off by default. - The paper tape now references a common implementation file, dec_pt.h. - Device address conflicts are not detected until simulation starts. 1.5 PDP-1 - DECtape (then known as MicroTape) support has been added. - The line printer and DECtape can be disabled and enabled. 1.6 PDP-8 - The RX28 (double density floppy) has been added as an option to the existing RX8E controller. - SHOW <device> DEVNO displays the device's device number. Most devices allow the device number to be changed with SET <device> DEVNO=nnn. - Device number conflicts are not detected until simulation starts. 1.7 IBM 1620 - The IBM 1620 simulator has been released. 1.8 AltairZ80 - A hard drive has been added for increased storage. - Several bugs have been fixed. 1.9 HP 2100 - The 12845A has been added and made the default line printer (LPT). The 12653A has been renamed LPS and is off by default. It also supports the diagnostic functions needed to run the DCPC and DMS diagnostics. - The 12557A/13210A disk defaults to the 13210A (7900/7901). - The 12559A magtape is off by default. - New CPU options (EAU/NOEAU) enable/disable the extended arithmetic instructions for the 2116. These instructions are standard on the 2100 and 21MX. - New CPU options (MPR/NOMPR) enable/disable memory protect for the 2100 and 21MX. - New CPU options (DMS/NODMS) enable/disable the dynamic mapping instructions for the 21MX. - The 12539 timebase generator autocalibrates. 1.10 Simulated Magtapes - Simulated magtapes recognize end of file and the marker 0xFFFFFFFF as end of medium. Only the TMSCP tape simulator can generate an end of medium marker. - The error handling in simulated magtapes was overhauled to be consistent through all simulators. 1.11 Simulated DECtapes - Added support for RT11 image file format (256 x 16b) to DECtapes. 2. Release Notes 2.1 Bugs Fixed - TS11/TSV05 was not simulating the XS0_MOT bit, causing failures under VMS. In addition, two of the CTL options were coded interchanged. - IBM 1401 tape was not setting a word mark under group mark for load mode reads. This caused the diagnostics to crash. - SCP bugs in ssh_break and set_logon were fixed (found by Dave Hittner). - Numerous bugs in the HP 2100 extended arithmetic, floating point, 21MX, DMS, and IOP instructions were fixed. Bugs were also fixed in the memory protect and DMS functions. The moving head disks (DP, DQ) were revised to simulate the hardware more accurately. Missing functions in DQ (address skip, read address) were added. 2.2 HP 2100 Debugging - The HP 2100 CPU nows runs all of the CPU diagnostics. - The peripherals run most of the peripheral diagnostics. There is still a problem in overlapped seek operation on the disks. See the file hp2100_diag.txt for details. 3. In Progress These simulators are not finished and are available in a separate Zip archive distribution. - Interdata 16b/32b: coded, partially tested. See the file id_diag.txt for details. - SDS 940: coded, partially tested.
580 lines
19 KiB
C
580 lines
19 KiB
C
/* gri_sys.c: GRI-909 simulator interface
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Copyright (c) 2001-2002, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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18-Oct-02 RMS Fixed bug in symbolic decode (found by Hans Pufal)
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*/
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#include "gri_defs.h"
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#include <ctype.h>
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extern DEVICE cpu_dev;
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extern UNIT cpu_unit;
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extern DEVICE tti_dev, tto_dev;
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extern DEVICE hsr_dev, hsp_dev;
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extern DEVICE rtc_dev;
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extern REG cpu_reg[];
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extern uint16 M[];
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extern int32 sim_switches;
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/* SCP data structures and interface routines
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sim_name simulator name string
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sim_PC pointer to saved PC register descriptor
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sim_emax maximum number of words for examine/deposit
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sim_devices array of pointers to simulated devices
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sim_stop_messages array of pointers to stop messages
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sim_load binary loader
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*/
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char sim_name[] = "GRI-909";
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REG *sim_PC = &cpu_reg[0];
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int32 sim_emax = 2;
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DEVICE *sim_devices[] = {
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&cpu_dev,
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&tti_dev,
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&tto_dev,
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&hsr_dev,
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&hsp_dev,
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&rtc_dev,
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NULL };
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const char *sim_stop_messages[] = {
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"Unknown error",
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"Unimplemented unit",
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"HALT instruction",
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"Breakpoint",
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"Invalid interrupt request" };
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/* Binary loader
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Bootstrap loader format consists of blocks separated by zeroes. Each
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word in the block has three frames: a control frame (ignored) and two
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data frames. The user must specify the load address. Switch -c means
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continue and load all blocks until end of tape.
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*/
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t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
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{
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int32 c, org;
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t_stat r;
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char gbuf[CBUFSIZE];
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if (*cptr != 0) { /* more input? */
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cptr = get_glyph (cptr, gbuf, 0); /* get origin */
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org = get_uint (gbuf, 8, AMASK, &r);
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if (r != SCPE_OK) return r;
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if (*cptr != 0) return SCPE_ARG; } /* no more */
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else org = 0200; /* default 200 */
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for (;;) { /* until EOF */
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while ((c = getc (fileref)) == 0) ; /* skip starting 0's */
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if (c == EOF) break; /* EOF? done */
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for ( ; c != 0; ) { /* loop until ctl = 0 */
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/* ign ctrl frame */
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if ((c = getc (fileref)) == EOF) /* get high byte */
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return SCPE_FMT; /* EOF is error */
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if (!MEM_ADDR_OK (org)) return SCPE_NXM;
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M[org] = ((c & 0377) << 8); /* store high */
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if ((c = getc (fileref)) == EOF) /* get low byte */
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return SCPE_FMT; /* EOF is error */
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M[org] = M[org] | (c & 0377); /* store low */
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org = org + 1; /* incr origin */
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if ((c = getc (fileref)) == EOF) /* get ctrl frame */
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return SCPE_OK; /* EOF is ok */
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} /* end block for */
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if (!(sim_switches & SWMASK ('C'))) return SCPE_OK;
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} /* end tape for */
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return SCPE_OK;
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}
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/* Symbol tables */
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#define F_V_FL 16
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#define F_M_FL 017
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#define F_V_FO 000 /* function out */
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#define F_V_FOI 001 /* FO, impl reg */
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#define F_V_SF 002 /* skip function */
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#define F_V_SFI 003 /* SF, impl reg */
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#define F_V_RR 004 /* reg reg */
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#define F_V_ZR 005 /* zero reg */
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#define F_V_RS 006 /* reg self */
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#define F_V_JC 010 /* jump cond */
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#define F_V_JU 011 /* jump uncond */
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#define F_V_RM 012 /* reg mem */
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#define F_V_ZM 013 /* zero mem */
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#define F_V_MR 014 /* mem reg */
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#define F_V_MS 015 /* mem self */
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#define F_2WD 010 /* 2 words */
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#define F_FO (F_V_FO << F_V_FL)
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#define F_FOI (F_V_FOI << F_V_FL)
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#define F_SF (F_V_SF << F_V_FL)
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#define F_SFI (F_V_SFI << F_V_FL)
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#define F_RR (F_V_RR << F_V_FL)
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#define F_ZR (F_V_ZR << F_V_FL)
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#define F_RS (F_V_RS << F_V_FL)
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#define F_JC (F_V_JC << F_V_FL)
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#define F_JU (F_V_JU << F_V_FL)
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#define F_RM (F_V_RM << F_V_FL)
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#define F_ZM (F_V_ZM << F_V_FL)
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#define F_MR (F_V_MR << F_V_FL)
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#define F_MS (F_V_MS << F_V_FL)
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struct fnc_op {
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uint32 inst; /* instr prot */
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uint32 imask; /* instr mask */
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uint32 oper; /* operator */
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uint32 omask; }; /* oper mask */
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static const int32 masks[] = {
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0176000, 0176077, 0000077, 0176077,
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0000300, 0176300, 0000300, 0177777,
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0000077, 0177777, 0000377, 0176377,
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0176300, 0176377 };
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/* Instruction mnemonics
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Order is critical, as some instructions are more precise versions of
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others. For example, JU must precede JC, otherwise, JU will be decoded
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as JC 0,ETZ,dst. There are some ambiguities, eg, what is 02-xxxx-06?
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Priority is as follows:
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FO (02-xxxx-rr)
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SF (rr-xxxx-02)
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MR (06-xxxx-rr)
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RM (rr-xxxx-06)
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JC (rr-xxxx-03)
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RR
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*/
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static const char *opcode[] = {
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"FOM", "FOA", "FOI", "FO", /* FOx before FO */
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"SFM", "SFA", "SFI", "SF", /* SFx before SF */
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"ZM", "ZMD", "ZMI", "ZMID", /* ZM before RM */
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"MS", "MSD", "MSI", "MSID",
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"RM", "RMD", "RMI", "RMID",
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"MR", "MRD", "MRI", "MRID",
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"JO", "JOD", "JN", "JND", /* JU before JC */
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"JU", "JUD", "JC", "JCD",
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"ZR", "ZRC", "RR", "RRC", /* ZR before RR */
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"RS", "RSC",
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NULL };
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static const uint32 opc_val[] = {
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0004000+F_FOI, 0004013+F_FOI, 0004004+F_FOI, 0004000+F_FO,
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0000002+F_SFI, 0026002+F_SFI, 0010002+F_SFI, 0000002+F_SF,
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0000006+F_ZM, 0000106+F_ZM, 0000206+F_ZM, 0000306+F_ZM,
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0014006+F_MS, 0014106+F_MS, 0014206+F_MS, 0014306+F_MS,
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0000006+F_RM, 0000106+F_RM, 0000206+F_RM, 0000306+F_RM,
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0014000+F_MR, 0014100+F_MR, 0014200+F_MR, 0014300+F_MR,
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0037003+F_JU, 0037103+F_JU, 0037203+F_JU, 0037303+F_JU,
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0000403+F_JU, 0000503+F_JU, 0000003+F_JC, 0000103+F_JC,
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0000000+F_ZR, 0000200+F_ZR, 0000000+F_RR, 0000200+F_RR,
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0000000+F_RS, 0000200+F_RS };
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/* Unit mnemonics. All 64 units are decoded, most just to octal integers */
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static const char *unsrc[64] = {
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"0", "IR", "2", "TRP", "ISR", "MA", "MB", "SC", /* 00 - 07 */
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"SWR", "AX", "AY", "AO", "14", "15", "16", "MSR", /* 10 - 17 */
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"20", "21", "22", "23", "BSW", "BPK", "26", "27", /* 20 - 27 */
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"GR1", "GR2", "GR3", "GR4", "GR5", "GR6", "36", "37", /* 30 - 37 */
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"40", "41", "42", "43", "44", "45", "46", "47",
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"50", "51", "52", "53", "54", "55", "56", "57",
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"60", "61", "62", "63", "64", "65", "66", "67",
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"70", "71", "72", "73", "74", "RTC", "HSR", "TTI" }; /* 70 - 77 */
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static const char *undst[64] = {
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"0", "IR", "2", "TRP", "ISR", "5", "MB", "SC", /* 00 - 07 */
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"SWR", "AX", "AY", "13", "EAO", "15", "16", "MSR", /* 10 - 17 */
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"20", "21", "22", "23", "BSW", "BPK", "26", "27", /* 20 - 27 */
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"GR1", "GR2", "GR3", "GR4", "GR5", "GR6", "36", "37", /* 30 - 37 */
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"40", "41", "42", "43", "44", "45", "46", "47",
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"50", "51", "52", "53", "54", "55", "56", "57",
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"60", "61", "62", "63", "64", "65", "66", "67",
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"70", "71", "72", "73", "74", "RTC", "HSP", "TTO" }; /* 70 - 77 */
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/* Operators */
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static const char *opname[4] = {
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NULL, "P1", "L1", "R1" };
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/* Conditions */
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static const char *cdname[8] = {
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"NEVER", "ALWAYS", "ETZ", "NEZ", "LTZ", "GEZ", "LEZ", "GTZ" };
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/* Function out/sense function */
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static const char *fname[] = {
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"NOT", /* any SF */
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"POK", "LNK", "BOV", /* SFM */
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"SOV", "AOV", /* SFA */
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"IRDY", "ORDY", /* any SF */
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"CLL", "STL", "CML", "HLT", /* FOM */
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"ICF", "ICO", /* FOI */
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"ADD", "AND", "XOR", "OR", /* FOA */
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"INP", "IRDY", "ORDY", "STRT", /* any FO */
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NULL };
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static const struct fnc_op fop[] = {
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{ 0000002, 0000077, 001, 001 }, /* NOT */
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{ 0000002, 0176077, 010, 010 }, /* POK */
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{ 0000002, 0176077, 004, 004 }, /* LNK */
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{ 0000002, 0176077, 002, 002 }, /* BOV */
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{ 0026002, 0176077, 004, 004 }, /* SOV */
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{ 0026002, 0176077, 002, 002 }, /* AOV */
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{ 0000002, 0000077, 010, 010 }, /* IRDY */
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{ 0000002, 0000077, 002, 002 }, /* ORDY */
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{ 0004000, 0176077, 001, 003 }, /* CLL */
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{ 0004000, 0176077, 002, 003 }, /* STL */
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{ 0004000, 0176077, 003, 003 }, /* CML */
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{ 0004000, 0176077, 004, 004 }, /* HLT */
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{ 0004004, 0176077, 001, 001 }, /* ICF */
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{ 0004004, 0176077, 002, 002 }, /* ICO */
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{ 0004013, 0176077, 000, 014 }, /* ADD */
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{ 0004013, 0176077, 004, 014 }, /* AND */
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{ 0004013, 0176077, 010, 014 }, /* XOR */
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{ 0004013, 0176077, 014, 014 }, /* OR */
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{ 0004000, 0176000, 011, 011 }, /* INP */
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{ 0004000, 0176000, 010, 010 }, /* IRDY */
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{ 0004000, 0176000, 002, 002 }, /* ORDY */
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{ 0004000, 0176000, 001, 001 } }; /* STRT */
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/* Print opcode field for FO, SF */
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void fprint_op (FILE *of, uint32 inst, uint32 op)
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{
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int32 i, nfirst;
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for (i = nfirst = 0; fname[i] != NULL; i++) {
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if (((inst & fop[i].imask) == fop[i].inst) &&
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((op & fop[i].omask) == fop[i].oper)) {
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op = op & ~fop[i].omask;
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if (nfirst) fputc (' ', of);
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nfirst = 1;
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fprintf (of, "%s", fname[i]); }
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}
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if (op) fprintf (of, " %o", op);
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return;
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}
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/* Symbolic decode
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Inputs:
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*of = output stream
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addr = current PC
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*val = pointer to data
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*uptr = pointer to unit
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sw = switches
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Outputs:
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return = status code
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*/
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#define FMTASC(x) ((x) < 040)? "<%03o>": "%c", (x)
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t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
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UNIT *uptr, int32 sw)
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{
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int32 i, j;
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uint32 inst, src, dst, op, bop;
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inst = val[0];
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if (sw & SWMASK ('A')) { /* ASCII? */
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if (inst > 0377) return SCPE_ARG;
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fprintf (of, FMTASC (inst & 0177));
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return SCPE_OK; }
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if (sw & SWMASK ('C')) { /* characters? */
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fprintf (of, FMTASC ((inst >> 8) & 0177));
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fprintf (of, FMTASC (inst & 0177));
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return SCPE_OK; }
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if (!(sw & SWMASK ('M'))) return SCPE_ARG;
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/* Instruction decode */
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inst = val[0];
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src = I_GETSRC (inst); /* get fields */
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op = I_GETOP (inst);
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dst = I_GETDST (inst);
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bop = op >> 2; /* bus op */
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for (i = 0; opcode[i] != NULL; i++) { /* loop thru ops */
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j = (opc_val[i] >> F_V_FL) & F_M_FL; /* get class */
|
||
if ((opc_val[i] & DMASK) == (inst & masks[j])) { /* match? */
|
||
|
||
switch (j) { /* case on class */
|
||
case F_V_FO: /* func out */
|
||
fprintf (of, "%s ", opcode[i]);
|
||
fprint_op (of, inst, op);
|
||
fprintf (of, ",%s", undst[dst]);
|
||
break;
|
||
case F_V_FOI: /* func out impl */
|
||
fprintf (of, "%s ", opcode[i]);
|
||
fprint_op (of, inst, op);
|
||
break;
|
||
case F_V_SF: /* skip func */
|
||
fprintf (of, "%s %s,", opcode[i], unsrc[src]);
|
||
fprint_op (of, inst, op);
|
||
break;
|
||
case F_V_SFI: /* skip func impl */
|
||
fprintf (of, "%s ", opcode[i]);
|
||
fprint_op (of, inst, op);
|
||
break;
|
||
case F_V_RR: /* reg reg */
|
||
if (strcmp (unsrc[src], undst[dst]) == 0) {
|
||
if (bop) fprintf (of, "%s %s,%s", opcode[i + 2],
|
||
unsrc[src], opname[bop]);
|
||
else fprintf (of, "%s %s", opcode[i + 2], unsrc[src]); }
|
||
else { if (bop) fprintf (of, "%s %s,%s,%s", opcode[i],
|
||
unsrc[src], opname[bop], undst[dst]);
|
||
else fprintf (of, "%s %s,%s", opcode[i],
|
||
unsrc[src], undst[dst]); }
|
||
break;
|
||
case F_V_ZR: /* zero reg */
|
||
if (bop) fprintf (of, "%s %s,%s", opcode[i],
|
||
opname[bop], undst[dst]);
|
||
else fprintf (of, "%s %s", opcode[i], undst[dst]);
|
||
break;
|
||
case F_V_JC: /* jump cond */
|
||
fprintf (of, "%s %s,%s,%o", opcode[i],
|
||
unsrc[src], cdname[op >> 1], val[1]);
|
||
break;
|
||
case F_V_JU: /* jump uncond */
|
||
fprintf (of, "%s %o", opcode[i], val[1]);
|
||
break;
|
||
case F_V_RM: /* reg mem */
|
||
if (bop) fprintf (of, "%s %s,%s,%o", opcode[i],
|
||
unsrc[src], opname[bop], val[1]);
|
||
else fprintf (of, "%s %s,%o", opcode[i], unsrc[src], val[1]);
|
||
break;
|
||
case F_V_ZM: /* zero mem */
|
||
if (bop) fprintf (of, "%s %s,%o", opcode[i],
|
||
opname[bop], val[1]);
|
||
else fprintf (of, "%s %o", opcode[i], val[1]);
|
||
break;
|
||
case F_V_MR: /* mem reg */
|
||
if (bop) fprintf (of, "%s %o,%s,%s", opcode[i],
|
||
val[1], opname[bop], undst[dst]);
|
||
else fprintf (of, "%s %o,%s", opcode[i], val[1], undst[dst]);
|
||
break;
|
||
case F_V_MS: /* mem self */
|
||
if (bop) fprintf (of, "%s %o,%s", opcode[i],
|
||
val[1], opname[bop]);
|
||
else fprintf (of, "%s %o", opcode[i], val[1]);
|
||
break; } /* end case */
|
||
return (j >= F_2WD)? -1: SCPE_OK; } /* end if */
|
||
} /* end for */
|
||
return SCPE_ARG;
|
||
}
|
||
|
||
/* Field parse routines
|
||
|
||
get_fnc get function field
|
||
get_ma get memory address
|
||
get_sd get source or dest
|
||
get_op get optional bus operator
|
||
*/
|
||
|
||
char *get_fnc (char *cptr, t_value *val)
|
||
{
|
||
char gbuf[CBUFSIZE];
|
||
int32 i;
|
||
t_value d;
|
||
t_stat r;
|
||
uint32 inst = val[0];
|
||
uint32 fncv = 0, fncm = 0;
|
||
|
||
while (*cptr) {
|
||
cptr = get_glyph (cptr, gbuf, 0); /* get glyph */
|
||
d = get_uint (gbuf, 8, 017, &r); /* octal? */
|
||
if (r == SCPE_OK) { /* ok? */
|
||
if (d & fncm) return NULL; /* already filled? */
|
||
fncv = fncv | d; /* save */
|
||
fncm = fncm | d; } /* field filled */
|
||
else { /* symbol? */
|
||
for (i = 0; fname[i] != NULL; i++) { /* search table */
|
||
if ((strcmp (gbuf, fname[i]) == 0) && /* match for inst? */
|
||
((inst & fop[i].imask) == fop[i].inst)) {
|
||
if (fop[i].oper & fncm) return NULL; /* already filled? */
|
||
fncm = fncm | fop[i].omask;
|
||
fncv = fncv | fop[i].oper;
|
||
break; } }
|
||
if (fname[i] == NULL) return NULL; } /* end else */
|
||
} /* end while */
|
||
val[0] = val[0] | (fncv << I_V_OP); /* store fnc */
|
||
return cptr;
|
||
}
|
||
|
||
char *get_ma (char *cptr, t_value *val, char term)
|
||
{
|
||
char gbuf[CBUFSIZE];
|
||
t_value d;
|
||
t_stat r;
|
||
|
||
cptr = get_glyph (cptr, gbuf, term); /* get glyph */
|
||
d = get_uint (gbuf, 8, DMASK, &r); /* [0,177777] */
|
||
if (r != SCPE_OK) return NULL;
|
||
val[1] = d; /* second wd */
|
||
return cptr;
|
||
}
|
||
|
||
char *get_sd (char *cptr, t_value *val, char term, t_bool src)
|
||
{
|
||
char gbuf[CBUFSIZE];
|
||
int32 d;
|
||
t_stat r;
|
||
|
||
cptr = get_glyph (cptr, gbuf, term); /* get glyph */
|
||
for (d = 0; d < 64; d++) { /* symbol match? */
|
||
if ((strcmp (gbuf, unsrc[d]) == 0) ||
|
||
(strcmp (gbuf, undst[d]) == 0)) break; }
|
||
if (d >= 64) { /* no, [0,63]? */
|
||
d = get_uint (gbuf, 8, 077, &r);
|
||
if (r != SCPE_OK) return NULL; }
|
||
val[0] = val[0] | (d << (src? I_V_SRC: I_V_DST)); /* or to inst */
|
||
return cptr;
|
||
}
|
||
|
||
char *get_op (char *cptr, t_value *val, char term)
|
||
{
|
||
char gbuf[CBUFSIZE], *tptr;
|
||
int32 i;
|
||
|
||
tptr = get_glyph (cptr, gbuf, term); /* get glyph */
|
||
for (i = 1; i < 4; i++) { /* symbol match? */
|
||
if (strcmp (gbuf, opname[i]) == 0) {
|
||
val[0] = val[0] | (i << (I_V_OP + 2)); /* or to inst */
|
||
return tptr; } }
|
||
return cptr; /* original ptr */
|
||
}
|
||
|
||
/* Symbolic input
|
||
|
||
Inputs:
|
||
*cptr = pointer to input string
|
||
addr = current PC
|
||
*uptr = pointer to unit
|
||
*val = pointer to output values
|
||
sw = switches
|
||
Outputs:
|
||
status = error status
|
||
*/
|
||
|
||
t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
|
||
{
|
||
int32 i, j, k;
|
||
char *tptr, gbuf[CBUFSIZE];
|
||
|
||
while (isspace (*cptr)) cptr++; /* absorb spaces */
|
||
if ((sw & SWMASK ('A')) || ((*cptr == '\'') && cptr++)) { /* ASCII char? */
|
||
if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */
|
||
val[0] = (t_value) cptr[0] & 0177;
|
||
return SCPE_OK; }
|
||
if ((sw & SWMASK ('C')) || ((*cptr == '"') && cptr++)) { /* char string? */
|
||
if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */
|
||
val[0] = (((t_value) cptr[0] & 0177) << 8) |
|
||
((t_value) cptr[1] & 0177);
|
||
return SCPE_OK; }
|
||
|
||
/* Instruction parse */
|
||
|
||
cptr = get_glyph (cptr, gbuf, 0); /* get opcode */
|
||
for (i = 0; (opcode[i] != NULL) && (strcmp (opcode[i], gbuf) != 0) ; i++) ;
|
||
if (opcode[i] == NULL) return SCPE_ARG;
|
||
val[0] = opc_val[i] & DMASK; /* get value */
|
||
j = (opc_val[i] >> F_V_FL) & F_M_FL; /* get class */
|
||
|
||
switch (j) { /* case on class */
|
||
case F_V_FO: /* func out */
|
||
tptr = strchr (cptr, ','); /* find dst */
|
||
if (!tptr) return SCPE_ARG; /* none? */
|
||
*tptr = 0; /* split fields */
|
||
cptr = get_fnc (cptr, val); /* fo # */
|
||
if (!cptr) return SCPE_ARG;
|
||
cptr = get_sd (tptr + 1, val, 0, FALSE); /* dst */
|
||
break;
|
||
case F_V_FOI: /* func out impl */
|
||
cptr = get_fnc (cptr, val); /* fo # */
|
||
break;
|
||
case F_V_SF: /* skip func */
|
||
cptr = get_sd (cptr, val, ',', TRUE); /* src */
|
||
if (!cptr) return SCPE_ARG;
|
||
case F_V_SFI: /* skip func impl */
|
||
cptr = get_fnc (cptr, val); /* fo # */
|
||
break;
|
||
case F_V_RR: /* reg-reg */
|
||
cptr = get_sd (cptr, val, ',', TRUE); /* src */
|
||
if (!cptr) return SCPE_ARG;
|
||
cptr = get_op (cptr, val, ','); /* op */
|
||
if (!cptr) return SCPE_ARG;
|
||
cptr = get_sd (cptr, val, 0, FALSE); /* dst */
|
||
break;
|
||
case F_V_ZR: /* zero-reg */
|
||
cptr = get_op (cptr, val, ','); /* op */
|
||
if (!cptr) return SCPE_ARG;
|
||
cptr = get_sd (cptr, val, 0, FALSE); /* dst */
|
||
break;
|
||
case F_V_RS: /* reg self */
|
||
cptr = get_sd (cptr, val, ',', TRUE); /* src */
|
||
if (!cptr) return SCPE_ARG;
|
||
val[0] = val[0] | I_GETSRC (val[0]); /* duplicate */
|
||
cptr = get_op (cptr, val, 0); /* op */
|
||
break;
|
||
case F_V_JC: /* jump cond */
|
||
cptr = get_sd (cptr, val, ',', TRUE); /* src */
|
||
if (!cptr) return SCPE_ARG;
|
||
cptr = get_glyph (cptr, gbuf, ','); /* cond */
|
||
for (k = 0; k < 8; k++) { /* symbol? */
|
||
if (strcmp (gbuf, cdname[k]) == 0) break; }
|
||
if (k >= 8) return SCPE_ARG;
|
||
val[0] = val[0] | (k << (I_V_OP + 1)); /* or to inst */
|
||
case F_V_JU: /* jump uncond */
|
||
cptr = get_ma (cptr, val, 0); /* addr */
|
||
break;
|
||
case F_V_RM: /* reg mem */
|
||
cptr = get_sd (cptr, val, ',', TRUE); /* src */
|
||
if (!cptr) return SCPE_ARG;
|
||
case F_V_ZM: /* zero mem */
|
||
cptr = get_op (cptr, val, ','); /* op */
|
||
if (!cptr) return SCPE_ARG;
|
||
cptr = get_ma (cptr, val, 0); /* addr */
|
||
break;
|
||
case F_V_MR: /* mem reg */
|
||
cptr = get_ma (cptr, val, ','); /* addr */
|
||
if (!cptr) return SCPE_ARG;
|
||
cptr = get_op (cptr, val, ','); /* op */
|
||
if (!cptr) return SCPE_ARG;
|
||
cptr = get_sd (cptr, val, 0, FALSE); /* dst */
|
||
break;
|
||
case F_V_MS: /* mem self */
|
||
cptr = get_ma (cptr, val, ','); /* addr */
|
||
if (!cptr) return SCPE_ARG;
|
||
cptr = get_op (cptr, val, 0); /* op */
|
||
break; }
|
||
if (!cptr || (*cptr != 0)) return SCPE_ARG; /* junk at end? */
|
||
return (j >= F_2WD)? -1: SCPE_OK;
|
||
}
|