simh-testsetgenerator/HP2100/hp2100_fp.c
Bob Supnik 2c2dd5ea33 Notes For V2.10-0
WARNING: V2.10 has reorganized and renamed some of the definition
files for the PDP-10, PDP-11, and VAX.  Be sure to delete all
previous source files before you unpack the Zip archive, or
unpack it into a new directory structure.

WARNING: V2.10 has a new, more comprehensive save file format.
Restoring save files from previous releases will cause 'invalid
register' errors and loss of CPU option flags, device enable/
disable flags, unit online/offline flags, and unit writelock
flags.

WARNING: If you are using Visual Studio .NET through the IDE,
be sure to turn off the /Wp64 flag in the project settings, or
dozens of spurious errors will be generated.

WARNING: Compiling Ethernet support under Windows requires
extra steps; see the Ethernet readme file.  Ethernet support is
currently available only for Windows, Linux, NetBSD, and OpenBSD.

1. New Features

1.1 SCP and Libraries

- The VT emulation package has been replaced by the capability
  to remote the console to a Telnet session.  Telnet clients
  typically have more complete and robust VT100 emulation.
- Simulated devices may now have statically allocated buffers,
  in addition to dynamically allocated buffers or disk-based
  data stores.
- The DO command now takes substitutable arguments (max 9).
  In command files, %n represents substitutable argument n.
- The initial command line is now interpreted as the command
  name and substitutable arguments for a DO command.  This is
  backward compatible to prior versions.
- The initial command line parses switches.  -Q is interpreted
  as quiet mode; informational messages are suppressed.
- The HELP command now takes an optional argument.  HELP <cmd>
  types help on the specified command.
- Hooks have been added for implementing GUI-based consoles,
  as well as simulator-specific command extensions.  A few
  internal data structures and definitions have changed.
- Two new routines (tmxr_open_master, tmxr_close_master) have
  been added to sim_tmxr.c.  The calling sequence for
  sim_accept_conn has been changed in sim_sock.c.
- The calling sequence for the VM boot routine has been modified
  to add an additional parameter.
- SAVE now saves, and GET now restores, controller and unit flags.
- Library sim_ether.c has been added for Ethernet support.

1.2 VAX

- Non-volatile RAM (NVR) can behave either like a memory or like
  a disk-based peripheral.  If unattached, it behaves like memory
  and is saved and restored by SAVE and RESTORE, respectively.
  If attached, its contents are loaded from disk by ATTACH and
  written back to disk at DETACH and EXIT.
- SHOW <device> VECTOR displays the device's interrupt vector.
  A few devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The TK50 (TMSCP tape) has been added.
- The DEQNA/DELQA (Qbus Ethernet controllers) have been added.
- Autoconfiguration support has been added.
- The paper tape reader has been removed from vax_stddev.c and
  now references a common implementation file, dec_pt.h.
- Examine and deposit switches now work on all devices, not just
  the CPU.
- Device address conflicts are not detected until simulation starts.

1.3 PDP-11

- SHOW <device> VECTOR displays the device's interrupt vector.
  Most devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The TK50 (TMSCP tape), RK611/RK06/RK07 (cartridge disk),
  RX211 (double density floppy), and KW11P programmable clock
  have been added.
- The DEQNA/DELQA (Qbus Ethernet controllers) have been added.
- Autoconfiguration support has been added.
- The paper tape reader has been removed from pdp11_stddev.c and
  now references a common implementation file, dec_pt.h.
- Device bootstraps now use the actual CSR specified by the
  SET ADDRESS command, rather than just the default CSR.  Note
  that PDP-11 operating systems may NOT support booting with
  non-standard addresses.
- Specifying more than 256KB of memory, or changing the bus
  configuration, causes all peripherals that are not compatible
  with the current bus configuration to be disabled.
- Device address conflicts are not detected until simulation starts.

1.4 PDP-10

- SHOW <device> VECTOR displays the device's interrupt vector.
  A few devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The RX211 (double density floppy) has been added; it is off
  by default.
- The paper tape now references a common implementation file,
  dec_pt.h.
- Device address conflicts are not detected until simulation starts.

1.5 PDP-1

- DECtape (then known as MicroTape) support has been added.
- The line printer and DECtape can be disabled and enabled.

1.6 PDP-8

- The RX28 (double density floppy) has been added as an option to
  the existing RX8E controller.
- SHOW <device> DEVNO displays the device's device number.  Most
  devices allow the device number to be changed with SET <device>
  DEVNO=nnn.
- Device number conflicts are not detected until simulation starts.

1.7 IBM 1620

- The IBM 1620 simulator has been released.

1.8 AltairZ80

- A hard drive has been added for increased storage.
- Several bugs have been fixed.

1.9 HP 2100

- The 12845A has been added and made the default line printer (LPT).
  The 12653A has been renamed LPS and is off by default.  It also
  supports the diagnostic functions needed to run the DCPC and DMS
  diagnostics.
- The 12557A/13210A disk defaults to the 13210A (7900/7901).
- The 12559A magtape is off by default.
- New CPU options (EAU/NOEAU) enable/disable the extended arithmetic
  instructions for the 2116.  These instructions are standard on
  the 2100 and 21MX.
- New CPU options (MPR/NOMPR) enable/disable memory protect for the
  2100 and 21MX.
- New CPU options (DMS/NODMS) enable/disable the dynamic mapping
  instructions for the 21MX.
- The 12539 timebase generator autocalibrates.

1.10 Simulated Magtapes

- Simulated magtapes recognize end of file and the marker
  0xFFFFFFFF as end of medium.  Only the TMSCP tape simulator
  can generate an end of medium marker.
- The error handling in simulated magtapes was overhauled to be
  consistent through all simulators.

1.11 Simulated DECtapes

- Added support for RT11 image file format (256 x 16b) to DECtapes.

2. Release Notes

2.1 Bugs Fixed

- TS11/TSV05 was not simulating the XS0_MOT bit, causing failures
  under VMS.  In addition, two of the CTL options were coded
  interchanged.
- IBM 1401 tape was not setting a word mark under group mark for
  load mode reads.  This caused the diagnostics to crash.
- SCP bugs in ssh_break and set_logon were fixed (found by Dave
  Hittner).
- Numerous bugs in the HP 2100 extended arithmetic, floating point,
  21MX, DMS, and IOP instructions were fixed.  Bugs were also fixed
  in the memory protect and DMS functions.  The moving head disks
  (DP, DQ) were revised to simulate the hardware more accurately.
  Missing functions in DQ (address skip, read address) were added.

2.2 HP 2100 Debugging

- The HP 2100 CPU nows runs all of the CPU diagnostics.
- The peripherals run most of the peripheral diagnostics.  There
  is still a problem in overlapped seek operation on the disks.
  See the file hp2100_diag.txt for details.

3. In Progress

These simulators are not finished and are available in a separate
Zip archive distribution.

- Interdata 16b/32b: coded, partially tested.  See the file
  id_diag.txt for details.
- SDS 940: coded, partially tested.
2011-04-15 08:33:49 -07:00

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/* hp2100_fp.c: HP 2100 floating point instructions
Copyright (c) 2002, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
21-Oct-02 RMS Recoded for compatibility with 21MX microcode algorithms
The HP2100 uses a unique binary floating point format:
15 14 0
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|S | fraction high | : A
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| fraction low | exponent |XS| : A + 1
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
15 8 7 1 0
where S = 0 for plus fraction, 1 for minus fraction
fraction = s.bbbbb..., 24 binary digits
exponent = 2**+/-n
XS = 0 for plus exponent, 1 for minus exponent
Numbers can be normalized or unnormalized but are always normalized
when loaded.
Unpacked floating point numbers are stored in structure ufp
exp = exponent, 2's complement
h'l = fraction, 2's comp, left justified
This routine tries to reproduce the algorithms of the 2100/21MX
microcode in order to achieve 'bug-for-bug' compatibility. In
particular,
- The FIX code produces various results in B.
- The fraction multiply code uses 16b x 16b multiplies to produce
a 31b result. It always loses the low order bit of the product.
- The fraction divide code is an approximation that may produce
an error of 1 LSB.
- Signs are tracked implicitly as part of the fraction. Unnormalized
inputs may cause the packup code to produce the wrong sign.
- "Unclean" zeros (zero fraction, non-zero exponent) are processed
like normal operands.
*/
#include "hp2100_defs.h"
struct ufp { /* unpacked fp */
int32 exp; /* exp */
uint32 fr; }; /* frac */
#define FP_V_SIGN 31 /* sign */
#define FP_M_SIGN 01
#define FP_V_FR 8 /* fraction */
#define FP_M_FR 077777777
#define FP_V_EXP 1 /* exponent */
#define FP_M_EXP 0177
#define FP_V_EXPS 0 /* exp sign */
#define FP_M_EXPS 01
#define FP_SIGN (FP_M_SIGN << FP_V_SIGN)
#define FP_FR (FP_M_FR << FP_V_FR)
#define FP_EXP (FP_M_EXP << FP_V_EXP)
#define FP_EXPS (FP_M_EXPS << FP_V_EXPS)
#define FP_GETSIGN(x) (((x) >> FP_V_SIGN) & FP_M_SIGN)
#define FP_GETEXP(x) (((x) >> FP_V_EXP) & FP_M_EXP)
#define FP_GETEXPS(x) (((x) >> FP_V_EXPS) & FP_M_EXPS)
#define FP_NORM (1 << (FP_V_SIGN - 1)) /* normalized */
#define FP_LOW (1 << FP_V_FR)
#define FP_RNDP (1 << (FP_V_FR - 1)) /* round for plus */
#define FP_RNDM (FP_RNDP - 1) /* round for minus */
#define FPAB ((((uint32) AR) << 16) | ((uint32) BR))
#define DMASK32 0xFFFFFFFF
/* Fraction shift; 0 < shift < 32 */
#define FR_ARS(v,s) (((v) >> (s)) | (((v) & FP_SIGN)? \
(DMASK32 << (32 - (s))): 0)) & DMASK32
#define FR_NEG(v) ((~(v) + 1) & DMASK32)
extern uint16 *M;
uint32 UnpackFP (struct ufp *fop, uint32 opnd);
void NegFP (struct ufp *fop);
void NormFP (struct ufp *fop);
uint32 StoreFP (struct ufp *fop);
/* Floating to integer conversion */
uint32 f_fix (void)
{
struct ufp fop;
uint32 res = 0;
UnpackFP (&fop, FPAB); /* unpack op */
if (fop.exp < 0) { /* exp < 0? */
AR = 0; /* result = 0 */
return 0; } /* B unchanged */
if (fop.exp > 15) { /* exp > 15? */
BR = AR; /* B has high bits */
AR = 077777; /* result = 77777 */
return 1; } /* overflow */
if (fop.exp < 15) { /* if not aligned */
res = FR_ARS (fop.fr, 15 - fop.exp); /* shift right */
AR = (res >> 16) & DMASK; } /* AR gets result */
BR = AR;
if ((AR & SIGN) && ((fop.fr | res) & DMASK)) /* any low bits lost? */
AR = (AR + 1) & DMASK; /* round up */
return 0;
}
/* Integer to floating conversion */
uint32 f_flt (void)
{
struct ufp res = { 15, 0 }; /* +, 2**15 */
res.fr = ((uint32) AR) << 16; /* left justify */
StoreFP (&res); /* store result */
return 0; /* clr overflow */
}
/* Floating point add/subtract */
uint32 f_as (uint32 opnd, t_bool sub)
{
struct ufp fop1, fop2, t;
int32 ediff;
UnpackFP (&fop1, FPAB); /* unpack A-B */
UnpackFP (&fop2, opnd); /* get op */
if (sub) { /* subtract? */
fop2.fr = FR_NEG (fop2.fr); /* negate frac */
if (fop2.fr == FP_SIGN) { /* -1/2? */
fop2.fr = fop2.fr >> 1; /* special case */
fop2.exp = fop2.exp + 1; } }
if (fop1.fr == 0) fop1 = fop2; /* op1 = 0? res = op2 */
else if (fop2.fr != 0) { /* op2 = 0? no add */
if (fop1.exp < fop2.exp) { /* |op1| < |op2|? */
t = fop2; /* swap operands */
fop2 = fop1;
fop1 = t; }
ediff = fop1.exp - fop2.exp; /* get exp diff */
if (ediff <= 24) {
if (ediff) fop2.fr = FR_ARS (fop2.fr, ediff); /* denorm, signed */
if ((fop1.fr ^ fop2.fr) & FP_SIGN) /* unlike signs? */
fop1.fr = fop1.fr + fop2.fr; /* eff subtract */
else { /* like signs */
fop1.fr = fop1.fr + fop2.fr; /* eff add */
if (fop2.fr & FP_SIGN) { /* both -? */
if ((fop1.fr & FP_SIGN) == 0) { /* overflow? */
fop1.fr = FP_SIGN | (fop1.fr >> 1); /* renormalize */
fop1.exp = fop1.exp + 1; } } /* incr exp */
else if (fop1.fr & FP_SIGN) { /* both +, cry out? */
fop1.fr = fop1.fr >> 1; /* renormalize */
fop1.exp = fop1.exp + 1; } /* incr exp */
} /* end else like */
} /* end if ediff */
} /* end if fop2 */
return StoreFP (&fop1); /* store result */
}
/* Floating point multiply - passes diagnostic */
uint32 f_mul (uint32 opnd)
{
struct ufp fop1, fop2;
struct ufp res = { 0, 0 };
int32 shi1, shi2, t1, t2, t3, t4, t5;
UnpackFP (&fop1, FPAB); /* unpack A-B */
UnpackFP (&fop2, opnd); /* unpack op */
if (fop1.fr && fop2.fr) { /* if both != 0 */
res.exp = fop1.exp + fop2.exp + 1; /* exp = sum */
shi1 = SEXT (fop1.fr >> 16); /* mpy hi */
shi2 = SEXT (fop2.fr >> 16); /* mpc hi */
t1 = shi2 * ((int32) ((fop1.fr >> 1) & 077600));/* mpc hi * (mpy lo/2) */
t2 = shi1 * ((int32) ((fop2.fr >> 1) & 077600));/* mpc lo * (mpy hi/2) */
t3 = t1 + t2; /* cross product */
t4 = (shi1 * shi2) & ~1; /* mpy hi * mpc hi */
t5 = (SEXT (t3 >> 16)) << 1; /* add in cross */
res.fr = (t4 + t5) & DMASK32; } /* bit<0> is lost */
return StoreFP (&res); /* store */
}
/* Floating point divide - reverse engineered from diagnostic */
uint32 divx (uint32 ba, uint32 dvr, uint32 *rem)
{
int32 sdvd = 0, sdvr = 0;
uint32 q, r;
if (ba & FP_SIGN) sdvd = 1; /* 32b/16b signed dvd */
if (dvr & SIGN) sdvr = 1; /* use old-fashioned */
if (sdvd) ba = (~ba + 1) & DMASK32; /* unsigned divides, */
if (sdvr) dvr = (~dvr + 1) & DMASK; /* as results may ovflo */
q = ba / dvr;
r = ba % dvr;
if (sdvd ^ sdvr) q = (~q + 1) & DMASK;
if (sdvd) r = (~r + 1) & DMASK;
if (rem) *rem = r;
return q;
}
uint32 f_div (uint32 opnd)
{
struct ufp fop1, fop2;
struct ufp quo = { 0, 0 };
uint32 ba, q0, q1, q2, dvrh;
UnpackFP (&fop1, FPAB); /* unpack A-B */
UnpackFP (&fop2, opnd); /* unpack op */
dvrh = (fop2.fr >> 16) & DMASK; /* high divisor */
if (dvrh == 0) { /* div by zero? */
AR = 0077777; /* return most pos */
BR = 0177776;
return 1; }
if (fop1.fr) { /* dvd != 0? */
quo.exp = fop1.exp - fop2.exp + 1; /* exp = diff */
ba = FR_ARS (fop1.fr, 2); /* prevent ovflo */
q0 = divx (ba, dvrh, &ba); /* Q0 = dvd / dvrh */
ba = (ba & ~1) << 16; /* remainder */
ba = FR_ARS (ba, 1); /* prevent ovflo */
q1 = divx (ba, dvrh, NULL); /* Q1 = rem / dvrh */
ba = (fop2.fr & 0xFF00) << 13; /* dvrl / 8 */
q2 = divx (ba, dvrh, NULL); /* dvrl / dvrh */
ba = -(SEXT (q2)) * (SEXT (q0)); /* -Q0 * Q2 */
ba = (ba >> 16) & 0xFFFF; /* save ms half */
if (q1 & SIGN) quo.fr = quo.fr - 0x00010000; /* Q1 < 0? -1 */
if (ba & SIGN) quo.fr = quo.fr - 0x00010000; /* -Q0*Q2 < 0? */
quo.fr = quo.fr + ((ba << 2) & 0xFFFF) + q1; /* rest prod, add Q1 */
quo.fr = quo.fr << 1; /* shift result */
quo.fr = quo.fr + (q0 << 16); /* add Q0 */
} /* end if fop1.h */
return StoreFP (&quo); /* store result */
}
/* Utility routines */
/* Unpack operand */
uint32 UnpackFP (struct ufp *fop, uint32 opnd)
{
fop->fr = opnd & FP_FR; /* get frac */
fop->exp = FP_GETEXP (opnd); /* get exp */
if (FP_GETEXPS (opnd)) fop->exp = fop->exp | ~FP_M_EXP; /* < 0? sext */
return FP_GETSIGN (opnd); /* return sign */
}
/* Normalize unpacked floating point number */
void NormFP (struct ufp *fop)
{
if (fop->fr) { /* any fraction? */
uint32 test = (fop->fr >> 1) & FP_NORM;
while ((fop->fr & FP_NORM) == test) { /* until norm */
fop->exp = fop->exp - 1;
fop->fr = (fop->fr << 1); } }
else fop->exp = 0; /* clean 0 */
return;
}
/* Round fp number, store, generate overflow */
uint32 StoreFP (struct ufp *fop)
{
uint32 sign, svfr, hi, ov = 0;
NormFP (fop); /* normalize */
svfr = fop->fr; /* save fraction */
sign = FP_GETSIGN (fop->fr); /* save sign */
fop->fr = (fop->fr + (sign? FP_RNDM: FP_RNDP)) & FP_FR; /* round */
if ((fop->fr ^ svfr) & FP_SIGN) { /* sign change? */
fop->fr = (fop->fr >> 1) | (sign? FP_SIGN: 0); /* renormalize */
fop->exp = fop->exp + 1; }
if (fop->fr == 0) hi = 0; /* result 0? */
else if (fop->exp < -(FP_M_EXP + 1)) { /* underflow? */
hi = 0; /* store clean 0 */
ov = 1; }
else if (fop->exp > FP_M_EXP) { /* overflow? */
hi = 0x7FFFFFFE; /* all 1's */
ov = 1; }
else hi = (fop->fr & FP_FR) | /* merge frac */
((fop->exp & FP_M_EXP) << FP_V_EXP) | /* and exp */
((fop->exp < 0)? (1 << FP_V_EXPS): 0); /* add exp sign */
AR = (hi >> 16) & DMASK;
BR = hi & DMASK;
return ov;
}