Four corrections to typos in mnemonics in const char *opcode[] in alpha_sys.c:
_L should be _C for opcodes 2E and 2F.
Alpha simulator V4.0-0 Current git commit id: 3c1c92d
sim> ; Opcode 2E
sim> ev -m 0xB8000000
0: STL_L R0,0(R0)
4: 00000000B8000000
sim>
sim> ; Opcode 2F
sim> ev -m 0xBC000000
0: STQ_L R0,0(R0)
4: 00000000BC000000
sim>
According to, Alpha Architecture Handbook V4, October 1998, Table C2:
There are no instructions with the mnemonics STL_L or STQ_L, but there are STL_C and STQ_C.
The nmemonics are correct in https://github.com/simh/simh/blob/master/alpha/alpha_cpu.c
case OP_STL_C: /* STL_C /
case OP_STQ_C: / STQ_C */
but in https://github.com/simh/simh/blob/master/alpha/alpha_sys.c
In const char *opcode[] = { the line:
"STL", "STQ", "STL_L", "STQ_L",
has been corrected to be:
"STL", "STQ", "STL_C", "STQ_C",
=====
BF should be FB in mnemonic for Opcode 36.
Alpha simulator V4.0-0 Current git commit id: 3c1c92d
sim> ; Opcode 36
sim> ev -m 0xD8000000
0: BFGE R0,4
4: 00000000D8000000
sim>
According to, Alpha Architecture Handbook V4, October 1998, Table C2:
FBGE Bra 36 Floating branch if ≥ zero
This is correct in https://github.com/simh/simh/blob/master/alpha/alpha_cpu.c
case OP_FBGT: /* FBGT */
but in https://github.com/simh/simh/blob/master/alpha/alpha_sys.c
In const char *opcode[] = { the line
"BSR", "FBNE", "BFGE", "FBGT",
has been corrected to be...
"BSR", "FBNE", "FBGE", "FBGT",
=====
MULLQ/V should MULQ/V as the mnemonic for Opcode 13.60
sim> ; Opcode 13.60
sim> ev -m 0x4C000C00
0: MULLQ/V R0,R0,R0
4: 000000004C000C00
sim>
According to, Alpha Architecture Handbook V4, October 1998, Table C2:
MULQ/V Opr 13.60 Multiply quadword
This is correct in https://github.com/simh/simh/blob/master/alpha/alpha_cpu.c
case 0x60: /* MULQ/V */
but in https://github.com/simh/simh/blob/master/alpha/alpha_sys.c
In const char *opcode[] = { the line
"MULL/V", "MULLQ/V",
has been corrected to be:
"MULL/V", "MULQ/V",
2d5226a1cd