408 lines
12 KiB
C
408 lines
12 KiB
C
/* i0.c: Intel intellec imm8-60
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Copyright (c) 2020, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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MODIFICATIONS:
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18 July 20 - Original file.
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NOTES:
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These functions support a simulated imm8-60 interface board attached to a
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Teletype Model 33 ASR.
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*/
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#include "system_defs.h"
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#if defined (IO_NUM) && (IO_NUM > 0)
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// imm8-60 status bits
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// I/O COMMAND CONSTANTS
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#define RBIT 1 //TTY READER GO/NO GO
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#define PCMD 2 //PTP GO/NO GO
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#define RCMD 4 //PTR GO/NO GO
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#define DSB 8 //PROM ENABLE/DISABLE. DSB=1
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#define XXX 0x10 //DATA IN T/C
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#define XXY 0x20 //DATA OUT T/C
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#define PBIT 0x40 //1702 PROM PROG. GO/NO GO
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#define PBITA 0x80 //1702A PROM PROG. GO/NO GO
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// TTY I/O CONSTANTS
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#define TTI 0 //TTY INPUT DATA PORT
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#define TTO 0 //TTY OUTPUT DATA PORT
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#define TTS 1 //TTY INPUT STATUS PORT
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#define TTC 1 //TTY OUTPUT COMMAND PORT
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#define TTYGO RBIT OR DSB //START TTY READER
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#define TTYNO DSB //STOP TTY READER
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#define TTYDA 1 //DATA AVAILABLE
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#define TTYBE 4 //TRANSMIT BUFFER EMPTY
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// CRT I/O CONSTANTS
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#define CRTI 4 //CRT INPUT DATA PORT
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#define CRTS 5 //CRT INPUT STATUS PORT
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#define CRTO 4 //CRT OUTPUT DATA PORT
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#define CRTDA 1 //DATA AVAILABLE
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#define CRTBE 4 //TRANSMIT BUFFER EMPTY
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// PTR I/O CONSTANTS
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#define PTRI 3 //PTR INPUT DATA PORT (NOT INVERTED)
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#define PTRS TTS //PTR INPUT STATUS PORT
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#define PTRC TTC //PTR OUTPUT COMMAND PORT
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#define PTRGO RCMD OR DSB //START PTR
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#define PTRNO TTYNO //STOP PTR
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#define PTRDA 0x20 //PTR DATA AVAILABLE
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// PTP I/O CONSTANTS
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#define PTPO 3 //PTP OUTPUT DATA PORT
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#define PTPS TTS //PTP INPUT STATUS PORT
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#define PTPC TTC //PTP OUTPUT COMMAND PORT
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#define PRDY 0x40 //PUNCH READY STATUS
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#define PTPGO PCMD OR DSB //PTP START PUNCH
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#define PTPNO TTYNO //STOP PUNCH
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// PROM PROGRAMMER I/O CONSTANTS
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#define PAD 2 //PROM ADDRES OUTPUT PORT
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#define PDO PTPO //PROM DATA OUTPUT PORT
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#define PDI 2 //PROM DATA INPUT PORT
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#define PROMC TTC //PROGRAMMING PULSE OUTPUT PORT
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#define PROGO PBITA //START PROGRAMMING
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#define PRONO 0 //STOP PROGRAMMING
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#define ENB 0 //ENABLE PROGRAMMER
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/* external globals */
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/* external function prototypes */
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extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
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/* globals */
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uint8 status = 0;
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uint8 command = 0;
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/* function prototypes */
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t_stat IO_cfg(uint8 base, uint8 devnum);
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t_stat IO_svc (UNIT *uptr);
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t_stat IO_reset (DEVICE *dptr);
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t_stat IO_attach (UNIT *uptr, CONST char *cptr);
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t_stat PTR_reset(DEVICE *dptr);
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t_stat PTR_attach (UNIT *uptr, CONST char *cptr);
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uint8 IO_is(t_bool io, uint8 data, uint8 devnum);
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uint8 IO_id(t_bool io, uint8 data, uint8 devnum);
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uint8 IO_oc(t_bool io, uint8 data, uint8 devnum);
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uint8 IO_od(t_bool io, uint8 data, uint8 devnum);
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void IO_reset_dev(uint8 devnum);
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/* imm-60 Standard I/O Data Structures */
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UNIT IO_unit[4] = {
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{ UDATA (&IO_svc, 0, 0), 10 }, //TTY input/output
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{ UDATA (&IO_svc, 0, 0), 10 }, //TTY status/command
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{ UDATA (&IO_svc, 0, 0), KBD_POLL_WAIT }, //PROM data input/output
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF, 0x1000) } //TTY reader/punch
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};
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REG IO_reg[] = {
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{ HRDATA (DATA0, IO_unit[0].buf, 8) },
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{ HRDATA (STAT0, status, 8) },
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{ HRDATA (MODE0, IO_unit[0].u4, 8) },
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{ HRDATA (CMD0, IO_unit[0].u5, 8) },
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{ HRDATA (DATA1, IO_unit[1].buf, 8) },
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{ HRDATA (STAT1, status, 8) },
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{ HRDATA (MODE1, IO_unit[1].u4, 8) },
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{ HRDATA (CMD1, IO_unit[1].u5, 8) },
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{ HRDATA (DATA2, IO_unit[2].buf, 8) },
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{ HRDATA (STAT2, status, 8) },
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{ HRDATA (MODE2, IO_unit[2].u4, 8) },
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{ HRDATA (CMD2, IO_unit[2].u5, 8) },
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{ HRDATA (DATA3, IO_unit[3].buf, 8) },
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{ HRDATA (STAT3, status, 8) },
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{ HRDATA (MODE3, IO_unit[3].u4, 8) },
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{ HRDATA (CMD3, IO_unit[3].u5, 8) },
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{ NULL }
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};
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DEBTAB IO_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "XACK", DEBUG_xack },
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{ "LEV1", DEBUG_level1 },
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{ "LEV2", DEBUG_level2 },
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{ NULL }
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};
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MTAB IO_mod[] = {
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{ 0 }
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};
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/* address width is set to 16 bits to use devices in 8086/8088 implementations */
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DEVICE IO_dev = {
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"IO", //name
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IO_unit, //units
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IO_reg, //registers
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IO_mod, //modifiers
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IO_NUM, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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&IO_reset, //reset
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NULL, //boot
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&IO_attach, //attach
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NULL, //detach
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NULL, //ctxt
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0, //flags
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0, //dctrl
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IO_debug, //debflags
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NULL, //msize
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NULL //lname
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};
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UNIT PTR_unit[1] = {
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF, 0x1000) } //TTY reader/punch
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};
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REG PTR_reg[] = {
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{ HRDATA (DATA0, IO_unit[0].buf, 8) },
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{ HRDATA (STAT0, status, 8) },
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{ HRDATA (MODE0, IO_unit[0].u4, 8) },
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{ HRDATA (CMD0, IO_unit[0].u5, 8) },
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{ NULL }
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};
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DEBTAB PTR_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "XACK", DEBUG_xack },
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{ "LEV1", DEBUG_level1 },
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{ "LEV2", DEBUG_level2 },
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{ NULL }
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};
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MTAB PTR_mod[] = {
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{ 0 }
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};
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/* address width is set to 16 bits to use devices in 8086/8088 implementations */
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DEVICE PTR_dev = {
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"PTR", //name
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PTR_unit, //units
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PTR_reg, //registers
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PTR_mod, //modifiers
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PTR_NUM, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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&PTR_reset, //reset
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NULL, //boot
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&PTR_attach, //attach
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NULL, //detach
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NULL, //ctxt
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0, //flags
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0, //dctrl
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PTR_debug, //debflags
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NULL, //msize
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NULL //lname
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};
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// imm-60 configuration
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t_stat IO_cfg(uint8 base, uint8 devnum)
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{
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sim_printf(" io[%d]: at base port 0%02XH\n",
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devnum, base & 0xFF);
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reg_dev(IO_id, base, devnum);
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reg_dev(IO_is, base + 1, devnum);
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reg_dev(IO_oc, base + 2, devnum);
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reg_dev(IO_od, base + 3, devnum);
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return SCPE_OK;
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}
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/* Service routines to handle simulator functions */
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/* IO_svc - actually gets char & places in buffer */
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t_stat IO_svc (UNIT *uptr)
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{
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int32 temp;
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sim_activate (uptr, uptr->wait); /* continue poll */
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if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) {
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status |= TTYDA; //clear data avail
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return temp; /* no char or error? */
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}
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// if (command & RBIT) { //read from tty rdr
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// printf("%c", (int)(uptr+3)->filebuf);
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// }
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uptr->buf = toupper(temp & 0x7F); /* Save char */
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status &= ~TTYDA; /* Set data available status */
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat IO_reset (DEVICE *dptr)
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{
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uint8 devnum;
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for (devnum=0; devnum < IO_NUM; devnum++) {
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IO_reset_dev(devnum);
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sim_activate (&IO_unit[devnum], IO_unit[devnum].wait); /* activate unit */
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}
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return SCPE_OK;
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}
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void IO_reset_dev(uint8 devnum)
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{
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status = TTYDA | PTRDA | DSB; /* set data not avail status */
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IO_unit[devnum].u4 = 0;
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IO_unit[devnum].u5 = 0;
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IO_unit[devnum].u6 = 0;
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IO_unit[devnum].buf = 0;
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IO_unit[devnum].pos = 0;
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}
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t_stat IO_attach (UNIT *uptr, CONST char *cptr)
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{
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t_stat r;
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if ((r = attach_unit (uptr, cptr)) != SCPE_OK) {
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sim_printf(" IO_attach: Attach error %d\n", r);
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return r;
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}
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return SCPE_OK;
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}
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t_stat PTR_reset(DEVICE *dptr)
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{
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return SCPE_OK;
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}
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t_stat PTR_attach (UNIT *uptr, CONST char *cptr)
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{
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t_stat r;
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if ((r = attach_unit (uptr, cptr)) != SCPE_OK) {
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sim_printf(" PTR_attach: Attach error %d\n", r);
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return r;
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}
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return SCPE_OK;
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}
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/* I/O instruction handlers, called from the CPU module when an
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IN or OUT instruction is issued.
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*/
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// status/command
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uint8 IO_is(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read status port - works*/
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return status;
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} else { /* write command port */
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command = data;
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if (command & RBIT) {
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status &= ~TTYDA; /* Set data available status */
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data = data;
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}
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}
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return 0;
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}
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// TTY in/out
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uint8 IO_id(t_bool io, uint8 data, uint8 devnum)
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{
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char val;
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if (io == 0) { /* read data port */
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if (command & RBIT) { //read from tty rdr
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status |= TTYDA; //set TTYDA off
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return 'Z';
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} else {
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status |= TTYDA; //set TTYDA off
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val = IO_unit[devnum].buf;
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val = (~val) & 0x7f;
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return (val);
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}
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} else { /* write data port - works*/
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// IO_unit[devnum].u3 |= TTYBE; //set TTYBE off
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val = ~data;
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sim_putchar(val & 0x7f);
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}
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return 0;
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}
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uint8 IO_oc(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read status port */
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data = data;
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} else { /* write status port */
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data = data;
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}
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return 0;
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}
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// TTY RDR in/PCH out
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uint8 IO_od(t_bool io, uint8 data, uint8 devnum)
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{
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char val;
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if (io == 0) { /* read data port */
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status |= PTRDA; //set PTRDA off
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val = IO_unit[devnum].buf;
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val = (~val) & 0x7f;
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return (val);
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} else { /* write data port - works*/
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data = data;
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// IO_unit[devnum].u3 |= TTYBE; //set TTYBE off
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// val = ~data;
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// sim_putchar(val & 0x7f);
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}
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return 0;
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}
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#endif /* IO_NUM > 0 */
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/* end of imm8-60.c */
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