38668a25f1
a) Added sim_debug statements, formatted console messages. b) Removed old debugging statements and redundant byte/word mask operations. c) Added more device commands. d) Added zx-200a and changed nulldev to return 0 vice 0xff. e) Added commands and corrected RTYPE and RBYTE behavior so ISIS-II would boot. f) Corrected device calls in SBC_reset, corrected get_mbyte and put_mbyte to match control bits from ipc_cont.c.
752 lines
28 KiB
C
752 lines
28 KiB
C
/* isbc202.c: Intel double density disk adapter adapter
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Copyright (c) 2010, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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MODIFICATIONS:
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27 Jun 16 - Original file.
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NOTES:
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This controller will mount 4 DD disk images on drives :F0: thru :F3: addressed
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at ports 078H to 07FH.
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Registers:
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078H - Read - Subsystem status
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bit 0 - ready status of drive 0
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bit 1 - ready status of drive 1
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bit 2 - state of channel's interrupt FF
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bit 3 - controller presence indicator
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bit 4 - DD controller presence indicator
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bit 5 - ready status of drive 2
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bit 6 - ready status of drive 3
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bit 7 - zero
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079H - Read - Read result type (bits 2-7 are zero)
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00 - I/O complete with error
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01 - Reserved
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10 - Result byte contains diskette ready status
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11 - Reserved
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079H - Write - IOPB address low byte.
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07AH - Write - IOPB address high byte and start operation.
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07BH - Read - Read result byte
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If result type is 00H
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bit 0 - deleted record
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bit 1 - CRC error
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bit 2 - seek error
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bit 3 - address error
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bit 4 - data overrun/underrun
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bit 5 - write protect
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bit 6 - write error
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bit 7 - not ready
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If result type is 02H
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bit 0 - zero
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bit 1 - zero
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bit 2 - zero
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bit 3 - zero
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bit 4 - drive 2 ready
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bit 5 - drive 3 ready
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bit 6 - drive 0 ready
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bit 7 - drive 1 ready
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07FH - Write - Reset diskette system.
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Operations:
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NOP - 0x00
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Seek - 0x01
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Format Track - 0x02
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Recalibrate - 0x03
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Read Data - 0x04
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Verify CRC - 0x05
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Write Data - 0x06
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Write Deleted Data - 0x07
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IOPB - I/O Parameter Block
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Byte 0 - Channel Word
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bit 3 - data word length (=8-bit, 1=16-bit)
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bit 4-5 - interrupt control
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00 - I/O complete interrupt to be issued
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01 - I/O complete interrupts are disabled
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10 - illegal code
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11 - illegal code
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bit 6- randon format sequence
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Byte 1 - Diskette Instruction
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bit 0-2 - operation code
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000 - no operation
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001 - seek
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010 - format track
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011 - recalibrate
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100 - read data
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101 - verify CRC
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110 - write data
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111 - write deleted data
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bit 3 - data word length ( same as byte-0, bit-3)
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bit 4-5 - unit select
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00 - drive 0
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01 - drive 1
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10 - drive 2
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11 - drive 3
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bit 6-7 - reserved (zero)
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Byte 2 - Number of Records
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Byte 4 - Track Address
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Byte 5 - Sector Address
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Byte 6 - Buffer Low Address
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Byte 7 - Buffer High Address
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u3 -
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u4 -
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u5 -
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u6 - fdd number.
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*/
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#include "system_defs.h" /* system header in system dir */
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#define DEBUG 0
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#define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */
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#define UNIT_WPMODE (1 << UNIT_V_WPMODE)
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#define FDD_NUM 4
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//disk controoler operations
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#define DNOP 0x00 //disk no operation
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#define DSEEK 0x01 //disk seek
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#define DFMT 0x02 //disk format
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#define DHOME 0x03 //disk home
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#define DREAD 0x04 //disk read
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#define DVCRC 0x05 //disk verify CRC
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#define DWRITE 0x06 //disk write
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//status
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#define RDY0 0x01 //FDD 0 ready
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#define RDY1 0x02 //FDD 1 ready
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#define FDCINT 0x04 //FDC interrupt flag
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#define FDCPRE 0x08 //FDC board present
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#define FDCDD 0x10 //fdc is DD
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#define RDY2 0x20 //FDD 2 ready
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#define RDY3 0x40 //FDD 3 ready
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//result type
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#define RERR 0x00 //FDC returned error
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#define ROK 0x02 //FDC returned ok
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// If result type is RERR then rbyte is
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#define RB0DR 0x01 //deleted record
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#define RB0CRC 0x02 //CRC error
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#define RB0SEK 0x04 //seek error
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#define RB0ADR 0x08 //address error
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#define RB0OU 0x10 //data overrun/underrun
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#define RB0WP 0x20 //write protect
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#define RB0WE 0x40 //write error
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#define RB0NR 0x80 //not ready
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// If result type is ROK then rbyte is
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#define RB1RD2 0x10 //drive 2 ready
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#define RB1RD3 0x20 //drive 3 ready
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#define RB1RD0 0x40 //drive 0 ready
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#define RB1RD1 0x80 //drive 1 ready
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/* external globals */
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extern uint16 port; //port called in dev_table[port]
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extern int32 PCX;
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/* external function prototypes */
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extern uint16 reg_dev(uint8 (*routine)(t_bool, uint8), uint16, uint8);
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extern uint8 multibus_get_mbyte(uint16 addr);
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extern uint16 multibus_get_mword(uint16 addr);
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extern void multibus_put_mbyte(uint16 addr, uint8 val);
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extern uint8 multibus_put_mword(uint16 addr, uint16 val);
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/* function prototypes */
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t_stat isbc202_reset(DEVICE *dptr, uint16 base);
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void isbc202_reset1(uint8 fdcnum);
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t_stat isbc202_attach (UNIT *uptr, CONST char *cptr);
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t_stat isbc202_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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uint8 isbc202_get_dn(void);
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uint8 isbc2020(t_bool io, uint8 data); /* isbc202 0 */
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uint8 isbc2021(t_bool io, uint8 data); /* isbc202 1 */
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uint8 isbc2022(t_bool io, uint8 data); /* isbc202 2 */
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uint8 isbc2023(t_bool io, uint8 data); /* isbc202 3 */
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uint8 isbc2027(t_bool io, uint8 data); /* isbc202 7 */
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void isbc202_diskio(uint8 fdcnum); //do actual disk i/o
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/* globals */
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int32 isbc202_fdcnum = 0; //actual number of SBC-202 instances + 1
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typedef struct { //FDD definition
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uint8 *buf;
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int t0;
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int rdy;
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uint8 sec;
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uint8 cyl;
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uint8 maxsec;
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uint8 maxcyl;
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} FDDDEF;
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typedef struct { //FDC definition
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uint16 baseport; //FDC base port
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uint16 iopb; //FDC IOPB
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uint8 stat; //FDC status
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uint8 rtype; //FDC result type
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uint8 rbyte0; //FDC result byte for type 00
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uint8 rbyte1; //FDC result byte for type 10
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uint8 intff; //fdc interrupt FF
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FDDDEF fdd[FDD_NUM]; //indexed by the FDD number
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} FDCDEF;
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FDCDEF fdc202[4]; //indexed by the isbc-202 instance number
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UNIT isbc202_unit[] = {
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE, 0), 20 },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE, 0), 20 },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE, 0), 20 },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE, 0), 20 }
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};
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REG isbc202_reg[] = {
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{ HRDATA (STAT0, fdc202[0].stat, 8) }, /* isbc202 0 status */
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{ HRDATA (RTYP0, fdc202[0].rtype, 8) }, /* isbc202 0 result type */
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{ HRDATA (RBYT0A, fdc202[0].rbyte0, 8) }, /* isbc202 0 result byte 0 */
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{ HRDATA (RBYT0B, fdc202[0].rbyte1, 8) }, /* isbc202 0 result byte 1 */
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{ HRDATA (INTFF0, fdc202[0].intff, 8) }, /* isbc202 0 interrupt f/f */
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{ HRDATA (STAT1, fdc202[1].stat, 8) }, /* isbc202 1 status */
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{ HRDATA (RTYP1, fdc202[1].rtype, 8) }, /* isbc202 1 result type */
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{ HRDATA (RBYT1A, fdc202[1].rbyte0, 8) }, /* isbc202 1 result byte 0 */
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{ HRDATA (RBYT1B, fdc202[1].rbyte1, 8) }, /* isbc202 1 result byte 1 */
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{ HRDATA (INTFF1, fdc202[1].intff, 8) }, /* isbc202 1 interrupt f/f */
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{ HRDATA (STAT2, fdc202[2].stat, 8) }, /* isbc202 2 status */
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{ HRDATA (RTYP2, fdc202[2].rtype, 8) }, /* isbc202 2 result type */
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{ HRDATA (RBYT2A, fdc202[2].rbyte0, 8) }, /* isbc202 2 result byte 0 */
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{ HRDATA (RBYT2B, fdc202[0].rbyte1, 8) }, /* isbc202 2 result byte 1 */
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{ HRDATA (INTFF2, fdc202[2].intff, 8) }, /* isbc202 2 interrupt f/f */
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{ HRDATA (STAT3, fdc202[3].stat, 8) }, /* isbc202 3 status */
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{ HRDATA (RTYP3, fdc202[3].rtype, 8) }, /* isbc202 3 result type */
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{ HRDATA (RBYT3A, fdc202[3].rbyte0, 8) }, /* isbc202 3 result byte 0 */
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{ HRDATA (RBYT3B, fdc202[3].rbyte1, 8) }, /* isbc202 3 result byte 1 */
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{ HRDATA (INTFF3, fdc202[0].intff, 8) }, /* isbc202 3 interrupt f/f */
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{ NULL }
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};
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MTAB isbc202_mod[] = {
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{ UNIT_WPMODE, 0, "RW", "RW", &isbc202_set_mode },
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{ UNIT_WPMODE, UNIT_WPMODE, "WP", "WP", &isbc202_set_mode },
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{ 0 }
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};
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DEBTAB isbc202_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "XACK", DEBUG_xack },
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{ "LEV1", DEBUG_level1 },
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{ "LEV2", DEBUG_level2 },
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{ NULL }
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};
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/* address width is set to 16 bits to use devices in 8086/8088 implementations */
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DEVICE isbc202_dev = {
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"SBC202", //name
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isbc202_unit, //units
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isbc202_reg, //registers
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isbc202_mod, //modifiers
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FDD_NUM, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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NULL, //reset
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NULL, //boot
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&isbc202_attach, //attach
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NULL, //detach
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NULL, //ctxt
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DEV_DEBUG+DEV_DISABLE+DEV_DIS, //flags
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DEBUG_flow + DEBUG_read + DEBUG_write, //dctrl
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isbc202_debug, //debflags
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NULL, //msize
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NULL //lname
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};
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/* Hardware reset routine */
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t_stat isbc202_reset(DEVICE *dptr, uint16 base)
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{
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sim_printf(" iSBC-202 FDC Board");
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if (SBC202_NUM) {
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sim_printf(" - Found\n");
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sim_printf(" isbc202-%d: Hardware Reset\n", isbc202_fdcnum);
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sim_printf(" isbc202-%d: Registered at %04X\n", isbc202_fdcnum, base);
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fdc202[isbc202_fdcnum].baseport = base;
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reg_dev(isbc2020, base, isbc202_fdcnum); //read status
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reg_dev(isbc2021, base + 1, isbc202_fdcnum); //read rslt type/write IOPB addr-l
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reg_dev(isbc2022, base + 2, isbc202_fdcnum); //write IOPB addr-h and start
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reg_dev(isbc2023, base + 3, isbc202_fdcnum); //read rstl byte
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reg_dev(isbc2027, base + 7, isbc202_fdcnum); //write reset isbc202
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isbc202_reset1(isbc202_fdcnum);
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isbc202_fdcnum++;
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} else
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sim_printf(" - Not Found\n");
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return SCPE_OK;
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}
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/* Software reset routine */
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void isbc202_reset1(uint8 fdcnum)
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{
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int32 i;
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UNIT *uptr;
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sim_printf(" isbc202-%d: Software Reset\n", fdcnum);
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fdc202[fdcnum].stat = 0; //clear status
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for (i = 0; i < FDD_NUM; i++) { /* handle all units */
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uptr = isbc202_dev.units + i;
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fdc202[fdcnum].stat |= FDCPRE | FDCDD; //set the FDC status
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fdc202[fdcnum].rtype = ROK;
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if (uptr->capac == 0) { /* if not configured */
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uptr->u5 = fdcnum; //fdc device number
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uptr->u6 = i; //fdd unit number
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uptr->flags |= UNIT_WPMODE; /* set WP in unit flags */
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sim_printf(" SBC202%d: Configured, Status=%02X Not attached\n", i, fdc202[fdcnum].stat);
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} else {
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switch(i){
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case 0:
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fdc202[fdcnum].stat |= RDY0; //set FDD 0 ready
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fdc202[fdcnum].rbyte1 |= RB1RD0;
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break;
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case 1:
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fdc202[fdcnum].stat |= RDY1; //set FDD 1 ready
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fdc202[fdcnum].rbyte1 |= RB1RD1;
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break;
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case 2:
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fdc202[fdcnum].stat |= RDY2; //set FDD 2 ready
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fdc202[fdcnum].rbyte1 |= RB1RD2;
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break;
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case 3:
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fdc202[fdcnum].stat |= RDY3; //set FDD 3 ready
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fdc202[fdcnum].rbyte1 |= RB1RD3;
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break;
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}
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sim_printf(" SBC202%d: Configured, Status=%02X Attached to %s\n",
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i, fdc202[fdcnum].stat, uptr->filename);
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}
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}
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}
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/* isbc202 attach - attach an .IMG file to a FDD */
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t_stat isbc202_attach (UNIT *uptr, CONST char *cptr)
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{
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t_stat r;
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FILE *fp;
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int32 i, c = 0;
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long flen;
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uint8 fdcnum, fddnum;
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sim_debug (DEBUG_flow, &isbc202_dev, " isbc202_attach: Entered with cptr=%s\n", cptr);
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if ((r = attach_unit (uptr, cptr)) != SCPE_OK) {
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sim_printf(" isbc202_attach: Attach error\n");
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return r;
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}
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fdcnum = uptr->u5;
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fddnum = uptr->u6;
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fp = fopen(uptr->filename, "rb");
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if (fp == NULL) {
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sim_printf(" Unable to open disk image file %s\n", uptr->filename);
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sim_printf(" No disk image loaded!!!\n");
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} else {
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sim_printf("isbc202: Attach\n");
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fseek(fp, 0, SEEK_END); /* size disk image */
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flen = ftell(fp);
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fseek(fp, 0, SEEK_SET);
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if (fdc202[fdcnum].fdd[fddnum].buf == NULL) { /* no buffer allocated */
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fdc202[fdcnum].fdd[fddnum].buf = (uint8 *)malloc(flen);
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if (fdc202[fdcnum].fdd[fddnum].buf == NULL) {
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sim_printf(" isbc202_attach: Malloc error\n");
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return SCPE_MEM;
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}
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}
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uptr->capac = flen;
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i = 0;
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c = fgetc(fp); // copy disk image into buffer
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while (c != EOF) {
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*(fdc202[fdcnum].fdd[fddnum].buf + i++) = c & 0xFF;
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c = fgetc(fp);
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}
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fclose(fp);
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switch(fddnum){
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case 0:
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fdc202[fdcnum].stat |= RDY0; //set FDD 0 ready
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fdc202[fdcnum].rtype = ROK;
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fdc202[fdcnum].rbyte1 |= RB1RD0;
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break;
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case 1:
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fdc202[fdcnum].stat |= RDY1; //set FDD 1 ready
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fdc202[fdcnum].rtype = ROK;
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fdc202[fdcnum].rbyte1 |= RB1RD1;
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break;
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case 2:
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fdc202[fdcnum].stat |= RDY2; //set FDD 2 ready
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fdc202[fdcnum].rtype = ROK;
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fdc202[fdcnum].rbyte1 |= RB1RD2;
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break;
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case 3:
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fdc202[fdcnum].stat |= RDY3; //set FDD 3 ready
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fdc202[fdcnum].rtype = ROK;
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fdc202[fdcnum].rbyte1 |= RB1RD3;
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break;
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}
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if (flen == 512512) { /* 8" 512K SSDD */
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fdc202[fdcnum].fdd[fddnum].maxcyl = 77;
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fdc202[fdcnum].fdd[fddnum].maxsec = 52;
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fdc202[fdcnum].fdd[fddnum].sec = 1;
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fdc202[fdcnum].fdd[fddnum].cyl = 0;
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} else
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sim_printf(" iSBC-202-%d: Not a DD disk image\n", fdcnum);
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sim_printf(" iSBC-202%d: Configured %d bytes, Attached to %s\n",
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fdcnum, uptr->capac, uptr->filename);
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}
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sim_debug (DEBUG_flow, &isbc202_dev, " isbc202_attach: Done\n");
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return SCPE_OK;
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}
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/* isbc202 set mode = Write protect */
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t_stat isbc202_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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// sim_debug (DEBUG_flow, &isbc202_dev, " isbc202_set_mode: Entered with val=%08XH uptr->flags=%08X\n",
|
|
// val, uptr->flags);
|
|
if (val & UNIT_WPMODE) { /* write protect */
|
|
uptr->flags |= val;
|
|
} else { /* read write */
|
|
uptr->flags &= ~val;
|
|
}
|
|
// sim_debug (DEBUG_flow, &isbc202_dev, " isbc202_set_mode: Done\n");
|
|
return SCPE_OK;
|
|
}
|
|
|
|
uint8 isbc202_get_dn(void)
|
|
{
|
|
int i;
|
|
|
|
for (i=0; i<SBC202_NUM; i++)
|
|
if (port >= fdc202[i].baseport && port <= fdc202[i].baseport + 7)
|
|
return i;
|
|
sim_printf("isbc202_get_dn: port %04X not in isbc202 device table\n", port);
|
|
return 0xFF;
|
|
}
|
|
|
|
/* ISBC202 control port functions */
|
|
|
|
uint8 isbc2020(t_bool io, uint8 data)
|
|
{
|
|
uint8 fdcnum;
|
|
|
|
if ((fdcnum = isbc202_get_dn()) != 0xFF) {
|
|
if (io == 0) { /* read ststus*/
|
|
if (DEBUG)
|
|
sim_printf("\n isbc202-%d: 0x78 returned status=%02X PCX=%04X", fdcnum, fdc202[fdcnum].stat, PCX);
|
|
return fdc202[fdcnum].stat;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
uint8 isbc2021(t_bool io, uint8 data)
|
|
{
|
|
uint8 fdcnum;
|
|
|
|
if ((fdcnum = isbc202_get_dn()) != 0xFF) {
|
|
if (io == 0) { /* read data port */
|
|
fdc202[fdcnum].intff = 0; //clear interrupt FF
|
|
fdc202[fdcnum].stat &= ~FDCINT;
|
|
if (DEBUG)
|
|
sim_printf("\n isbc202-%d: 0x79 returned rtype=%02X intff=%02X status=%02X PCX=%04X",
|
|
fdcnum, fdc202[fdcnum].rtype, fdc202[fdcnum].intff, fdc202[fdcnum].stat, PCX);
|
|
return fdc202[fdcnum].rtype;
|
|
} else { /* write data port */
|
|
fdc202[fdcnum].iopb = data;
|
|
if (DEBUG)
|
|
sim_printf("\n isbc202-%d: 0x79 IOPB low=%02X PCX=%04X", fdcnum, data, PCX);
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
uint8 isbc2022(t_bool io, uint8 data)
|
|
{
|
|
uint8 fdcnum;
|
|
|
|
if ((fdcnum = isbc202_get_dn()) != 0xFF) {
|
|
if (io == 0) { /* read data port */
|
|
;
|
|
} else { /* write data port */
|
|
fdc202[fdcnum].iopb |= (data << 8);
|
|
if (DEBUG)
|
|
sim_printf("\n isbc202-%d: 0x7A IOPB=%04X PCX=%04X", fdcnum, fdc202[fdcnum].iopb, PCX);
|
|
isbc202_diskio(fdcnum);
|
|
if (fdc202[fdcnum].intff)
|
|
fdc202[fdcnum].stat |= FDCINT;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
uint8 isbc2023(t_bool io, uint8 data)
|
|
{
|
|
uint8 fdcnum, rslt;
|
|
|
|
if ((fdcnum = isbc202_get_dn()) != 0xFF) {
|
|
if (io == 0) { /* read data port */
|
|
if (DEBUG)
|
|
sim_printf("\n isbc202-%d: 0x7B returned rtype=%02X result byte=%02X PCX=%04X",
|
|
fdcnum, fdc202[fdcnum].rtype, rslt, PCX);
|
|
return rslt;
|
|
} else { /* write data port */
|
|
; //stop diskette operation
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
uint8 isbc2027(t_bool io, uint8 data)
|
|
{
|
|
uint8 fdcnum;
|
|
|
|
if ((fdcnum = isbc202_get_dn()) != 0xFF) {
|
|
if (io == 0) { /* read data port */
|
|
;
|
|
} else { /* write data port */
|
|
isbc202_reset1(fdcnum);
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
// perform the actual disk I/O operation
|
|
|
|
void isbc202_diskio(uint8 fdcnum)
|
|
{
|
|
uint8 cw, di, nr, ta, sa, data, nrptr, c;
|
|
uint16 ba;
|
|
uint32 dskoff;
|
|
uint8 fddnum, fmtb;
|
|
uint32 i;
|
|
UNIT *uptr;
|
|
FILE *fp;
|
|
//parse the IOPB
|
|
cw = multibus_get_mbyte(fdc202[fdcnum].iopb);
|
|
di = multibus_get_mbyte(fdc202[fdcnum].iopb + 1);
|
|
nr = multibus_get_mbyte(fdc202[fdcnum].iopb + 2);
|
|
ta = multibus_get_mbyte(fdc202[fdcnum].iopb + 3);
|
|
sa = multibus_get_mbyte(fdc202[fdcnum].iopb + 4);
|
|
ba = multibus_get_mword(fdc202[fdcnum].iopb + 5);
|
|
fddnum = (di & 0x30) >> 4;
|
|
uptr = isbc202_dev.units + fddnum;
|
|
if (DEBUG) {
|
|
sim_printf("\n isbc202-%d: isbc202_diskio IOPB=%04X FDD=%02X STAT=%02X",
|
|
fdcnum, fdc202[fdcnum].iopb, fddnum, fdc202[fdcnum].stat);
|
|
sim_printf("\n isbc202-%d: cw=%02X di=%02X nr=%02X ta=%02X sa=%02X ba=%04X",
|
|
fdcnum, cw, di, nr, ta, sa, ba);
|
|
sim_printf("\n isbc202-%d: maxsec=%02X maxcyl=%02X",
|
|
fdcnum, fdc202[fdcnum].fdd[fddnum].maxsec, fdc202[fdcnum].fdd[fddnum].maxcyl);
|
|
}
|
|
//check for not ready
|
|
switch(fddnum) {
|
|
case 0:
|
|
if ((fdc202[fdcnum].stat & RDY0) == 0) {
|
|
fdc202[fdcnum].rtype = RERR;
|
|
fdc202[fdcnum].rbyte0 = RB0NR;
|
|
fdc202[fdcnum].intff = 1; //set interrupt FF
|
|
sim_printf("\n isbc202-%d: Ready error on drive %d", fdcnum, fddnum);
|
|
return;
|
|
}
|
|
break;
|
|
case 1:
|
|
if ((fdc202[fdcnum].stat & RDY1) == 0) {
|
|
fdc202[fdcnum].rtype = RERR;
|
|
fdc202[fdcnum].rbyte0 = RB0NR;
|
|
fdc202[fdcnum].intff = 1; //set interrupt FF
|
|
sim_printf("\n isbc202-%d: Ready error on drive %d", fdcnum, fddnum);
|
|
return;
|
|
}
|
|
break;
|
|
case 2:
|
|
if ((fdc202[fdcnum].stat & RDY2) == 0) {
|
|
fdc202[fdcnum].rtype = RERR;
|
|
fdc202[fdcnum].rbyte0 = RB0NR;
|
|
fdc202[fdcnum].intff = 1; //set interrupt FF
|
|
sim_printf("\n isbc202-%d: Ready error on drive %d", fdcnum, fddnum);
|
|
return;
|
|
}
|
|
break;
|
|
case 3:
|
|
if ((fdc202[fdcnum].stat & RDY3) == 0) {
|
|
fdc202[fdcnum].rtype = RERR;
|
|
fdc202[fdcnum].rbyte0 = RB0NR;
|
|
fdc202[fdcnum].intff = 1; //set interrupt FF
|
|
sim_printf("\n isbc202-%d: Ready error on drive %d", fdcnum, fddnum);
|
|
return;
|
|
}
|
|
break;
|
|
}
|
|
//check for address error
|
|
if (
|
|
((di & 0x07) != 0x03) && (
|
|
(sa > fdc202[fdcnum].fdd[fddnum].maxsec) ||
|
|
((sa + nr) > (fdc202[fdcnum].fdd[fddnum].maxsec + 1)) ||
|
|
(sa == 0) ||
|
|
(ta > fdc202[fdcnum].fdd[fddnum].maxcyl)
|
|
)) {
|
|
if (DEBUG)
|
|
sim_printf("\n isbc202-%d: maxsec=%02X maxcyl=%02X",
|
|
fdcnum, fdc202[fdcnum].fdd[fddnum].maxsec, fdc202[fdcnum].fdd[fddnum].maxcyl);
|
|
fdc202[fdcnum].rtype = RERR;
|
|
fdc202[fdcnum].rbyte0 = RB0ADR;
|
|
fdc202[fdcnum].intff = 1; //set interrupt FF
|
|
sim_printf("\n isbc202-%d: Address error on drive %d", fdcnum, fddnum);
|
|
return;
|
|
}
|
|
switch (di & 0x07) {
|
|
case DNOP:
|
|
fdc202[fdcnum].rtype = ROK;
|
|
fdc202[fdcnum].intff = 1; //set interrupt FF
|
|
break;
|
|
case DSEEK:
|
|
fdc202[fdcnum].fdd[fddnum].sec = sa;
|
|
fdc202[fdcnum].fdd[fddnum].cyl = ta;
|
|
fdc202[fdcnum].rtype = ROK;
|
|
fdc202[fdcnum].intff = 1; //set interrupt FF
|
|
break;
|
|
case DHOME:
|
|
fdc202[fdcnum].fdd[fddnum].sec = sa;
|
|
fdc202[fdcnum].fdd[fddnum].cyl = 0;
|
|
fdc202[fdcnum].rtype = ROK;
|
|
fdc202[fdcnum].intff = 1; //set interrupt FF
|
|
break;
|
|
case DVCRC:
|
|
fdc202[fdcnum].rtype = ROK;
|
|
fdc202[fdcnum].intff = 1; //set interrupt FF
|
|
break;
|
|
case DFMT:
|
|
//check for WP
|
|
if(uptr->flags & UNIT_WPMODE) {
|
|
fdc202[fdcnum].rtype = RERR;
|
|
fdc202[fdcnum].rbyte0 = RB0WP;
|
|
fdc202[fdcnum].intff = 1; //set interrupt FF
|
|
sim_printf("\n isbc202-%d: Write protect error 1 on drive %d", fdcnum, fddnum);
|
|
return;
|
|
}
|
|
fmtb = multibus_get_mbyte(ba); //get the format byte
|
|
//calculate offset into disk image
|
|
dskoff = ((ta * (uint32)(fdc202[fdcnum].fdd[fddnum].maxsec)) + (sa - 1)) * 128;
|
|
for(i=0; i<=((uint32)(fdc202[fdcnum].fdd[fddnum].maxsec) * 128); i++) {
|
|
*(fdc202[fdcnum].fdd[fddnum].buf + (dskoff + i)) = fmtb;
|
|
}
|
|
//*** quick fix. Needs more thought!
|
|
fp = fopen(uptr->filename, "wb"); // write out modified image
|
|
for (i=0; i<uptr->capac; i++) {
|
|
c = *(fdc202[fdcnum].fdd[fddnum].buf + i);
|
|
fputc(c, fp);
|
|
}
|
|
fclose(fp);
|
|
fdc202[fdcnum].rtype = ROK;
|
|
fdc202[fdcnum].intff = 1; //set interrupt FF
|
|
break;
|
|
case DREAD:
|
|
nrptr = 0;
|
|
while(nrptr < nr) {
|
|
//calculate offset into disk image
|
|
dskoff = ((ta * fdc202[fdcnum].fdd[fddnum].maxsec) + (sa - 1)) * 128;
|
|
// sim_printf("\n isbc202-%d: cw=%02X di=%02X nr=%02X ta=%02X sa=%02X ba=%04X dskoff=%06X",
|
|
// fdcnum, cw, di, nr, ta, sa, ba, dskoff);
|
|
for (i=0; i<128; i++) { //copy sector from image to RAM
|
|
data = *(fdc202[fdcnum].fdd[fddnum].buf + (dskoff + i));
|
|
multibus_put_mbyte(ba + i, data);
|
|
}
|
|
sa++;
|
|
ba+=0x80;
|
|
nrptr++;
|
|
}
|
|
fdc202[fdcnum].rtype = ROK;
|
|
fdc202[fdcnum].intff = 1; //set interrupt FF
|
|
break;
|
|
case DWRITE:
|
|
//check for WP
|
|
if(uptr->flags & UNIT_WPMODE) {
|
|
fdc202[fdcnum].rtype = RERR;
|
|
fdc202[fdcnum].rbyte0 = RB0WP;
|
|
fdc202[fdcnum].intff = 1; //set interrupt FF
|
|
sim_printf("\n isbc202-%d: Write protect error 2 on drive %d", fdcnum, fddnum);
|
|
return;
|
|
}
|
|
nrptr = 0;
|
|
while(nrptr < nr) {
|
|
//calculate offset into disk image
|
|
dskoff = ((ta * fdc202[fdcnum].fdd[fddnum].maxsec) + (sa - 1)) * 128;
|
|
// sim_printf("\n isbc202-%d: cw=%02X di=%02X nr=%02X ta=%02X sa=%02X ba=%04X dskoff=%06X",
|
|
// fdcnum, cw, di, nr, ta, sa, ba, dskoff);
|
|
for (i=0; i<128; i++) { //copy sector from image to RAM
|
|
data = multibus_get_mbyte(ba + i);
|
|
*(fdc202[fdcnum].fdd[fddnum].buf + (dskoff + i)) = data;
|
|
}
|
|
sa++;
|
|
ba+=0x80;
|
|
nrptr++;
|
|
}
|
|
//*** quick fix. Needs more thought!
|
|
fp = fopen(uptr->filename, "wb"); // write out modified image
|
|
for (i=0; i<uptr->capac; i++) {
|
|
c = *(fdc202[fdcnum].fdd[fddnum].buf + i);
|
|
fputc(c, fp);
|
|
}
|
|
fclose(fp);
|
|
fdc202[fdcnum].rtype = ROK;
|
|
fdc202[fdcnum].intff = 1; //set interrupt FF
|
|
break;
|
|
default:
|
|
sim_printf("\n isbc202-%d: isbc202_diskio bad di=%02X", fdcnum, di & 0x07);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* end of isbc202.c */
|