f028802bff
- MicroVAX 2000 & VAXstation 2000 - MicroVAX 3100 M10/M20 - MicroVAX 3100 M10e/M20e - InfoServer 100 - InfoServer 150 VXT - VAXstation 3100 M30 - VAXstation 3100 M38 - VAXstation 3100 M76 - VAXstation 4000 VLC - VAXstation 4000 M60 - MicroVAX 3100 M80 - InfoServer 1000
339 lines
14 KiB
C
339 lines
14 KiB
C
/* vax440_defs.h: MicroVAX 4000 model-specific definitions file
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Copyright (c) 2019, Matt Burke
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This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name(s) of the author(s) shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from the author(s).
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This file covers the KA440 ("PVAX2") systems.
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System memory map
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0000 0000 - 00FF FFFF main memory
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0800 0000 - 0803 FFFF secondary cache data store
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2000 0000 - 2001 FFFF DMA map
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2002 0000 - 2002 0003 configuration/test register
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2004 0000 - 2007 FFFF ROM space
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2008 0000 - 2008 001F local register space
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2009 0000 - 2009 007F network address ROM
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200A 0000 - 200A 000F serial line controller
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200B 0000 - 200B 00FF watch chip registers
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200C 0000 - 200C 00BF scsi controller
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200D 0000 - 200D 3FFF ISDN/audio controller
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200E 0000 - 200E 0007 ethernet contoller
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2010 0000 - 2013 FFFF option ROMs
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2010 1800 - 2010 180F memory registers
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2010 1A00 - 2010 1FFF invalidate single
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2020 0000 - 2021 FFFF invalidate filter
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2200 0000 - 2203 FFFF secondary cache tag store
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2300 0000 - 2300 0003 secondary cache control registers
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3680 0000 - 3680 0003 turbochannel registers
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*/
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#ifdef FULL_VAX /* subset VAX */
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#undef FULL_VAX
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#endif
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#ifndef _VAX_440_DEFS_H_
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#define _VAX_440_DEFS_H_ 1
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/* Microcode constructs */
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#if defined (VAX_46) || defined (VAX_47)
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#define VAX4X_SID (18 << 24) /* system ID */
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#else
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#define VAX4X_SID (20 << 24) /* system ID */
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#endif
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#define VAX4X_UREV 14 /* ucode revision */
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#define CON_HLTPIN 0x0200 /* external CPU halt */
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#define CON_PWRUP 0x0300 /* powerup code */
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#define CON_HLTINS 0x0600 /* HALT instruction */
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#define CON_DBLMCK 0x0500 /* Machine check in machine check */
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#define CON_BADPSL 0x4000 /* invalid PSL flag */
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#define CON_MAPON 0x8000 /* mapping on flag */
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#define MCHK_READ 0x80 /* read check */
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#define MCHK_WRITE 0x82 /* write check */
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/* Machine specific IPRs */
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#define MT_CADR 37 /* Cache disable reg */
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#define MT_MCESR 38 /* Machine check error/status reg */
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#define MT_CAER 39 /* Cache error reg */
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#define MT_ACCS 40 /* FPA control */
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#define MT_CONISP 41 /* Console Saved ISP */
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#define MT_CONPC 42 /* Console Saved PC */
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#define MT_CONPSL 43 /* Console Saved PSL */
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#define MT_PCTAG 124 /* Primary cache tag reg */
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#define MT_PCIDX 125 /* Primary cache index reg */
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#define MT_PCERR 126 /* Primary cache error reg */
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#define MT_PCSTS 127 /* Primary cache status reg */
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#define MT_MAX 127 /* last valid IPR */
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/* Cache disable register */
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#define CADR_RW 0xF3
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#define CADR_MBO 0x0C
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/* CPU */
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#if defined (VAX_46) || defined (VAX_48)
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#define CPU_MODEL_MODIFIERS \
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{ MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={MICROVAX|VAXSTATION}", \
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cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" }
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#else
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#define CPU_MODEL_MODIFIERS \
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{ 0 }
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#endif
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/* Memory */
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#define MAXMEMWIDTH 25 /* max mem, std KA440 */
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#define MAXMEMSIZE (1 << MAXMEMWIDTH) /* max mem size */
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#define MAXMEMWIDTH_X 27 /* max mem, KA440 */
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#define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X)
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#define INITMEMSIZE (1 << 24) /* initial memory size */
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#define MEMSIZE (cpu_unit.capac)
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#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
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#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size }, \
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{ UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size }, \
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{ UNIT_MSIZE, (1u << 24) + (1u << 23), NULL, "24M", &cpu_set_size }, \
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{ UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size }, \
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{ UNIT_MSIZE, (1u << 25) + (1u << 23), NULL, "40M", &cpu_set_size }, \
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{ UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size }, \
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{ UNIT_MSIZE, (1u << 25) + (1u << 24) + (1u << 23), NULL, "56M", &cpu_set_size }, \
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{ UNIT_MSIZE, (1u << 26) + (1u << 23), NULL, "72M", &cpu_set_size }, \
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{ UNIT_MSIZE, (1u << 26) + (1u << 24), NULL, "80M", &cpu_set_size }, \
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{ UNIT_MSIZE, (1u << 26) + (1u << 25) + (1u << 24), NULL, "104M", &cpu_set_size }
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/* DMA map */
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#define DMAAWIDTH 17 /* DMA addr width */
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#define DMASIZE (1u << DMAAWIDTH) /* DMA length */
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#define DMAAMASK (DMASIZE - 1) /* DMA addr mask */
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#define DMABASE 0x20000000 /* DMA base */
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/* Config/test register */
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#define CFGSIZE 4 /* CFG length */
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#define CFGBASE 0x20020000 /* CFG base */
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/* Read only memory */
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#define ROMAWIDTH 18 /* ROM addr width */
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#define ROMSIZE (1u << ROMAWIDTH) /* ROM length */
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#define ROMAMASK (ROMSIZE - 1) /* ROM addr mask */
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#define ROMBASE 0x20040000 /* ROM base */
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#define ADDR_IS_ROM(x) ((((uint32) (x)) >= ROMBASE) && \
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(((uint32) (x)) < (ROMBASE + ROMSIZE)))
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/* KA440 board registers */
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#define KAAWIDTH 5 /* REG addr width */
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#define KASIZE (1u << KAAWIDTH) /* REG length */
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#define KABASE 0x20080000 /* REG addr base */
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/* Network address ROM */
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#define NARAWIDTH 5 /* NAR addr width */
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#define NARSIZE (1u << NARAWIDTH) /* NAR length */
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#define NARAMASK (NARSIZE - 1) /* NAR addr mask */
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#define NARBASE 0x20090000 /* NAR base */
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/* Serial line controller */
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#define DZSIZE 0x10 /* DZ length */
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#define DZBASE 0x200A0000 /* DZ base */
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/* Non-volatile RAM - 1KB Bytes long */
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#define NVRAWIDTH 10 /* NVR addr width */
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#define NVRSIZE (1u << NVRAWIDTH) /* NVR length */
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#define NVRAMASK (NVRSIZE - 1) /* NVR addr mask */
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#define NVRBASE 0x200B0000 /* NVR base */
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#define ADDR_IS_NVR(x) ((((uint32) (x)) >= NVRBASE) && \
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(((uint32) (x)) < (NVRBASE + NVRSIZE)))
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/* SCSI disk controller */
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#define RZSIZE 0xC0 /* RZ length */
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#define RZBASE 0x200C0000 /* RZ base */
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/* LANCE Ethernet controller */
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#define XSSIZE 0x8 /* XS length */
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#define XSBASE 0x200E0000 /* XS base */
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/* Option ROMs */
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#define ORAWIDTH 20 /* OR addr width */
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#define ORSIZE (1u << ORAWIDTH) /* OR length */
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#define ORMASK (ORSIZE - 1) /* OR addr mask */
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#define ORBASE 0x20100000 /* OR base */
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/* Other address spaces */
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#define ADDR_IS_IO(x) (0)
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#define ADDR_IS_CDG(x) (0)
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/* Machine specific reserved operand tests (mostly NOPs) */
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#define ML_PA_TEST(r)
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#define ML_LR_TEST(r)
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#define ML_SBR_TEST(r)
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#define ML_PXBR_TEST(r)
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#define LP_AST_TEST(r)
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#define LP_MBZ84_TEST(r)
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#define LP_MBZ92_TEST(r)
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#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
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/* Common CSI flags */
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#define CSR_V_GO 0 /* go */
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#define CSR_V_IE 6 /* interrupt enable */
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#define CSR_V_DONE 7 /* done */
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#define CSR_V_BUSY 11 /* busy */
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#define CSR_V_ERR 15 /* error */
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#define CSR_GO (1u << CSR_V_GO)
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#define CSR_IE (1u << CSR_V_IE)
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#define CSR_DONE (1u << CSR_V_DONE)
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#define CSR_BUSY (1u << CSR_V_BUSY)
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#define CSR_ERR (1u << CSR_V_ERR)
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/* Timers */
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#define TMR_CLK 0 /* 100Hz clock */
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/* I/O system definitions */
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#define MT_MAXFR (1 << 16) /* magtape max rec */
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#define DEV_V_4XX (DEV_V_UF + 0) /* KA4xx I/O */
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#define DEV_4XX (1u << DEV_V_4XX)
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#define DEV_RDX 16 /* default device radix */
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/* Device information block */
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#define VEC_DEVMAX 4 /* max device vec */
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typedef struct {
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int32 rom_index; /* option ROM index */
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uint8 *rom_array; /* option ROM code */
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t_addr rom_size; /* option ROM size */
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} DIB;
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/* Within each IPL, priority is left to right */
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/* IPL 14 */
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#define INT_V_SC 0 /* storage controller */
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#define INT_V_XS1 1 /* network */
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#define INT_V_VC1 2 /* video primary */
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#define INT_V_VC2 3 /* video secondary */
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#define INT_V_DZTX 4 /* serial transmitter */
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#define INT_V_DZRX 5 /* serial receiver */
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#define INT_V_SP 6 /* audio/ISDN */
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#define INT_V_CO 7 /* sync comm (PV21X-DA) */
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#define INT_SC (1u << INT_V_SC)
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#define INT_XS1 (1u << INT_V_XS1)
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#define INT_VC1 (1u << INT_V_VC1)
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#define INT_VC2 (1u << INT_V_VC2)
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#define INT_DZTX (1u << INT_V_DZTX)
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#define INT_DZRX (1u << INT_V_DZRX)
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#define INT_SP (1u << INT_V_SP)
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#define INT_CO (1u << INT_V_CO)
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#define IPL_CLK 0x16
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#define IPL_HW 0x14 /* hwre level */
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#define IPL_SC (0x14 - IPL_HMIN)
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#define IPL_XS1 (0x14 - IPL_HMIN)
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#define IPL_DZTX (0x14 - IPL_HMIN)
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#define IPL_DZRX (0x14 - IPL_HMIN)
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#define IPL_HMIN IPL_HW
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#define IPL_HMAX IPL_HW
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#define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */
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#define IPL_SMAX 0xF /* highest swre level */
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/* Device vectors */
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#define VEC_QBUS 0 /* Not a Qbus system */
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#define VEC_Q 0
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/* Interrupt macros */
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#define IREQ(dv) int_req[0]
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#define SET_INT(dv) int_req[0] = int_req[0] | (INT_##dv)
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#define CLR_INT(dv) int_req[0] = int_req[0] & ~(INT_##dv)
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#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
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/* System model */
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extern int32 sys_model;
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/* Machine specific definitions - DZ */
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#define DZ_L3C 1 /* line 3 console */
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/* Machine specific definitions - OR */
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#define OR_COUNT 4 /* max number of option ROMs */
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/* Machine specific definitions - RZ94 */
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#define RZ_SCSI_ID 6 /* initiator SCSI id */
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#define RZ_READB Map_ReadB
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#define RZ_READW Map_ReadW
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#define RZ_WRITEB Map_WriteB
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#define RZ_WRITEW Map_WriteW
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/* Machine specific definitions - XS */
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#define XS_ROM_INDEX -1 /* no ROM needed */
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#define XS_FLAGS 0
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#define XS_READB Map_ReadB
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#define XS_READW Map_ReadW
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#define XS_WRITEB Map_WriteB
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#define XS_WRITEW Map_WriteW
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/* Function prototypes for I/O */
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int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf);
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int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf);
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int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf);
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int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf);
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/* Function prototypes for system-specific unaligned support */
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int32 ReadIOU (uint32 pa, int32 lnt);
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int32 ReadRegU (uint32 pa, int32 lnt);
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void WriteIOU (uint32 pa, int32 val, int32 lnt);
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void WriteRegU (uint32 pa, int32 val, int32 lnt);
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t_stat auto_config (const char *name, int32 nctrl);
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/* Function prototypes for virtual and physical memory interface (inlined) */
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#include "vax_mmu.h"
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#endif
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