268 lines
12 KiB
C
268 lines
12 KiB
C
/*************************************************************************
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* *
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* $Id: s100_mdriveh.c 1940 2008-06-13 05:28:57Z hharte $ *
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* *
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* Copyright (c) 2007-2008 Howard M. Harte. *
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* http://www.hartetec.com *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining *
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* a copy of this software and associated documentation files (the *
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* "Software"), to deal in the Software without restriction, including *
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* without limitation the rights to use, copy, modify, merge, publish, *
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* distribute, sublicense, and/or sell copies of the Software, and to *
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* permit persons to whom the Software is furnished to do so, subject to *
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* the following conditions: *
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* *
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* The above copyright notice and this permission notice shall be *
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* included in all copies or substantial portions of the Software. *
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, *
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF *
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND *
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* NONINFRINGEMENT. IN NO EVENT SHALL HOWARD M. HARTE BE LIABLE FOR ANY *
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, *
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE *
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. *
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* *
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* Except as contained in this notice, the name of Howard M. Harte shall *
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* not be used in advertising or otherwise to promote the sale, use or *
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* other dealings in this Software without prior written authorization *
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* Howard M. Harte. *
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* *
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* SIMH Interface based on altairz80_hdsk.c, by Peter Schorn. *
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* *
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* Module Description: *
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* CompuPro M-DRIVE/H Controller module for SIMH. *
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* *
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* Environment: *
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* User mode only *
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* *
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*************************************************************************/
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/*#define DBG_MSG */
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#include "altairz80_defs.h"
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#if defined (_WIN32)
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#include <windows.h>
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#endif
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#ifdef DBG_MSG
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#define DBG_PRINT(args) sim_printf args
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#else
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#define DBG_PRINT(args)
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#endif
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/* Debug flags */
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#define SEEK_MSG (1 << 0)
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#define RD_DATA_MSG (1 << 1)
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#define WR_DATA_MSG (1 << 2)
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#define VERBOSE_MSG (1 << 3)
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#define MDRIVEH_MAX_DRIVES 8
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typedef struct {
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PNP_INFO pnp; /* Plug and Play */
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uint32 dma_addr; /* DMA Transfer Address */
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UNIT uptr[MDRIVEH_MAX_DRIVES];
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uint8 *storage[MDRIVEH_MAX_DRIVES];
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} MDRIVEH_INFO;
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static MDRIVEH_INFO mdriveh_info_data = { { 0x0, 0, 0xC6, 2 } };
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static MDRIVEH_INFO *mdriveh_info = &mdriveh_info_data;
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extern uint32 PCX;
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extern t_stat set_iobase(UNIT *uptr, int32 val, char *cptr, void *desc);
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extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, void *desc);
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extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
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int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
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#define UNIT_V_MDRIVEH_WLK (UNIT_V_UF + 0) /* write locked */
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#define UNIT_MDRIVEH_WLK (1 << UNIT_V_MDRIVEH_WLK)
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#define UNIT_V_MDRIVEH_VERBOSE (UNIT_V_UF + 1) /* verbose mode, i.e. show error messages */
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#define UNIT_MDRIVEH_VERBOSE (1 << UNIT_V_MDRIVEH_VERBOSE)
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#define MDRIVEH_CAPACITY (512 * 1000) /* Default M-DRIVE/H Capacity */
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#define MDRIVEH_NONE 0
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static t_stat mdriveh_reset(DEVICE *mdriveh_dev);
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static int32 mdrivehdev(const int32 port, const int32 io, const int32 data);
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static uint8 MDRIVEH_Read(const uint32 Addr);
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static uint8 MDRIVEH_Write(const uint32 Addr, uint8 cData);
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static UNIT mdriveh_unit[] = {
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{ UDATA (NULL, UNIT_FIX + UNIT_DISABLE + UNIT_ROABLE, MDRIVEH_CAPACITY) },
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{ UDATA (NULL, UNIT_FIX + UNIT_DISABLE + UNIT_DIS + UNIT_ROABLE, MDRIVEH_CAPACITY) },
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{ UDATA (NULL, UNIT_FIX + UNIT_DISABLE + UNIT_DIS + UNIT_ROABLE, MDRIVEH_CAPACITY) },
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{ UDATA (NULL, UNIT_FIX + UNIT_DISABLE + UNIT_DIS + UNIT_ROABLE, MDRIVEH_CAPACITY) },
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{ UDATA (NULL, UNIT_FIX + UNIT_DISABLE + UNIT_DIS + UNIT_ROABLE, MDRIVEH_CAPACITY) },
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{ UDATA (NULL, UNIT_FIX + UNIT_DISABLE + UNIT_DIS + UNIT_ROABLE, MDRIVEH_CAPACITY) },
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{ UDATA (NULL, UNIT_FIX + UNIT_DISABLE + UNIT_DIS + UNIT_ROABLE, MDRIVEH_CAPACITY) },
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{ UDATA (NULL, UNIT_FIX + UNIT_DISABLE + UNIT_DIS + UNIT_ROABLE, MDRIVEH_CAPACITY) }
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};
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static REG mdriveh_reg[] = {
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{ NULL }
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};
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#define MDRIVEH_NAME "Compupro Memory Drive MDRIVEH"
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static MTAB mdriveh_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE",
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&set_iobase, &show_iobase, NULL, "Sets disk controller I/O base address" },
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{ UNIT_MDRIVEH_WLK, 0, "WRTENB", "WRTENB",
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NULL, NULL, NULL,
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"Enables " MDRIVEH_NAME "n for writing" },
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{ UNIT_MDRIVEH_WLK, UNIT_MDRIVEH_WLK, "WRTLCK", "WRTLCK",
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NULL, NULL, NULL,
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"Locks " MDRIVEH_NAME "n for writing" },
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/* quiet, no warning messages */
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{ UNIT_MDRIVEH_VERBOSE, 0, "QUIET", "QUIET",
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NULL, NULL, NULL, "No verbose messages for unit " MDRIVEH_NAME "n" },
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/* verbose, show warning messages */
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{ UNIT_MDRIVEH_VERBOSE, UNIT_MDRIVEH_VERBOSE, "VERBOSE", "VERBOSE",
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NULL, NULL, NULL, "Verbose messages for unit " MDRIVEH_NAME "n" },
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{ 0 }
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};
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/* Debug Flags */
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static DEBTAB mdriveh_dt[] = {
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{ "SEEK", SEEK_MSG, "Seek messages" },
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{ "READ", RD_DATA_MSG, "Read messages" },
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{ "WRITE", WR_DATA_MSG, "Write messages" },
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{ "VERBOSE", VERBOSE_MSG, "Verbose messages" },
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{ NULL, 0 }
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};
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DEVICE mdriveh_dev = {
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"MDRIVEH", mdriveh_unit, mdriveh_reg, mdriveh_mod,
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MDRIVEH_MAX_DRIVES, 10, 31, 1, MDRIVEH_MAX_DRIVES, MDRIVEH_MAX_DRIVES,
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NULL, NULL, &mdriveh_reset,
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NULL, NULL, NULL,
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&mdriveh_info_data, (DEV_DISABLE | DEV_DIS | DEV_DEBUG), 0,
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mdriveh_dt, NULL, MDRIVEH_NAME
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};
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/* Reset routine */
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static t_stat mdriveh_reset(DEVICE *dptr)
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{
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uint8 i;
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PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;
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if(dptr->flags & DEV_DIS) { /* Disconnect ROM and I/O Ports */
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sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &mdrivehdev, TRUE);
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} else {
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/* Connect MDRIVEH at base address */
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if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &mdrivehdev, FALSE) != 0) {
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sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
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return SCPE_ARG;
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}
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}
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for(i=0; i<MDRIVEH_MAX_DRIVES; i++) {
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mdriveh_info->uptr[i] = dptr->units[i];
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if((dptr->flags & DEV_DIS) || (dptr->units[i].flags & UNIT_DIS)) {
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if (dptr->units[i].flags & UNIT_MDRIVEH_VERBOSE)
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sim_printf("MDRIVEH: Unit %d disabled", i);
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if(mdriveh_info->storage[i] != NULL) {
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if (dptr->units[i].flags & UNIT_MDRIVEH_VERBOSE)
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sim_printf(", freed 0x%p\n", mdriveh_info->storage[i]);
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free(mdriveh_info->storage[i]);
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mdriveh_info->storage[i] = NULL;
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} else if (dptr->units[i].flags & UNIT_MDRIVEH_VERBOSE) {
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sim_printf(".\n");
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}
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} else {
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if(mdriveh_info->storage[i] == NULL) {
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mdriveh_info->storage[i] = calloc(1, 524288);
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}
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if (dptr->units[i].flags & UNIT_MDRIVEH_VERBOSE)
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sim_printf("MDRIVEH: Unit %d enabled, 512K at 0x%p\n", i, mdriveh_info->storage[i]);
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}
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}
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return SCPE_OK;
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}
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static int32 mdrivehdev(const int32 port, const int32 io, const int32 data)
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{
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DBG_PRINT(("MDRIVEH: " ADDRESS_FORMAT " IO %s, Port %02x" NLP, PCX, io ? "WR" : "RD", port));
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if(io) {
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MDRIVEH_Write(port, data);
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return 0;
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} else {
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return(MDRIVEH_Read(port));
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}
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}
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#define MDRIVEH_DATA 0 /* R=Drive Status Register / W=DMA Address Register */
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#define MDRIVEH_ADDR 1 /* R=Unused / W=Motor Control Register */
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static uint8 MDRIVEH_Read(const uint32 Addr)
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{
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uint8 cData;
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uint8 unit;
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uint32 offset;
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cData = 0xFF; /* default is High-Z Data */
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switch(Addr & 0x1) {
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case MDRIVEH_ADDR:
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sim_debug(VERBOSE_MSG, &mdriveh_dev, "MDRIVEH: " ADDRESS_FORMAT " RD Addr = 0x%02x\n", PCX, cData);
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break;
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case MDRIVEH_DATA:
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unit = (mdriveh_info->dma_addr & 0x380000) >> 19;
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offset = mdriveh_info->dma_addr & 0x7FFFF;
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if(mdriveh_info->storage[unit] != NULL) {
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cData = mdriveh_info->storage[unit][offset];
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}
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sim_debug(RD_DATA_MSG, &mdriveh_dev, "MDRIVEH: " ADDRESS_FORMAT " RD Data [%x:%05x] = 0x%02x\n", PCX, unit, offset, cData);
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/* Increment M-DRIVE/H Data Address */
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mdriveh_info->dma_addr++;
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mdriveh_info->dma_addr &= 0x3FFFFF;
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break;
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}
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return (cData);
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}
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static uint8 MDRIVEH_Write(const uint32 Addr, uint8 cData)
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{
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uint8 result = 0;
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uint8 unit;
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uint32 offset;
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switch(Addr & 0x1) {
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case MDRIVEH_ADDR:
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mdriveh_info->dma_addr <<= 8;
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mdriveh_info->dma_addr &= 0x003FFF00;
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mdriveh_info->dma_addr |= cData;
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sim_debug(SEEK_MSG, &mdriveh_dev, "MDRIVEH: " ADDRESS_FORMAT " DMA Address=%06x\n", PCX, mdriveh_info->dma_addr);
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break;
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case MDRIVEH_DATA:
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unit = (mdriveh_info->dma_addr & 0x380000) >> 19;
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offset = mdriveh_info->dma_addr & 0x7FFFF;
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if(mdriveh_info->storage[unit] != NULL) {
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if(mdriveh_info->uptr[unit].flags & UNIT_MDRIVEH_WLK) {
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sim_debug(WR_DATA_MSG, &mdriveh_dev, "MDRIVEH: " ADDRESS_FORMAT " WR Data [%x:%05x] = Unit Write Locked\n", PCX, unit, offset);
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} else {
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sim_debug(WR_DATA_MSG, &mdriveh_dev, "MDRIVEH: " ADDRESS_FORMAT " WR Data [%x:%05x] = 0x%02x\n", PCX, unit, offset, cData);
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mdriveh_info->storage[unit][offset] = cData;
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}
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} else {
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sim_debug(WR_DATA_MSG, &mdriveh_dev, "MDRIVEH: " ADDRESS_FORMAT " WR Data [%x:%05x] = Unit OFFLINE\n", PCX, unit, offset);
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}
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/* Increment M-DRIVE/H Data Address */
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mdriveh_info->dma_addr++;
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mdriveh_info->dma_addr &= 0x3FFFFF;
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break;
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}
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return (result);
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}
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