6ce8d99cd8
The goals here being to simplify calling code while getting consistent output delivered everywhere it may be useful. Modified most places which explicitly used sim_log or merely called printf to now avoid doing that and merely call sim_printf().
332 lines
12 KiB
C
332 lines
12 KiB
C
/* vax780_mem.c: VAX 11/780 memory controllers
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Copyright (c) 2004-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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This module contains the VAX 11/780 system-specific registers and devices.
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mctl0, mctl1 MS780C/E memory controllers
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*/
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#include "vax_defs.h"
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/* Memory controller register A */
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#define MCRA_OF 0x0
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#define MCRA_SUMM 0x00100000 /* err summ (MS780E) */
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#define MCRA_M_SIZE 0x00007E00 /* array size - field */
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#define MCRA_V_SIZE 9
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#define MCRA_ILVE 0x00000100 /* interleave wr enab */
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#define MCRA_M_TYPE 0x000000F8 /* type */
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#define MCRA_C_TYPE_16K 0x00000010 /* 16k uninterleaved (256kb arrays) */
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#define MCRA_C_TYPE_4K 0x00000008 /* 4k uninterleaved (64kb arrays) */
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#define MCRA_E_TYPE_256K 0x00000070 /* 256k uninterleaved (4096kb arrays) */
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#define MCRA_E_TYPE_64K 0x00000068 /* 64k uninterleaved (1024kb arrays) */
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#define MCRA_E_TYPE 0x0000006A /* 256k upper + lower */
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#define MCRA_ILV 0x00000007 /* interleave */
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#define MCRA_RD (0x00107FFF|SBI_FAULTS)
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#define MCRA_WR 0x00000100
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/* Memory controller register B */
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#define MCRB_OF 0x1
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#define MCRB_FP 0xF0000000 /* file pointers */
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#define MCRB_V_SA 15 /* start addr */
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#define MCRB_M_SA 0x1FFF
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#define MCRB_SA (MCRB_M_SA << MCRB_V_SA)
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#define MCRB_SAE 0x00004000 /* start addr wr enab */
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#define MCRB_INIT 0x00003000 /* init state */
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#define MCRB_REF 0x00000400 /* refresh */
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#define MCRB_ECC 0x000003FF /* ECC for diags */
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#define MCRB_RD 0xFFFFF7FF
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#define MCRB_WR 0x000043FF
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/* Memory controller register C,D */
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#define MCRC_OF 0x2
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#define MCRD_OF 0x3
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#define MCRC_DCRD 0x40000000 /* disable CRD */
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#define MCRC_HER 0x20000000 /* high error rate */
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#define MCRC_ERL 0x10000000 /* log error */
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#define MCRC_C_ER 0x0FFFFFFF /* MS780C error */
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#define MCRC_E_PE1 0x00080000 /* MS780E par ctl 1 */
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#define MCRC_E_PE0 0x00040000 /* MS780E par ctl 0 */
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#define MCRC_E_CRD 0x00000200 /* MS780E CRD */
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#define MCRC_E_PEW 0x00000100 /* MS780E par err wr */
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#define MCRC_E_USEQ 0x00000080 /* MS780E seq err */
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#define MCRC_C_RD 0x7FFFFFFF
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#define MCRC_E_RD 0x700C0380
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#define MCRC_WR 0x40000000
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#define MCRC_C_W1C 0x30000000
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#define MCRC_E_W1C 0x300C0380
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#define MCRROM_OF 0x400
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uint32 mcr_a[MCTL_NUM];
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uint32 mcr_b[MCTL_NUM];
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uint32 mcr_c[MCTL_NUM];
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uint32 mcr_d[MCTL_NUM];
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uint32 rom_lw[MCTL_NUM][ROMSIZE >> 2];
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extern UNIT cpu_unit;
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t_stat mctl_reset (DEVICE *dptr);
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char *mctl_description (DEVICE *dptr);
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t_stat mctl_rdreg (int32 *val, int32 pa, int32 mode);
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t_stat mctl_wrreg (int32 val, int32 pa, int32 mode);
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/* MCTLx data structures
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mctlx_dev MCTLx device descriptor
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mctlx_unit MCTLx unit
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mctlx_reg MCTLx register list
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*/
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DIB mctl0_dib = { TR_MCTL0, 0, &mctl_rdreg, &mctl_wrreg, 0 };
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UNIT mctl0_unit = { UDATA (NULL, 0, 0) };
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REG mctl0_reg[] = {
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{ HRDATA (CRA, mcr_a[0], 32) },
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{ HRDATA (CRB, mcr_b[0], 32) },
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{ HRDATA (CRC, mcr_c[0], 32) },
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{ HRDATA (CRD, mcr_d[0], 32) },
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{ BRDATA (ROM, rom_lw[0], 16, 32, ROMSIZE >> 2) },
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{ NULL }
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};
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MTAB mctl0_mod[] = {
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{ MTAB_XTD|MTAB_VDV, TR_MCTL0, "NEXUS", NULL,
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NULL, &show_nexus, NULL, "Display nexus" },
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{ 0 }
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};
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DIB mctl1_dib = { TR_MCTL1, 0, &mctl_rdreg, &mctl_wrreg, 0 };
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UNIT mctl1_unit = { UDATA (NULL, 0, 0) };
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MTAB mctl1_mod[] = {
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{ MTAB_XTD|MTAB_VDV, TR_MCTL1, "NEXUS", NULL,
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NULL, &show_nexus, NULL, "Display nexus" },
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{ 0 } };
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REG mctl1_reg[] = {
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{ HRDATA (CRA, mcr_a[1], 32) },
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{ HRDATA (CRB, mcr_b[1], 32) },
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{ HRDATA (CRC, mcr_c[1], 32) },
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{ HRDATA (CRD, mcr_d[1], 32) },
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{ BRDATA (ROM, rom_lw[1], 16, 32, ROMSIZE >> 2) },
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{ NULL }
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};
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DEVICE mctl_dev[] = {
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{
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"MCTL0", &mctl0_unit, mctl0_reg, mctl0_mod,
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1, 16, 16, 1, 16, 8,
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NULL, NULL, &mctl_reset,
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NULL, NULL, NULL,
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&mctl0_dib, DEV_NEXUS, 0,
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NULL, NULL, NULL, NULL, NULL, NULL,
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&mctl_description
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},
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{
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"MCTL1", &mctl1_unit, mctl1_reg, mctl1_mod,
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1, 16, 16, 1, 16, 8,
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NULL, NULL, &mctl_reset,
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NULL, NULL, NULL,
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&mctl1_dib, DEV_NEXUS, 0,
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NULL, NULL, NULL, NULL, NULL, NULL,
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&mctl_description
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}
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};
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/* Memory controller register read */
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t_stat mctl_rdreg (int32 *val, int32 pa, int32 lnt)
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{
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int32 mctl, ofs;
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t_bool extmem = MEMSIZE > MAXMEMSIZE;
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if ((pa & 3) || (lnt != L_LONG)) { /* unaligned or not lw? */
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sim_printf (">>MCTL: invalid adapter read mask, pa = %X, lnt = %d\r\n", pa, lnt);
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sbi_set_errcnf (); /* err confirmation */
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return SCPE_OK;
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}
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mctl = NEXUS_GETNEX (pa) - TR_MCTL0; /* get mctl num */
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ofs = NEXUS_GETOFS (pa); /* get offset */
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if (ofs >= MCRROM_OF) { /* ROM? */
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*val = rom_lw[mctl][ofs - MCRROM_OF]; /* get lw */
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return SCPE_OK;
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}
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switch (ofs) {
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case MCRA_OF: /* CR A */
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*val = mcr_a[mctl] & MCRA_RD;
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break;
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case MCRB_OF: /* CR B */
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*val = (mcr_b[mctl] & MCRB_RD) | MCRB_INIT;
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break;
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case MCRC_OF: /* CR C */
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*val = mcr_c[mctl] & (extmem? MCRC_E_RD: MCRC_C_RD);
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break;
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case MCRD_OF: /* CR D */
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if (!extmem) /* MS780E only */
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return SCPE_NXM;
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*val = mcr_d[mctl] & MCRC_E_RD;
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break;
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default:
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return SCPE_NXM;
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}
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return SCPE_OK;
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}
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/* Memory controller register write */
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t_stat mctl_wrreg (int32 val, int32 pa, int32 lnt)
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{
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int32 mctl, ofs, mask;
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t_bool extmem = MEMSIZE > MAXMEMSIZE;
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if ((pa & 3) || (lnt != L_LONG)) { /* unaligned or not lw? */
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sim_printf (">>MCTL: invalid adapter write mask, pa = %X, lnt = %d\r\n", pa, lnt);
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sbi_set_errcnf (); /* err confirmation */
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return SCPE_OK;
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}
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mctl = NEXUS_GETNEX (pa) - TR_MCTL0; /* get mctl num */
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ofs = NEXUS_GETOFS (pa); /* get offset */
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switch (ofs) {
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case MCRA_OF: /* CR A */
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mask = MCRA_WR | ((val & MCRA_ILVE)? MCRA_ILV: 0);
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mcr_a[mctl] = (mcr_a[mctl] & ~mask) | (val & mask);
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break;
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case MCRB_OF: /* CR B */
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mask = MCRB_WR | ((val & MCRB_SAE)? MCRB_SA: 0);
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mcr_b[mctl] = (mcr_b[mctl] & ~mask) | (val & mask);
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break;
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case MCRC_OF: /* CR C */
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mcr_c[mctl] = ((mcr_c[mctl] & ~MCRC_WR) | (val & MCRC_WR)) &
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~(val & (extmem? MCRC_E_W1C: MCRC_C_W1C));
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break;
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case MCRD_OF: /* CR D */
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if (!extmem) /* MS780E only */
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return SCPE_NXM;
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mcr_d[mctl] = ((mcr_d[mctl] & ~MCRC_WR) | (val & MCRC_WR)) &
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~(val & MCRC_E_W1C);
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break;
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default:
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return SCPE_NXM;
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}
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return SCPE_OK;
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}
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/* Used by CPU and loader */
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void rom_wr_B (int32 pa, int32 val)
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{
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uint32 mctl = NEXUS_GETNEX (pa) - TR_MCTL0; /* get mctl num */
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uint32 ofs = NEXUS_GETOFS (pa) - MCRROM_OF; /* get offset */
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int32 sc = (pa & 3) << 3;
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rom_lw[mctl][ofs] = ((val & 0xFF) << sc) | (rom_lw[mctl][ofs] & ~(0xFF << sc));
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return;
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}
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/* MEMCTL reset */
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t_stat mctl_reset (DEVICE *dptr)
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{
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int32 i, amb, akb;
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t_bool extmem = MEMSIZE > MAXMEMSIZE;
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amb = (int32) (MEMSIZE / MCTL_NUM) >> 20; /* array size MB */
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akb = (int32) (MEMSIZE / MCTL_NUM) >> 10; /* array size KB */
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for (i = 0; i < MCTL_NUM; i++) {
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if (extmem) /* Need MS780E? */
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mcr_a[i] = ((amb - 1) << MCRA_V_SIZE) | ((amb <= 16) ? MCRA_E_TYPE_64K : MCRA_E_TYPE_256K);
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else /* Use MS780C */
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mcr_a[i] = (((akb >> 6) - 1) << MCRA_V_SIZE) | ((akb <= 1024) ? MCRA_C_TYPE_4K : MCRA_C_TYPE_16K);
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mcr_b[i] = MCRB_INIT | ((i * akb) << (MCRB_V_SA - 6));
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mcr_c[i] = 0;
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mcr_d[i] = 0;
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}
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return SCPE_OK;
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}
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char *mctl_description (DEVICE *dptr)
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{
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static char buf[64];
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sprintf (buf, "Memory controller %d", (int)(dptr-mctl_dev));
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return buf;
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}
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t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, void* desc)
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{
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struct {
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uint32 capacity;
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char *option;
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} boards[] = {
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{ 4096, "MS780-JD M8374 array"},
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{ 1024, "MS780-FD M8373 array"},
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{ 256, "MS780-C M8210 array"},
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{ 64, "MS780-C M8211 array"},
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{ 0, NULL}};
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uint32 i, slot, bd;
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for (i = 0; i < MCTL_NUM; i++) {
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uint32 baseaddr = ((mcr_b[i] & MCRB_SA) << 1);
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fprintf (st, "Memory Controller %d - MS780-%s\n", i, ((mcr_a[i]&MCRA_M_TYPE) >> 5) ? "E" : "C");
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switch (mcr_a[i]&MCRA_M_TYPE) {
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case MCRA_C_TYPE_4K:
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bd = 3; /* 4kbit chips, 64Kbyte arrays */
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break;
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case MCRA_C_TYPE_16K:
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bd = 2; /* 16kbit chips, 256Kbyte arrays */
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break;
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case MCRA_E_TYPE_64K:
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bd = 1; /* 64kbit chips, 1Mbyte arrays */
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break;
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case MCRA_E_TYPE_256K:
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bd = 0; /* 256kbit chips, 4Mbyte arrays */
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break;
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}
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for (slot=0; slot<=((mcr_a[i]&MCRA_M_SIZE)>>MCRA_V_SIZE); slot += ((mcr_a[i]&MCRA_C_TYPE_4K)? 1 : 4)) {
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if (boards[bd].capacity)
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fprintf(st, "Memory slot %d (@0x%08x): %3d %sbytes (%s)\n", slot, baseaddr, boards[bd].capacity/((boards[bd].capacity>=1024) ? 1024 : 1), (boards[bd].capacity>=1024) ? "M" : "K", boards[bd].option);
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baseaddr += boards[bd].capacity<<10;
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}
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}
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return SCPE_OK;
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}
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