298 lines
10 KiB
C
298 lines
10 KiB
C
/* pdp10_tim.c: PDP-10 tim subsystem simulator
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Copyright (c) 1993-2012, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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tim timer subsystem
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18-Apr-12 RMS Removed absolute scheduling on reset
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18-Jun-07 RMS Added UNIT_IDLE flag
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03-Nov-06 RMS Rewritten to support idling
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29-Oct-06 RMS Added clock coscheduling function
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02-Feb-04 RMS Exported variables needed by Ethernet simulator
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29-Jan-02 RMS New data structures
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06-Jan-02 RMS Added enable/disable support
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02-Dec-01 RMS Fixed bug in ITS PC sampling (found by Dave Conroy)
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31-Aug-01 RMS Changed int64 to t_int64 for Windoze
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17-Jul-01 RMS Moved function prototype
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04-Jul-01 RMS Added DZ11 support
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*/
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#include "pdp10_defs.h"
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#include <time.h>
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/* Invariants */
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#define TIM_HW_FREQ 4100000 /* 4.1Mhz */
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#define TIM_HWRE_MASK 07777
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#define UNIT_V_Y2K (UNIT_V_UF + 0) /* Y2K compliant OS */
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#define UNIT_Y2K (1u << UNIT_V_Y2K)
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/* Clock mode TOPS-10/ITS */
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#define TIM_TPS_T10 60
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#define TIM_WAIT_T10 8000
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#define TIM_MULT_T10 1
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#define TIM_ITS_QUANT (TIM_HW_FREQ / TIM_TPS_T10)
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/* Clock mode TOPS-20/KLAD */
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#define TIM_TPS_T20 1001
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#define TIM_WAIT_T20 500
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#define TIM_MULT_T20 16
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/* Probability function for TOPS-20 idlelock */
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#define PROB(x) (((rand() * 100) / RAND_MAX) >= (x))
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d10 tim_base[2] = { 0, 0 }; /* 71b timebase */
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d10 tim_ttg = 0; /* time to go */
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d10 tim_period = 0; /* period */
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d10 quant = 0; /* ITS quantum */
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int32 tim_mult = TIM_MULT_T10; /* tmxr poll mult */
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int32 tim_t20_prob = 33; /* TOPS-20 prob */
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/* Exported variables */
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int32 clk_tps = TIM_TPS_T10; /* clock ticks/sec */
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int32 tmr_poll = TIM_WAIT_T10; /* clock poll */
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int32 tmxr_poll = TIM_WAIT_T10 * TIM_MULT_T10; /* term mux poll */
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extern int32 apr_flg, pi_act;
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extern UNIT cpu_unit;
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extern d10 pcst;
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extern a10 pager_PC;
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extern int32 t20_idlelock;
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DEVICE tim_dev;
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t_stat tcu_rd (int32 *data, int32 PA, int32 access);
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t_stat tim_svc (UNIT *uptr);
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t_stat tim_reset (DEVICE *dptr);
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void tim_incr_base (d10 *base, d10 incr);
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extern d10 Read (a10 ea, int32 prv);
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extern d10 ReadM (a10 ea, int32 prv);
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extern void Write (a10 ea, d10 val, int32 prv);
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extern void WriteP (a10 ea, d10 val);
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extern int32 pi_eval (void);
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extern t_stat wr_nop (int32 data, int32 PA, int32 access);
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/* TIM data structures
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tim_dev TIM device descriptor
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tim_unit TIM unit descriptor
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tim_reg TIM register list
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*/
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DIB tcu_dib = { IOBA_TCU, IOLN_TCU, &tcu_rd, &wr_nop, 0 };
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UNIT tim_unit = { UDATA (&tim_svc, UNIT_IDLE, 0), TIM_WAIT_T10 };
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REG tim_reg[] = {
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{ BRDATA (TIMEBASE, tim_base, 8, 36, 2) },
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{ ORDATA (TTG, tim_ttg, 36) },
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{ ORDATA (PERIOD, tim_period, 36) },
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{ ORDATA (QUANT, quant, 36) },
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{ DRDATA (TIME, tim_unit.wait, 24), REG_NZ + PV_LEFT },
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{ DRDATA (PROB, tim_t20_prob, 6), REG_NZ + PV_LEFT + REG_HIDDEN },
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{ DRDATA (POLL, tmr_poll, 32), REG_HRO + PV_LEFT },
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{ DRDATA (MUXPOLL, tmxr_poll, 32), REG_HRO + PV_LEFT },
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{ DRDATA (MULT, tim_mult, 6), REG_HRO + PV_LEFT },
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{ DRDATA (TPS, clk_tps, 12), REG_HRO + PV_LEFT },
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{ NULL }
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};
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MTAB tim_mod[] = {
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{ UNIT_Y2K, 0, "non Y2K OS", "NOY2K", NULL },
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{ UNIT_Y2K, UNIT_Y2K, "Y2K OS", "Y2K", NULL },
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{ MTAB_XTD|MTAB_VDV, 000, "ADDRESS", NULL,
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NULL, &show_addr, NULL },
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{ 0 }
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};
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DEVICE tim_dev = {
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"TIM", &tim_unit, tim_reg, tim_mod,
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1, 0, 0, 0, 0, 0,
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NULL, NULL, &tim_reset,
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NULL, NULL, NULL,
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&tcu_dib, DEV_UBUS
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};
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/* Timer instructions */
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/* Timer - if the timer is running at less than hardware frequency,
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need to interpolate the value by calculating how much of the current
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clock tick has elapsed, and what that equates to in msec. */
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t_bool rdtim (a10 ea, int32 prv)
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{
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d10 tempbase[2];
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ReadM (INCA (ea), prv); /* check 2nd word */
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tempbase[0] = tim_base[0]; /* copy time base */
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tempbase[1] = tim_base[1];
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if (tim_mult != TIM_MULT_T20) { /* interpolate? */
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int32 used;
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d10 incr;
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used = tmr_poll - (sim_activate_time (&tim_unit) - 1);
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incr = (d10) (((double) used * TIM_HW_FREQ) /
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((double) tmr_poll * (double) clk_tps));
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tim_incr_base (tempbase, incr);
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}
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tempbase[0] = tempbase[0] & ~((d10) TIM_HWRE_MASK); /* clear low 12b */
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Write (ea, tempbase[0], prv);
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Write (INCA(ea), tempbase[1], prv);
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return FALSE;
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}
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t_bool wrtim (a10 ea, int32 prv)
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{
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tim_base[0] = Read (ea, prv);
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tim_base[1] = CLRS (Read (INCA (ea), prv));
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return FALSE;
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}
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t_bool rdint (a10 ea, int32 prv)
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{
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Write (ea, tim_period, prv);
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return FALSE;
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}
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t_bool wrint (a10 ea, int32 prv)
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{
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tim_period = Read (ea, prv);
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tim_ttg = tim_period;
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return FALSE;
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}
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/* Timer service - the timer is only serviced when the 'ttg' register
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has reached 0 based on the expected frequency of clock interrupts. */
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t_stat tim_svc (UNIT *uptr)
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{
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if (cpu_unit.flags & UNIT_KLAD) /* diags? */
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tmr_poll = uptr->wait; /* fixed clock */
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else tmr_poll = sim_rtc_calb (clk_tps); /* else calibrate */
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sim_activate (uptr, tmr_poll); /* reactivate unit */
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tmxr_poll = tmr_poll * tim_mult; /* set mux poll */
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tim_incr_base (tim_base, tim_period); /* incr time base */
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tim_ttg = tim_period; /* reload */
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apr_flg = apr_flg | APRF_TIM; /* request interrupt */
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if (Q_ITS) { /* ITS? */
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if (pi_act == 0)
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quant = (quant + TIM_ITS_QUANT) & DMASK;
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if (TSTS (pcst)) { /* PC sampling? */
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WriteP ((a10) pcst & AMASK, pager_PC); /* store sample */
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pcst = AOB (pcst); /* add 1,,1 */
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}
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} /* end ITS */
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else if (t20_idlelock && PROB (100 - tim_t20_prob))
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t20_idlelock = 0;
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return SCPE_OK;
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}
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void tim_incr_base (d10 *base, d10 incr)
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{
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base[1] = base[1] + incr; /* add on incr */
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base[0] = base[0] + (base[1] >> 35); /* carry to high */
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base[0] = base[0] & DMASK; /* mask high */
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base[1] = base[1] & MMASK; /* mask low */
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return;
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}
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/* Timer reset */
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t_stat tim_reset (DEVICE *dptr)
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{
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sim_register_clock_unit (&tim_unit); /* declare clock unit */
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tim_period = 0; /* clear timer */
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tim_ttg = 0;
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apr_flg = apr_flg & ~APRF_TIM; /* clear interrupt */
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tmr_poll = sim_rtc_init (tim_unit.wait); /* init timer */
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sim_activate (&tim_unit, tmr_poll); /* activate unit */
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tmxr_poll = tmr_poll * tim_mult; /* set mux poll */
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return SCPE_OK;
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}
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/* Set timer parameters from CPU model */
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t_stat tim_set_mod (UNIT *uptr, int32 val, char *cptr, void *desc)
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{
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if (val & (UNIT_T20|UNIT_KLAD)) {
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clk_tps = TIM_TPS_T20;
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uptr->wait = TIM_WAIT_T20;
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tmr_poll = TIM_WAIT_T20;
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tim_mult = TIM_MULT_T20;
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uptr->flags = uptr->flags | UNIT_Y2K;
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}
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else {
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clk_tps = TIM_TPS_T10;
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uptr->wait = TIM_WAIT_T10;
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tmr_poll = TIM_WAIT_T10;
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tim_mult = TIM_MULT_T10;
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if (Q_ITS)
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uptr->flags = uptr->flags | UNIT_Y2K;
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else uptr->flags = uptr->flags & ~UNIT_Y2K;
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}
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tmxr_poll = tmr_poll * tim_mult;
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return SCPE_OK;
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}
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/* Time of year clock */
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t_stat tcu_rd (int32 *data, int32 PA, int32 access)
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{
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time_t curtim;
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struct tm *tptr;
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curtim = time (NULL); /* get time */
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tptr = localtime (&curtim); /* decompose */
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if (tptr == NULL)
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return SCPE_NXM;
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if ((tptr->tm_year > 99) && !(tim_unit.flags & UNIT_Y2K))
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tptr->tm_year = 99; /* Y2K prob? */
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switch ((PA >> 1) & 03) { /* decode PA<3:1> */
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case 0: /* year/month/day */
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*data = (((tptr->tm_year) & 0177) << 9) |
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(((tptr->tm_mon + 1) & 017) << 5) |
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((tptr->tm_mday) & 037);
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return SCPE_OK;
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case 1: /* hour/minute */
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*data = (((tptr->tm_hour) & 037) << 8) |
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((tptr->tm_min) & 077);
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return SCPE_OK;
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case 2: /* second */
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*data = (tptr->tm_sec) & 077;
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return SCPE_OK;
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case 3: /* status */
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*data = CSR_DONE;
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return SCPE_OK;
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}
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return SCPE_NXM; /* can't get here */
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}
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