620 lines
24 KiB
C
620 lines
24 KiB
C
/* sigma_coc.c: Sigma character-oriented communications subsystem simulator
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Copyright (c) 2007-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substanXIAl portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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coc 7611 communications multiplexor
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*/
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#include "sigma_io_defs.h"
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#include "sim_sock.h"
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#include "sim_tmxr.h"
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#include <ctype.h>
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/* Constants */
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#define MUX_LINES 64 /* max lines */
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#define MUX_LINES_DFLT 8 /* default lines */
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#define MUX_INIT_POLL 8000
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#define MUXL_WAIT 500
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#define MUX_NUMLIN mux_desc.lines /* curr # lines */
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#define MUXC 0 /* channel thread */
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#define MUXI 1 /* input thread */
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/* Line status */
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#define MUXL_XIA 0x01 /* xmt intr armed */
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#define MUXL_XIR 0x02 /* xmt intr req */
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#define MUXL_REP 0x04 /* rcv enable pend */
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#define MUXL_RBP 0x10 /* rcv break pend */
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/* Channel state */
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#define MUXC_IDLE 0 /* idle */
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#define MUXC_INIT 1 /* init */
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#define MUXC_RCV 2 /* receive */
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#define MUXC_END 3 /* end */
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/* DIO address */
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#define MUXDIO_V_FNC 0 /* function */
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#define MUXDIO_M_FNC 0xF
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#define MUXDIO_V_COC 4 /* ctlr num */
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#define MUXDIO_M_COC 0xF
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#define MUXDIO_GETFNC(x) (((x) >> MUXDIO_V_FNC) & MUXDIO_M_FNC)
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#define MUXDIO_GETCOC(x) (((x) >> MUXDIO_V_COC) & MUXDIO_M_COC)
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#define MUXDAT_V_LIN 0 /* line num */
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#define MUXDAT_M_LIN (MUX_LINES - 1)
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#define MUXDAT_V_CHR 8 /* output char */
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#define MUXDAT_M_CHR 0xFF
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#define MUXDAT_GETLIN(x) (((x) >> MUXDAT_V_LIN) & MUXDAT_M_LIN)
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#define MUXDAT_GETCHR(x) (((x) >> MUXDAT_V_CHR) & MUXDAT_M_CHR)
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uint8 mux_rbuf[MUX_LINES]; /* rcv buf */
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uint8 mux_xbuf[MUX_LINES]; /* xmt buf */
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uint8 mux_sta[MUX_LINES]; /* status */
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uint32 mux_tps = RTC_HZ_50; /* polls/second */
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uint32 mux_scan = 0; /* scanner */
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uint32 mux_slck = 0; /* scanner locked */
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uint32 muxc_cmd = MUXC_IDLE; /* channel state */
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uint32 mux_rint = INTV (INTG_E2, 0);
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uint32 mux_xint = INTV (INTG_E2, 1);
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TMLN mux_ldsc[MUX_LINES] = { 0 }; /* line descrs */
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TMXR mux_desc = { MUX_LINES_DFLT, 0, 0, mux_ldsc }; /* mux descrr */
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extern uint32 chan_ctl_time;
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extern uint32 CC;
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extern uint32 *R;
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uint32 mux_disp (uint32 op, uint32 dva, uint32 *dvst);
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uint32 mux_dio (uint32 op, uint32 rn, uint32 ad);
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uint32 mux_tio_status (void);
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t_stat mux_chan_err (uint32 st);
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t_stat muxc_svc (UNIT *uptr);
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t_stat muxo_svc (UNIT *uptr);
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t_stat muxi_rtc_svc (UNIT *uptr);
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t_stat mux_reset (DEVICE *dptr);
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t_stat mux_attach (UNIT *uptr, char *cptr);
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t_stat mux_detach (UNIT *uptr);
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t_stat mux_vlines (UNIT *uptr, int32 val, char *cptr, void *desc);
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void mux_reset_ln (int32 ln);
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void mux_scan_next (t_bool clr);
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t_stat muxi_put_char (uint32 c, uint32 ln);
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/* MUX data structures
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mux_dev MUX device descriptor
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mux_unit MUX unit descriptor
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mux_reg MUX register list
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mux_mod MUX modifiers list
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*/
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dib_t mux_dib = { DVA_MUX, &mux_disp, DIO_MUX, &mux_dio };
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UNIT mux_unit[] = {
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{ UDATA (&muxc_svc, UNIT_ATTABLE, 0) },
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{ UDATA (&muxi_rtc_svc, UNIT_DIS, 0) }
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};
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REG mux_reg[] = {
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{ BRDATA (STA, mux_sta, 16, 8, MUX_LINES) },
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{ BRDATA (RBUF, mux_rbuf, 16, 8, MUX_LINES) },
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{ BRDATA (XBUF, mux_xbuf, 16, 8, MUX_LINES) },
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{ DRDATA (SCAN, mux_scan, 6) },
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{ FLDATA (SLCK, mux_slck, 0) },
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{ DRDATA (CMD, muxc_cmd, 2) },
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{ DRDATA (TPS, mux_tps, 8), REG_HRO },
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{ NULL }
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};
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MTAB mux_mod[] = {
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{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
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&tmxr_dscln, NULL, &mux_desc },
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{ UNIT_ATT, UNIT_ATT, "summary", NULL,
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NULL, &tmxr_show_summ, (void *) &mux_desc },
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{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
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NULL, &tmxr_show_cstat, (void *) &mux_desc },
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{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL,
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NULL, &tmxr_show_cstat, (void *) &mux_desc },
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{ MTAB_XTD|MTAB_VDV, 0, "CHAN", "CHAN",
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&io_set_dvc, &io_show_dvc, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "DVA", "DVA",
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&io_set_dva, &io_show_dva, NULL },
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{ MTAB_XTD | MTAB_VDV, 0, "LINES", "LINES",
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&mux_vlines, &tmxr_show_lines, (void *) &mux_desc },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "CSTATE", NULL,
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NULL, &io_show_cst, NULL },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, RTC_COC, "POLL", "POLL",
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&rtc_set_tps, &rtc_show_tps, (void *) &mux_tps },
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{ 0 }
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};
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DEVICE mux_dev = {
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"MUX", mux_unit, mux_reg, mux_mod,
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2, 10, 31, 1, 16, 8,
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&tmxr_ex, &tmxr_dep, &mux_reset,
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NULL, &mux_attach, &mux_detach,
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&mux_dib, DEV_NET | DEV_DISABLE
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};
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/* MUXL data structures
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muxl_dev MUXL device descriptor
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muxl_unit MUXL unit descriptor
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muxl_reg MUXL register list
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muxl_mod MUXL modifiers list
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*/
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UNIT muxl_unit[] = {
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{ UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, TT_MODE_UC|UNIT_DIS, 0), MUXL_WAIT }
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};
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MTAB muxl_mod[] = {
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{ TT_MODE, TT_MODE_UC, "UC", "UC", NULL },
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{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
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{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
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{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL },
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{ MTAB_XTD|MTAB_VUN, 0, NULL, "DISCONNECT",
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&tmxr_dscln, NULL, &mux_desc },
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{ MTAB_XTD|MTAB_VUN|MTAB_NC, 0, "LOG", "LOG",
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&tmxr_set_log, &tmxr_show_log, &mux_desc },
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{ MTAB_XTD|MTAB_VUN|MTAB_NC, 0, NULL, "NOLOG",
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&tmxr_set_nolog, NULL, &mux_desc },
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{ 0 }
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};
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REG muxl_reg[] = {
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{ URDATA (TIME, muxl_unit[0].wait, 10, 24, 0,
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MUX_LINES, REG_NZ + PV_LEFT) },
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{ NULL }
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};
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DEVICE muxl_dev = {
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"MUXL", muxl_unit, muxl_reg, muxl_mod,
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MUX_LINES, 10, 31, 1, 8, 8,
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NULL, NULL, &mux_reset,
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NULL, NULL, NULL,
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NULL, 0
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};
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/* MUX: IO dispatch routine */
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uint32 mux_disp (uint32 op, uint32 dva, uint32 *dvst)
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{
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switch (op) { /* case on op */
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case OP_SIO: /* start I/O */
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*dvst = mux_tio_status (); /* get status */
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if ((*dvst & DVS_CST) == 0) { /* ctrl idle? */
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muxc_cmd = MUXC_INIT; /* start dev thread */
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sim_activate (&mux_unit[MUXC], chan_ctl_time);
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}
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break;
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case OP_TIO: /* test status */
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*dvst = mux_tio_status (); /* return status */
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break;
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case OP_TDV: /* test status */
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*dvst = 0; /* no status */
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break;
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case OP_HIO: /* halt I/O */
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*dvst = mux_tio_status (); /* get status */
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muxc_cmd = MUXC_IDLE; /* stop dev thread */
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sim_cancel (&mux_unit[MUXC]);
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io_sclr_req (mux_rint, 0); /* clr rcv int */
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io_sclr_req (mux_xint, 0);
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break;
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case OP_AIO: /* acknowledge int */
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*dvst = 0; /* no status */
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break;
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default:
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*dvst = 0;
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return SCPE_IERR;
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}
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return 0;
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}
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/* MUX: DIO dispatch routine */
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uint32 mux_dio (uint32 op, uint32 rn, uint32 ad)
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{
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int32 ln;
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uint32 fnc = MUXDIO_GETFNC (ad);
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uint32 coc = MUXDIO_GETCOC (ad);
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if (op == OP_RD) { /* read direct */
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if (coc != 0) /* nx COC? */
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return 0;
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R[rn] = mux_scan | 0x40; /* return line num */
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mux_sta[mux_scan] &= ~MUXL_XIR; /* clear int req */
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return 0;
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}
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ln = MUXDAT_GETLIN (R[rn]); /* get line num */
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if (fnc & 0x4) { /* transmit */
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if ((coc != 0) || /* nx COC or */
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(ln >= MUX_NUMLIN)) { /* nx line? */
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CC |= CC4;
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return 0;
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}
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if ((fnc & 0x7) == 0x5) { /* send char? */
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if (fnc & 0x8) /* space? */
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mux_xbuf[ln] = 0;
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else mux_xbuf[ln] = MUXDAT_GETCHR (R[rn]); /* no, get char */
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sim_activate (&muxl_unit[ln], muxl_unit[ln].wait);
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mux_sta[ln] = (mux_sta[ln] | MUXL_XIA) & ~MUXL_XIR;
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mux_scan_next (1); /* unlock scanner */
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}
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else if (fnc == 0x06) { /* stop transmit */
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mux_sta[ln] &= ~MUXL_XIA|MUXL_XIR; /* disable int */
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mux_scan_next (1); /* unlock scanner */
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}
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else if (fnc == 0x07) { /* disconnect */
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tmxr_reset_ln (&mux_ldsc[ln]); /* reset line */
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mux_reset_ln (ln); /* reset state */
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}
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CC = (sim_is_active (&muxl_unit[ln])? 0: CC4) |
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(mux_ldsc[ln].conn? CC3: 0);
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}
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else { /* receive */
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if ((coc != 0) || /* nx COC or */
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(ln >= MUX_NUMLIN)) /* nx line */
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return 0;
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if (fnc == 0x01) { /* set rcv enable */
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if (mux_ldsc[ln].conn) /* connected? */
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mux_ldsc[ln].rcve = 1; /* just enable */
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else mux_sta[ln] |= MUXL_REP; /* enable pending */
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}
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else if (fnc == 0x02) { /* clr rcv enable */
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mux_ldsc[ln].rcve = 0;
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mux_sta[ln] &= ~MUXL_REP;
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}
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else if (fnc == 0x03) { /* disconnect */
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tmxr_reset_ln (&mux_ldsc[ln]); /* reset line */
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mux_reset_ln (ln); /* reset state */
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}
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if (mux_sta[ln] & MUXL_RBP) /* break pending? */
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CC = CC3|CC4;
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else CC = mux_ldsc[ln].rcve? CC4: CC3;
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}
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return 0;
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}
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/* Unit service - channel overhead */
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t_stat muxc_svc (UNIT *uptr)
|
|
{
|
|
uint32 st;
|
|
uint32 cmd;
|
|
|
|
if (muxc_cmd == MUXC_INIT) { /* init state? */
|
|
st = chan_get_cmd (mux_dib.dva, &cmd); /* get command */
|
|
if (CHS_IFERR (st)) /* channel error? */
|
|
mux_chan_err (st); /* go idle */
|
|
else muxc_cmd = MUXC_RCV; /* no, receive */
|
|
}
|
|
else if (muxc_cmd == MUXC_END) { /* end state? */
|
|
st = chan_end (mux_dib.dva); /* set channel end */
|
|
if (CHS_IFERR (st)) /* channel error? */
|
|
mux_chan_err (st); /* go idle */
|
|
else if (st == CHS_CCH) { /* command chain? */
|
|
muxc_cmd = MUXC_INIT; /* restart thread */
|
|
sim_activate (uptr, chan_ctl_time); /* schedule soon */
|
|
}
|
|
else muxc_cmd = MUXC_IDLE; /* else idle */
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Unit service - polled input - called from rtc scheduler
|
|
|
|
Poll for new connections
|
|
Poll all connected lines for input
|
|
*/
|
|
|
|
t_stat muxi_rtc_svc (UNIT *uptr)
|
|
{
|
|
t_stat r;
|
|
int32 newln, ln, c;
|
|
|
|
if ((mux_unit[MUXC].flags & UNIT_ATT) == 0) /* attached? */
|
|
return SCPE_OK;
|
|
newln = tmxr_poll_conn (&mux_desc); /* look for connect */
|
|
if ((newln >= 0) && (mux_sta[newln] & MUXL_REP)) { /* rcv enb pending? */
|
|
mux_ldsc[newln].rcve = 1; /* enable rcv */
|
|
mux_sta[newln] &= ~MUXL_REP; /* clr pending */
|
|
}
|
|
tmxr_poll_rx (&mux_desc); /* poll for input */
|
|
for (ln = 0; ln < MUX_NUMLIN; ln++) { /* loop thru lines */
|
|
if (mux_ldsc[ln].conn) { /* connected? */
|
|
if (c = tmxr_getc_ln (&mux_ldsc[ln])) { /* get char */
|
|
if (c & SCPE_BREAK) /* break? */
|
|
mux_sta[ln] |= MUXL_RBP; /* set rcv brk */
|
|
else { /* normal char */
|
|
mux_sta[ln] &= ~MUXL_RBP; /* clr rcv brk */
|
|
c = sim_tt_inpcvt (c, TT_GET_MODE (muxl_unit[ln].flags));
|
|
mux_rbuf[ln] = c; /* save char */
|
|
if ((muxc_cmd == MUXC_RCV) && /* chan active? */
|
|
(r = muxi_put_char (c, ln))) /* char to chan */
|
|
return r;
|
|
} /* end else char */
|
|
} /* end if char */
|
|
} /* end if conn */
|
|
else mux_sta[ln] &= ~MUXL_RBP; /* disconnected */
|
|
} /* end for */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Put character and line number in memory via channel */
|
|
|
|
t_stat muxi_put_char (uint32 c, uint32 ln)
|
|
{
|
|
uint32 st;
|
|
|
|
st = chan_WrMemB (mux_dib.dva, c); /* write char */
|
|
if (CHS_IFERR (st)) /* channel error? */
|
|
return mux_chan_err (st);
|
|
st = chan_WrMemB (mux_dib.dva, ln); /* write line */
|
|
if (CHS_IFERR (st)) /* channel error? */
|
|
return mux_chan_err (st);
|
|
if (st == CHS_ZBC) { /* bc == 0? */
|
|
muxc_cmd = MUXC_END; /* end state */
|
|
sim_activate (&mux_unit[MUXC], chan_ctl_time); /* quick schedule */
|
|
}
|
|
io_sclr_req (mux_rint, 1); /* req ext intr */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Channel error */
|
|
|
|
t_stat mux_chan_err (uint32 st)
|
|
{
|
|
chan_uen (mux_dib.dva); /* uend */
|
|
muxc_cmd = MUXC_IDLE; /* go idle */
|
|
if (st < CHS_ERR)
|
|
return st;
|
|
return 0;
|
|
}
|
|
|
|
/* Unit service - transmit side */
|
|
|
|
t_stat muxo_svc (UNIT *uptr)
|
|
{
|
|
int32 c;
|
|
uint32 ln = uptr - muxl_unit; /* line # */
|
|
|
|
if (mux_ldsc[ln].conn) { /* connected? */
|
|
if (mux_ldsc[ln].xmte) { /* xmt enabled? */
|
|
c = sim_tt_outcvt (mux_xbuf[ln], TT_GET_MODE (muxl_unit[ln].flags));
|
|
if (c >= 0)
|
|
tmxr_putc_ln (&mux_ldsc[ln], c); /* output char */
|
|
tmxr_poll_tx (&mux_desc); /* poll xmt */
|
|
if (mux_sta[ln] & MUXL_XIA) { /* armed? */
|
|
mux_sta[ln] |= MUXL_XIR; /* req intr */
|
|
mux_scan_next (0); /* kick scanner */
|
|
}
|
|
}
|
|
else { /* buf full */
|
|
tmxr_poll_tx (&mux_desc); /* poll xmt */
|
|
sim_activate (uptr, muxl_unit[ln].wait); /* wait */
|
|
return SCPE_OK;
|
|
}
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* MUX status routine */
|
|
|
|
uint32 mux_tio_status (void)
|
|
{
|
|
if (muxc_cmd == MUXC_IDLE) /* idle? */
|
|
return DVS_AUTO;
|
|
else return (DVS_AUTO|DVS_CBUSY|DVS_DBUSY|(CC2 << DVT_V_CC));
|
|
}
|
|
|
|
/* Kick scanner */
|
|
|
|
void mux_scan_next (t_bool clr)
|
|
{
|
|
int32 i;
|
|
|
|
if (clr) /* unlock? */
|
|
mux_slck = 0;
|
|
else if (mux_slck) /* locked? */
|
|
return;
|
|
for (i = 0; i < MUX_NUMLIN; i++) { /* scan lines */
|
|
mux_scan = mux_scan + 1; /* next line */
|
|
if (mux_scan >= (uint32) MUX_NUMLIN)
|
|
mux_scan = 0;
|
|
if (mux_sta[mux_scan] & MUXL_XIR) { /* flag set? */
|
|
mux_slck = 1; /* lock scanner */
|
|
io_sclr_req (mux_xint, 1); /* req ext int */
|
|
return;
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
|
|
/* Reset routine */
|
|
|
|
t_stat mux_reset (DEVICE *dptr)
|
|
{
|
|
int32 i;
|
|
|
|
if (mux_dev.flags & DEV_DIS) /* master disabled? */
|
|
muxl_dev.flags = muxl_dev.flags | DEV_DIS; /* disable lines */
|
|
else muxl_dev.flags = muxl_dev.flags & ~DEV_DIS;
|
|
if (mux_unit[MUXC].flags & UNIT_ATT) /* master att? */
|
|
rtc_register (RTC_COC, mux_tps, &mux_unit[MUXI]); /* register timer */
|
|
else rtc_register (RTC_COC, RTC_HZ_OFF, NULL); /* else dereg */
|
|
for (i = 0; i < MUX_LINES; i++) /* reset lines */
|
|
mux_reset_ln (i);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Attach master unit */
|
|
|
|
t_stat mux_attach (UNIT *uptr, char *cptr)
|
|
{
|
|
t_stat r;
|
|
|
|
r = tmxr_attach (&mux_desc, uptr, cptr); /* attach */
|
|
if (r != SCPE_OK) /* error */
|
|
return r;
|
|
rtc_register (RTC_COC, mux_tps, &mux_unit[MUXC]); /* register timer */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Detach master unit */
|
|
|
|
t_stat mux_detach (UNIT *uptr)
|
|
{
|
|
int32 i;
|
|
t_stat r;
|
|
|
|
r = tmxr_detach (&mux_desc, uptr); /* detach */
|
|
for (i = 0; i < MUX_LINES; i++) /* disable rcv */
|
|
mux_reset_ln (i);
|
|
rtc_register (RTC_COC, RTC_HZ_OFF, NULL); /* dereg */
|
|
return r;
|
|
}
|
|
|
|
|
|
/* Change number of lines */
|
|
|
|
t_stat mux_vlines (UNIT *uptr, int32 val, char *cptr, void *desc)
|
|
{
|
|
int32 newln, i, t;
|
|
t_stat r;
|
|
|
|
if (cptr == NULL)
|
|
return SCPE_ARG;
|
|
newln = get_uint (cptr, 10, MUX_LINES, &r);
|
|
if ((r != SCPE_OK) || (newln == MUX_NUMLIN))
|
|
return r;
|
|
if (newln == 0) return SCPE_ARG;
|
|
if (newln < MUX_NUMLIN) {
|
|
for (i = newln, t = 0; i < MUX_NUMLIN; i++) t = t | mux_ldsc[i].conn;
|
|
if (t && !get_yn ("This will disconnect users; proceed [N]?", FALSE))
|
|
return SCPE_OK;
|
|
for (i = newln; i < MUX_NUMLIN; i++) {
|
|
if (mux_ldsc[i].conn) {
|
|
tmxr_linemsg (&mux_ldsc[i], "\r\nOperator disconnected line\r\n");
|
|
tmxr_reset_ln (&mux_ldsc[i]); /* reset line */
|
|
}
|
|
muxl_unit[i].flags = muxl_unit[i].flags | UNIT_DIS;
|
|
mux_reset_ln (i);
|
|
}
|
|
}
|
|
else {
|
|
for (i = MUX_NUMLIN; i < newln; i++) {
|
|
muxl_unit[i].flags = muxl_unit[i].flags & ~UNIT_DIS;
|
|
mux_reset_ln (i);
|
|
}
|
|
}
|
|
MUX_NUMLIN = newln;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Reset an individual line */
|
|
|
|
void mux_reset_ln (int32 ln)
|
|
{
|
|
sim_cancel (&muxl_unit[ln]);
|
|
mux_sta[ln] = 0;
|
|
mux_rbuf[ln] = 0;
|
|
mux_xbuf[ln] = 0;
|
|
mux_ldsc[ln].rcve = 0;
|
|
return;
|
|
}
|