482 lines
No EOL
25 KiB
C
482 lines
No EOL
25 KiB
C
/* sigma_defs.h: XDS Sigma simulator definitions
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Copyright (c) 2007-2010, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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The author gratefullly acknowledges the help of George Plue, who provided
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answers to many puzzling questions about how the Sigma series worked.
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22-May-10 RMS Added check for 64b definitions
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*/
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#ifndef SIGMA_DEFS_H_
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#define SIGMA_DEFS_H_ 0
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#include "sim_defs.h" /* simulator defns */
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/* Rename of global PC variable to avoid namespace conflicts on some platforms */
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#define PC PC_Global
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#if defined(USE_INT64) || defined(USE_ADDR64)
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#error "Sigma 32b does not support 64b values!"
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#endif
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/* Simulator stops */
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#define STOP_INVIOC 1 /* invalid IO config */
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#define STOP_IBKPT 2 /* breakpoint */
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#define STOP_ASTOP 3 /* address stop */
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#define STOP_WAITNOINT 4 /* WAIT, no intr */
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#define STOP_INVPSD 5 /* invalid PSD */
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#define STOP_ROLLBACK 6 /* >= here, rollback PC */
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#define STOP_EXULIM 6 /* EXU loop */
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#define STOP_ILLEG 7 /* illegal instr */
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#define STOP_ILLTRP 8 /* illegal trap inst */
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#define STOP_ILLVEC 9 /* illegal vector */
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#define STOP_TRPT 10 /* trap inside int/trap */
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#define STOP_MAX 15 /* <= here for all stops */
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/* Timers */
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#define TMR_RTC 0 /* clocks */
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/* Architectural constants */
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#define PASIZE17 17 /* phys addr width, S5-8 */
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#define PASIZE20 20 /* phys addr width, 5X0 */
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#define PASIZE22 22 /* phys addr width, S9 */
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#define PAMASK17 ((1u << PASIZE17) - 1)
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#define BPAMASK17 ((1u << (PASIZE17 + 2)) - 1)
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#define PAMASK20 ((1u << PASIZE20) - 1)
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#define BPAMASK20 ((1u << (PASIZE20 + 2)) - 1)
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#define PAMASK22 ((1u << PASIZE22) - 1)
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#define BPAMASK22 ((1u << (PASIZE22 + 2)) - 1)
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#define MAXMEMSIZE (1u << PASIZE20) /* maximum memory */
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#define MEMSIZE (cpu_unit.capac)
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#define MEM_IS_NXM(x) ((x) >= MEMSIZE)
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#define BPA_IS_NXM(x) (((x) >> 2) >= MEMSIZE)
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#define VASIZE 17 /* virtual addr width */
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#define VAMASK ((1u << VASIZE) - 1) /* virtual addr mask */
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#define BVAMASK ((1u << (VASIZE + 2)) - 1) /* byte virtual addr mask */
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#define RF_NUM 16 /* number of registers */
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#define RF_NBLK 32 /* max number reg blocks */
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#define RF_DFLT 4 /* default reg blocks */
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/* CPU models, options, and variable data */
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#define CPUF_STR (1u << (UNIT_V_UF + 0)) /* byte string */
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#define CPUF_DEC (1u << (UNIT_V_UF + 1)) /* decimal */
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#define CPUF_FP (1u << (UNIT_V_UF + 2)) /* floating point */
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#define CPUF_MAP (1u << (UNIT_V_UF + 3)) /* memory map */
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#define CPUF_WLK (1u << (UNIT_V_UF + 4)) /* write lock protect */
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#define CPUF_LAMS (1u << (UNIT_V_UF + 5)) /* LAS/LMS */
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#define CPUF_ALLOPT (CPUF_STR|CPUF_DEC|CPUF_FP|CPUF_MAP|CPUF_WLK|CPUF_LAMS)
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#define CPUF_MSIZE (1u << (UNIT_V_UF + 6)) /* dummy for memory */
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#define CPU_V_S5 0
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#define CPU_V_S6 1
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#define CPU_V_S7 2
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#define CPU_V_S8 3 /* not supported */
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#define CPU_V_S9 4 /* not supported */
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#define CPU_V_550 5 /* not supported */
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#define CPU_V_560 6 /* not supported */
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#define CPU_S5 (1u << CPU_V_S5)
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#define CPU_S6 (1u << CPU_V_S6)
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#define CPU_S7 (1u << CPU_V_S7)
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#define CPU_S7B (1u << CPU_V_S7B)
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#define CPU_S8 (1u << CPU_V_S8)
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#define CPU_S9 (1u << CPU_V_S9)
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#define CPU_550 (1u << CPU_V_550)
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#define CPU_560 (1u << CPU_V_560)
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#define QCPU_S5 (cpu_model == CPU_V_S5)
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#define QCPU_S9 (cpu_model == CPU_V_S9)
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#define QCPU_5X0 ((1u << cpu_model) & (CPU_550|CPU_560))
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#define QCPU_S567 ((1u << cpu_model) & (CPU_S5|CPU_S6|CPU_S7))
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#define QCPU_S89 ((1u << cpu_model) & (CPU_S8|CPU_S9))
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#define QCPU_S89_5X0 ((1u << cpu_model) & (CPU_S8|CPU_S9|CPU_550|CPU_560))
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#define QCPU_BIGM ((1u << cpu_model) & (CPU_S9|CPU_550|CPU_560))
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#define CPU_MUNIT_SIZE (1u << 15) /* mem unit size */
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typedef struct {
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uint32 psw1_mbz; /* PSW1 mbz */
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uint32 psw2_mbz; /* PSW2 mbz */
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uint32 mmc_cm_map1; /* MMC mode 1 cmask */
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uint32 pamask; /* physical addr mask */
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uint32 eigrp_max; /* max num ext int groups */
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uint32 chan_max; /* max num channels */
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uint32 iocc; /* IO instr CC bits */
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uint32 std; /* required options */
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uint32 opt; /* variable options */
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} cpu_var_t;
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/* Instruction format */
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#define INST_V_IND 31 /* indirect */
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#define INST_IND (1u << INST_V_IND)
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#define INST_V_OP 24 /* opcode */
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#define INST_M_OP 0x7F
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#define INST_V_RN 20 /* register */
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#define INST_M_RN 0xF
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#define INST_V_XR 17 /* index */
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#define INST_M_XR 0x7
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#define INST_V_ADDR 0 /* 17b addr */
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#define INST_M_ADDR 0x1FFFF
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#define INST_V_LIT 0 /* 20b literal or addr */
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#define INST_M_LIT 0xFFFFF
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#define TST_IND(x) ((x) & INST_IND)
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#define I_GETOP(x) (((x) >> INST_V_OP) & INST_M_OP)
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#define I_GETRN(x) (((x) >> INST_V_RN) & INST_M_RN)
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#define I_GETXR(x) (((x) >> INST_V_XR) & INST_M_XR)
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#define I_GETADDR(x) (((x) >> INST_V_ADDR) & INST_M_ADDR)
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#define I_GETADDR20(x) (((x) >> INST_V_ADDR) & PAMASK20)
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#define I_GETLIT(x) (((x) >> INST_V_LIT) & INST_M_LIT)
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#define IRB(x) (1u << (31 - (x)))
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/* Shift instructions */
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#define SHF_V_SOP 8 /* shift operation */
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#define SHF_M_SOP 0x7
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#define SHF_V_SC 0 /* shift count */
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#define SHF_M_SC 0x7F
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#define SCSIGN 0x40
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#define SHF_GETSOP(x) (((x) >> SHF_V_SOP) & SHF_M_SOP)
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#define SHF_GETSC(x) (((x) >> SHF_V_SC) & SHF_M_SC)
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/* String instructions */
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#define S_V_MCNT 24 /* string mask/count */
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#define S_M_MCNT 0xFF
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#define S_MCNT (S_M_MCNT << S_V_MCNT)
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#define S_GETMCNT(x) (((x) >> S_V_MCNT) & S_M_MCNT)
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#define S_ADDRINC (S_MCNT + 1)
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/* Data types */
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#define WMASK 0xFFFFFFFF /* word */
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#define WSIGN 0x80000000 /* word sign */
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#define LITMASK (INST_M_LIT) /* literal */
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#define LITSIGN 0x80000 /* literal sign */
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#define HMASK 0xFFFF /* halfword mask */
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#define HSIGN 0x8000 /* halfword sign */
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#define BMASK 0xFF /* byte */
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#define BSIGN 0x80 /* byte sign */
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#define RNMASK (INST_M_RN) /* reg lit */
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#define RNSIGN 0x08 /* reg lit sign */
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#define FP_V_SIGN 31 /* sign */
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#define FP_SIGN (1u << FP_V_SIGN)
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#define FP_V_EXP 24 /* exponent */
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#define FP_M_EXP 0x7F
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#define FP_BIAS 0x40 /* exponent bias */
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#define FP_V_FRHI 0 /* high fraction */
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#define FP_M_FRHI 0x00FFFFFF
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#define FP_NORM 0x00F00000
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#define FP_M_FRLO 0xFFFFFFFF /* low fraction */
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#define FP_GETSIGN(x) (((x) >> FP_V_SIGN) & 1)
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#define FP_GETEXP(x) (((x) >> FP_V_EXP) & FP_M_EXP)
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#define FP_GETFRHI(x) (((x) >> FP_V_FRHI) & FP_M_FRHI)
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#define FP_GETFRLO(x) ((x) & FP_M_FRLO)
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/* PSW1 fields */
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#define PSW1_V_CC 28 /* cond codes */
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#define PSW1_M_CC 0xF
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#define CC1 0x8
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#define CC2 0x4
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#define CC3 0x2
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#define CC4 0x1
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#define PSW1_V_FR 27 /* fp mode controls */
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#define PSW1_V_FS 26
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#define PSW1_V_FZ 25
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#define PSW1_V_FN 24
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#define PSW1_V_FPC 24 /* as a group */
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#define PSW1_M_FPC 0xF
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#define PSW1_FPC (PSW1_M_FPC << PSW1_V_FPC)
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#define PSW1_V_MS 23 /* master/slave */
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#define PSW1_V_MM 22 /* memory map */
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#define PSW1_V_DM 21 /* decimal trap */
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#define PSW1_V_AM 20 /* arithmetic trap */
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#define PSW1_V_AS 19 /* EBCDIC/ASCII, S9 */
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#define PSW1_V_XA 15 /* ext addr flag, S9 */
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#define PSW1_V_PC 0 /* PC */
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#define PSW1_M_PC (VAMASK)
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#define PSW1_FR (1u << PSW1_V_FR)
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#define PSW1_FS (1u << PSW1_V_FS)
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#define PSW1_FZ (1u << PSW1_V_FZ)
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#define PSW1_FN (1u << PSW1_V_FN)
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#define PSW1_MS (1u << PSW1_V_MS)
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#define PSW1_MM (1u << PSW1_V_MM)
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#define PSW1_DM (1u << PSW1_V_DM)
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#define PSW1_AM (1u << PSW1_V_AM)
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#define PSW1_AS (1u << PSW1_V_AS)
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#define PSW1_XA (1u << PSW1_V_XA)
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#define PSW1_CCMASK (PSW1_M_CC << PSW1_V_CC)
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#define PSW1_PCMASK (PSW1_M_PC << PSW1_V_PC)
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#define PSW1_GETCC(x) (((x) >> PSW1_V_CC) & PSW1_M_CC)
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#define PSW1_GETPC(x) (((x) >> PSW1_V_PC) & PSW1_M_PC)
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#define PSW1_DFLT 0
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/* PSW2 fields */
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#define PSW2_V_WLK 28 /* write key */
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#define PSW2_M_WLK 0xF
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#define PSW2_V_CI 26 /* counter int inhibit */
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#define PSW2_V_II 25 /* IO int inhibit */
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#define PSW2_V_EI 24 /* external int inhibit */
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#define PSW2_V_INH (PSW2_V_EI) /* inhibits as a group */
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#define PSW2_M_INH 0x7
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#define PSW2_V_MA9 23 /* mode altered, S9 */
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#define PSW2_V_EA 16 /* ext addr, S9 */
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#define PSW2_M_EA 0x3F
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#define PSW2_EA (PSW2_M_EA << PSW2_V_EA)
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#define PSW2_V_TSF 8 /* trapped status, S9 */
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#define PSW2_M_TSF 0xFF
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#define PSW2_TSF (PSW2_M_TSF << PSW2_V_TSF)
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#define PSW2_V_RP 4 /* register block ptr */
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#define PSW2_M_RP5B 0x1F
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#define PSW2_M_RP4B 0xF
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#define PSW2_RP ((QCPU_S567? PSW2_M_RP5B: PSW2_M_RP4B) << PSW2_V_RP)
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#define PSW2_V_RA 3 /* reg altered, 9,5X0 */
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#define PSW2_V_MA5X0 2 /* mode altered, 5X0 */
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#define PSW2_CI (1u << PSW2_V_CI)
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#define PSW2_II (1u << PSW2_V_II)
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#define PSW2_EI (1u << PSW2_V_EI)
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#define PSW2_ALLINH (PSW2_CI|PSW2_II|PSW2_EI) /* all inhibits */
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#define PSW2_MA9 (1u << PSW2_V_MA9)
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#define PSW2_RA (1u << PSW2_V_RA)
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#define PSW2_MA5X0 (1u << PSW2_V_MA5X0)
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#define PSW2_WLKMASK (PSW2_M_WLK << PSW2_V_WLK)
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#define PSW2_RPMASK (PSW2_M_RP << PSW2_V_RP)
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#define PSW2_GETINH(x) (((x) >> PSW2_V_INH) & PSW2_M_INH);
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#define PSW2_GETWLK(x) (((x) >> PSW2_V_WLK) & PSW2_M_WLK)
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#define PSW2_GETRP(x) (((x) & PSW2_RP) >> PSW2_V_RP)
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#define PSW2_DFLT 0
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/* Stack pointers */
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#define SP_V_TS 31 /* space trap enable */
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#define SP_TS (1u << SP_V_TS)
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#define SP_V_SPC 16 /* space */
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#define SP_M_SPC 0x7FFF
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#define SP_V_TW 15 /* words trap enable */
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#define SP_TW (1u << SP_V_TW)
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#define SP_V_WDS 0 /* words */
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#define SP_M_WDS 0x7FFF
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#define SP_GETSPC(x) (((x) >> SP_V_SPC) & SP_M_SPC)
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#define SP_GETWDS(x) (((x) >> SP_V_WDS) & SP_M_WDS)
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/* System stack pointer (5X0 only) */
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#define SSP_TOS 0 /* system stack */
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#define SSP_SWC 1 /* space/word count */
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#define SSP_DFLT_PSW1 2 /* default PSD */
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#define SSP_DFLT_PSW2 3
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#define SSP_FR_LNT 28 /* frame length */
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#define SSP_FR_RN 0 /* registers */
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#define SSP_FR_PSW1 24 /* PSD */
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#define SSP_FR_PSW2 25
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#define SSP_FR_PSW4 27
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/* The Sigma series had word addressable memory, but byte addressable
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data. Virtual addresses in the simulator are BYTE addresses, and
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these definitions are in terms of a byte address (word << 2). */
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#define VA_NUM_PAG (1 << (VASIZE - (BVA_V_PAG - 2)))
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#define PA_NUM_PAG (1 << (PASIZE22 - (BVA_V_PAG - 2)))
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#define BVA_V_OFF 0 /* offset */
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#define BVA_M_OFF 0x7FF
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#define BVA_V_PAG 11 /* page */
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#define BVA_M_PAG 0xFF
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#define BVA_GETOFF(x) (((x) >> BVA_V_OFF) & BVA_M_OFF)
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#define BVA_GETPAG(x) (((x) >> BVA_V_PAG) & BVA_M_PAG)
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#define BPA_V_PAG (BVA_V_PAG) /* phys page */
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#define BPA_M_PAG 0x1FFF
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#define BPA_GETPAG(x) (((x) >> BPA_V_PAG) & BPA_M_PAG)
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/* Memory maps */
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#define MMC_V_CNT 24 /* count */
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#define MMC_M_CNT 0xFF
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#define MMC_CNT (MMC_M_CNT << MMC_V_CNT)
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#define MMC_V_CS 9 /* start of page */
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/* /* map 1: 2b locks, per model */
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#define MMC_M_CS2 0xFC /* map 2: access controls */
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#define MMC_M_CS3 0x7FE /* map 3: 4b locks */
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#define MMC_M_CS4 0xFF /* map 4: 8b relocation */
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#define MMC_M_CS5 0xFF /* map 5: 13b relocation */
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#define MMC_GETCNT(x) (((x) >> MMC_V_CNT) & MMC_M_CNT)
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#define MMC_L_CS1 (VA_NUM_PAG) /* map lengths */
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#define MMC_L_CS2 (VA_NUM_PAG)
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#define MMC_L_CS3 (PA_NUM_PAG)
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#define MMC_L_CS4 (VA_NUM_PAG)
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#define MMC_L_CS5 (VA_NUM_PAG)
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/* Trap codes */
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#define TR_V_FL 17 /* trap flag */
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#define TR_FL (1u << TR_V_FL)
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#define TR_V_PDF 16 /* proc detected fault */
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#define TR_PDF (1u << TR_V_FL)
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#define TR_V_CC 12 /* or'd to CC/addr offset */
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#define TR_M_CC 0xF
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#define TR_V_VEC 0 /* trap address */
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#define TR_M_VEC 0xFFF
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#define TR_GETVEC(x) (((x) >> TR_V_VEC) & TR_M_VEC)
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#define TR_GETCC(x) (((x) >> TR_V_CC) & TR_M_CC)
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#define TR_NXI (TR_FL|0x8040) /* non-existent inst */
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#define TR_NXM (TR_FL|0x4040) /* non-existent memory */
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#define TR_PRV (TR_FL|0x2040) /* privileged inst */
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#define TR_MPR (TR_FL|0x1040) /* mem protect violation */
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#define TR_WLK (TR_FL|0x3040) /* write lock (5x0 only) */
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#define TR_UNI (TR_FL|0x0041) /* unimplemented inst */
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#define TR_PSH (TR_FL|0x0042) /* pushdown overflow */
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#define TR_FIX (TR_FL|0x0043) /* fixed point arith */
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#define TR_FLT (TR_FL|0x0044) /* floating point arith */
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#define TR_DEC (TR_FL|0x0045) /* decimal arithmetic */
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#define TR_WAT (TR_FL|0x0046) /* watchdog timer */
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#define TR_47 (TR_FL|0x0047) /* 5X0 - WD trap */
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#define TR_C1(x) (TR_FL|0x0048|((x) << TR_V_CC)) /* call instruction */
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#define TR_C2(x) (TR_FL|0x0049|((x) << TR_V_CC)) /* call instruction */
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#define TR_C3(x) (TR_FL|0x004A|((x) << TR_V_CC)) /* call instruction */
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#define TR_C4(x) (TR_FL|0x004B|((x) << TR_V_CC)) /* call instruction */
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#define TR_NESTED (TR_FL|TR_PDF|0xF04D) /* 9,5X0 - fault in inv/trap */
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#define TR_INVTRP (TR_FL|TR_PDF|0xC04D) /* 9,5X0 - inv int/trap inst */
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#define TR_INVRPT (TR_FL|TR_PDF|0x804D) /* 9 - inv new RP in trap */
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#define TR_INVSSP (TR_FL|TR_PDF|0x404D) /* 5X0 - inv SSP for PLS */
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#define TR_INVMMC (TR_FL|TR_PDF|0x204D) /* 9,5X0 - inv MMC config */
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#define TR_INVREG (TR_FL|0x104D) /* 9,5x0 - inv reg num */
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#define TR_INVRPN (TR_FL|TR_PDF|0x004D) /* 9 - inv new RP, non-trap */
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/* Effective address and memory access routines interface
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The access types are defined to make the following equation work:
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trap if ((access_type != 0) && (access_control >= access_type))
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The length codes are defined so that length in bytes = 1 << length_code */
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#define PH 0x0 /* physical */
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#define VW 0x1 /* write */
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#define VI 0x2 /* instruction */
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#define VR 0x3 /* read */
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#define VNT 0x4 /* no traps */
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#define BY 0x0 /* byte */
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#define HW 0x1 /* halfword */
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#define WD 0x2 /* word */
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#define DW 0x3 /* doubleword */
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/* Interrupt groups - the Sigma's have flexibly configured interrupt groups
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of various widths that map non-uniformly to control register bits */
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typedef struct {
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uint32 psw2_inh; /* PSW2 inhibit */
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uint32 nbits; /* number of bits */
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uint32 vecbase; /* vector base */
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uint32 rwgroup; /* RWdirect group */
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uint32 regbit; /* RWdirect reg bit */
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} int_grp_t;
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#define INTG_MAX 17 /* max # int groups */
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#define EIGRP_DFLT 1 /* dflt # ei groups */
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#define INTG_OVR 0 /* override group */
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#define INTG_CTR 1 /* counter group */
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#define INTG_IO 2 /* I/O group */
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#define INTGIO_IO 0x2 /* I/O interrupt */
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#define INTGIO_PANEL 0x1 /* panel interrupt */
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#define INTG_E2 3 /* ext group 2 */
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#define INTG_E3 4 /* ext group 3 */
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#define INT_V_GRP 4 /* interrupt group */
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#define INT_M_GRP 0x1F
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#define INT_V_BIT 0 /* interrupt bit */
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#define INT_M_BIT 0xF
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#define INT_GETGRP(x) (((x) >> INT_V_GRP) & INT_M_GRP)
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#define INT_GETBIT(x) (((x) >> INT_V_BIT) & INT_M_BIT)
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#define INTV(x,y) (((x) << INT_V_GRP) | ((y) << INT_V_BIT))
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#define NO_INT (INTV (INTG_MAX, 0))
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#define VEC_C1P 0x52 /* clock pulse vectors */
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#define VEC_C4P 0x55
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#define VEC_C1Z 0x58 /* clock zero vector */
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/* Integer data operations and condition codes */
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#define SEXT_RN_W(x) (((x) & RNSIGN)? ((x) | ~RNMASK): ((x) & RNMASK))
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#define SEXT_H_W(x) (((x) & HSIGN)? ((x) | ~HMASK): ((x) & HMASK))
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#define SEXT_LIT_W(x) (((x) & LITSIGN)? ((x) | ~LITMASK): ((x) & LITMASK))
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#define NEG_W(x) ((~(x) + 1) & WMASK)
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#define NEG_D(x,y) do { y = NEG_W(y); x = (~(x) + ((y) == 0)) & WMASK; } while (0)
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#define CC34_W(x) CC = (((x) & WSIGN)? \
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((CC & ~CC3) | CC4): \
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|
(((x) != 0)? \
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((CC & ~CC4) | CC3): \
|
|
(CC & ~(CC3|CC4))))
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#define CC234_CMP(x,y) CC = (CC & CC1) | Cmp32 ((x), (y)) | \
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|
(((x) & (y))? CC2: 0)
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/* Instructions */
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|
|
enum opcodes {
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OP_00, OP_01, OP_LCFI, OP_03, OP_CAL1, OP_CAL2, OP_CAL3, OP_CAL4,
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OP_PLW, OP_PSW, OP_PLM, OP_PSM, OP_PLS, OP_PSS, OP_LPSD, OP_XPSD,
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OP_AD, OP_CD, OP_LD, OP_MSP, OP_14, OP_STD, OP_16, OP_17,
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OP_SD, OP_CLM, OP_LCD, OP_LAD, OP_FSL, OP_FAL, OP_FDL, OP_FML,
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OP_AI, OP_CI, OP_LI, OP_MI, OP_SF, OP_S, OP_LAS, OP_27,
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OP_CVS, OP_CVA, OP_LM, OP_STM, OP_LRA, OP_LMS, OP_WAIT, OP_LRP,
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OP_AW, OP_CW, OP_LW, OP_MTW, OP_LVAW, OP_STW, OP_DW, OP_MW,
|
|
OP_SW, OP_CLR, OP_LCW, OP_LAW, OP_FSS, OP_FAS, OP_FDS, OP_FMS,
|
|
OP_TTBS, OP_TBS, OP_42, OP_43, OP_ANLZ, OP_CS, OP_XW, OP_STS,
|
|
OP_EOR, OP_OR, OP_LS, OP_AND, OP_SIO, OP_TIO, OP_TDV, OP_HIO,
|
|
OP_AH, OP_CH, OP_LH, OP_MTH, OP_54, OP_STH, OP_DH, OP_MH,
|
|
OP_SH, OP_59, OP_LCH, OP_LAH, OP_5C, OP_5D, OP_5E, OP_5F,
|
|
OP_CBS, OP_MBS, OP_62, OP_EBS, OP_BDR, OP_BIR, OP_AWM, OP_EXU,
|
|
OP_BCR, OP_BCS, OP_BAL, OP_INT, OP_RD, OP_WD, OP_AIO, OP_MMC,
|
|
OP_LCF, OP_CB, OP_LB, OP_MTB, OP_STCF, OP_STB, OP_PACK, OP_UNPK,
|
|
OP_DS, OP_DA, OP_DD, OP_DM, OP_DSA, OP_DC, OP_DL, OP_DST
|
|
};
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|
|
/* Function prototypes */
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|
|
|
uint32 Ea (uint32 ir, uint32 *bva, uint32 acc, uint32 lnt);
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|
uint32 ReadB (uint32 bva, uint32 *dat, uint32 acc);
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|
uint32 ReadH (uint32 bva, uint32 *dat, uint32 acc);
|
|
uint32 ReadW (uint32 bva, uint32 *dat, uint32 acc);
|
|
uint32 ReadD (uint32 bva, uint32 *dat, uint32 *dat1, uint32 acc);
|
|
uint32 WriteB (uint32 bva, uint32 dat, uint32 acc);
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|
uint32 WriteH (uint32 bva, uint32 dat, uint32 acc);
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|
uint32 WriteW (uint32 bva, uint32 dat, uint32 acc);
|
|
uint32 WriteD (uint32 bva, uint32 dat, uint32 dat1, uint32 acc);
|
|
uint32 ReadMemVW (uint32 bva, uint32 *dat, uint32 acc);
|
|
uint32 WriteMemVW (uint32 bva, uint32 dat, uint32 acc);
|
|
uint32 ReadPB (uint32 ba, uint32 *dat);
|
|
uint32 WritePB (uint32 ba, uint32 dat);
|
|
uint32 ReadPW (uint32 pa, uint32 *dat);
|
|
uint32 WritePW (uint32 pa, uint32 dat);
|
|
uint32 ReadHist (uint32 bva, uint32 *dat, uint32 *dat1, uint32 acc, uint32 lnt);
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#endif |