b5ea9ec38e
These include simulators for the IBM 701, IBM 702, IBM 704, IBM 705, IBM 705/3, IBM 709, IBM 1410/IBM 7010, IBM 7070, IBM 7080, IBM 7090 and IBM7094. These basically were a collection of machines that shared a common set it peripherals, Each group had its own instruction set, hence different simulators. IBM 701 -> i701 IBM 702/705/705/3/7080 -> i7080 IBM 7070/7074 -> i7070 IBM 1410/7010 -> i7010 IBM 704 -> i704 IBM 704/709/7090/7094 -> i7090 The i7090 can be set to simulate a IBM 704 however you end up disabling almost everything, since the 704 did not have any channels. A build option exists that allows this one to be built without all the extra features. The i7090 simulator’s implementation of the IBM 7094 is a more complete implementation of the IBM 7094 which can run CTSS while the existing simh I7094 can’t.
253 lines
8.2 KiB
C
253 lines
8.2 KiB
C
/* i7090_drum.c: IBM 7320A High Speed Drum
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Copyright (c) 2005-2016, Richard Cornwell
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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RICHARD CORNWELL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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High speed drum for CTSS
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*/
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#include "i7090_defs.h"
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#ifdef NUM_DEVS_HD
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#define UNIT_DRM UNIT_ATTABLE | UNIT_DISABLE | UNIT_FIX | \
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UNIT_BUFABLE | UNIT_MUSTBUF
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/* Device status information stored in u5 */
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#define DRMSTA_READ 000001 /* Unit is in read */
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#define DRMSTA_WRITE 000002 /* Unit is in write */
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#define DRMSTA_START 000004 /* Which half of drum accessing */
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#define DRMSTA_CMD 000010 /* Unit has recieved a cmd */
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#define DRMSTA_UNIT 000700 /* Unitmask */
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#define DRMSTA_SHFT 6
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uint32 hsdrm_cmd(UNIT *, uint16, uint16);
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t_stat hsdrm_srv(UNIT *);
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void hsdrm_ini(UNIT *, t_bool);
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t_stat hsdrm_reset(DEVICE *);
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t_uint64 hsdrm_addr; /* Read/write drum address */
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t_stat set_hunits(UNIT * uptr, int32 val, CONST char *cptr, void *desc);
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t_stat get_hunits(FILE * st, UNIT * uptr, int32 v, CONST void *desc);
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t_stat hsdrm_attach(UNIT * uptr, CONST char *file);
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t_stat hsdrm_detach(UNIT * uptr);
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t_stat hsdrm_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag,
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const char *cptr);
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const char *hsdrm_description (DEVICE *dptr);
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UNIT hsdrm_unit[] = {
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{UDATA (&hsdrm_srv, UNIT_S_CHAN(7) | UNIT_DRM,
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NUM_UNITS_HD * 8 * 32767), 0, NUM_UNITS_HD},
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};
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MTAB hsdrm_mod[] = {
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{MTAB_XTD | MTAB_VUN | MTAB_VALR, 0, "UNITS", "UNITS",
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&set_hunits, &get_hunits, NULL},
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{MTAB_XTD | MTAB_VUN | MTAB_VALR, 0, "CHAN", "CHAN",
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&set_chan, &get_chan, NULL},
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{0}
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};
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DEVICE hsdrm_dev = {
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"HD", hsdrm_unit, NULL /* Registers */ , hsdrm_mod,
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NUM_DEVS_HD, 8, 15, 1, 8, 36,
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NULL, NULL, &hsdrm_reset, NULL, &hsdrm_attach, &hsdrm_detach,
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&hsdrm_dib, DEV_DISABLE | DEV_DEBUG, 0, dev_debug,
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NULL, NULL, &hsdrm_help, NULL, NULL, &hsdrm_description
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};
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uint32 hsdrm_cmd(UNIT * uptr, uint16 cmd, uint16 dev)
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{
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int chan = UNIT_G_CHAN(uptr->flags);
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if ((uptr->flags & UNIT_ATT) != 0) {
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/* Delay if transfer still in progress. */
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if (chan_active(chan))
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return SCPE_BUSY;
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/* Wait for device to time out */
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if (uptr->u5 & DRMSTA_CMD)
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return SCPE_BUSY;
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switch (cmd) {
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case IO_RDS:
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/* Start device */
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uptr->u5 = DRMSTA_READ | DRMSTA_CMD;
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chan_set_sel(chan, 0);
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sim_debug(DEBUG_CMD, &hsdrm_dev, "RDS dev %o\n", dev);
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break;
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case IO_WRS:
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/* Start device */
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uptr->hwmark = uptr->capac; /* Mark as changed */
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uptr->u5 = DRMSTA_WRITE | DRMSTA_CMD;
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chan_set_sel(chan, 1);
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sim_debug(DEBUG_CMD, &hsdrm_dev, "WRS dev %o\n", dev);
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break;
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default:
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return SCPE_IOERR;
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}
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hsdrm_addr = 0; /* Set drum address */
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if (!sim_is_active(uptr))
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sim_activate(uptr, us_to_ticks(100));
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return SCPE_OK;
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}
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return SCPE_IOERR;
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}
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t_stat hsdrm_srv(UNIT * uptr)
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{
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int chan = UNIT_G_CHAN(uptr->flags);
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t_uint64 *buf = (t_uint64 *)uptr->filebuf;
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t_stat r;
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/* Channel has disconnected, abort current read. */
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if (uptr->u5 & DRMSTA_CMD && chan_stat(chan, DEV_DISCO)) {
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uptr->u5 = 0;
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chan_clear(chan, DEV_WEOR | DEV_SEL);
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sim_debug(DEBUG_CHAN, &hsdrm_dev, "disconnecting\n");
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sim_activate(uptr, us_to_ticks(50));
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}
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uptr->u6++; /* Adjust rotation */
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uptr->u6 &= 007777;
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/* Check if we have a address match */
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if ((chan_flags[chan] & (STA_ACTIVE | DEV_SEL)) == (STA_ACTIVE | DEV_SEL)
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&& uptr->u5 & (DRMSTA_READ | DRMSTA_WRITE)
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&& (uint32)uptr->u6 == (hsdrm_addr & 007777)) {
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int addr =
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((hsdrm_addr >> 12) & 07000000) |
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((hsdrm_addr >> 3) & 0700000) |
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(hsdrm_addr & 077777);
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sim_debug(DEBUG_DETAIL, &hsdrm_dev, "drum addr %o\n\r", addr);
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if (((addr >> 18) & 07) > uptr->u3) {
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chan_set(chan, DEV_REOR | CHS_ATTN | CHS_ERR);
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goto next;
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}
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/* Flag to disconnect without setting iocheck */
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if (uptr->u5 & DRMSTA_READ)
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r = chan_write(chan, &buf[addr], DEV_DISCO);
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else
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r = chan_read(chan, &buf[addr], DEV_DISCO);
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switch (r) {
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case DATA_OK:
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sim_debug(DEBUG_DATA, &hsdrm_dev,
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"transfer %s %o: %012llo\n\r",
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(uptr->u5 & DRMSTA_READ) ? "read" : "write",
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addr, buf[addr]);
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hsdrm_addr++;
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hsdrm_addr &= 070007077777LL;
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if ((hsdrm_addr & (2048 - 1)) == 0)
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chan_set(chan, DEV_REOR);
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break;
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case END_RECORD:
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case TIME_ERROR:
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uptr->u5 = DRMSTA_CMD;
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break;
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}
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}
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next:
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sim_activate(uptr, us_to_ticks(20));
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return SCPE_OK;
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}
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void
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hsdrm_ini(UNIT * uptr, t_bool f)
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{
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uptr->u5 = 0;
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}
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t_stat
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hsdrm_reset(DEVICE * dptr)
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{
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return SCPE_OK;
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}
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/* Sets the number of drum units */
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t_stat
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set_hunits(UNIT * uptr, int32 val, CONST char *cptr, void *desc)
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{
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int i;
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if (cptr == NULL)
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return SCPE_ARG;
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if (uptr == NULL)
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return SCPE_IERR;
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if (uptr->flags & UNIT_ATT)
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return SCPE_ALATT;
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i = 0;
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while (*cptr != '\0') {
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if (*cptr < '0' || *cptr > '9')
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return SCPE_ARG;
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i = (i * 10) + (*cptr++) - '0';
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}
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if (i < 0 || i > NUM_UNITS_HD)
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return SCPE_ARG;
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uptr->capac = i * 32767 * 8;
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uptr->u3 = i;
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return SCPE_OK;
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}
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t_stat
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get_hunits(FILE * st, UNIT * uptr, int32 v, CONST void *desc)
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{
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if (uptr == NULL)
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return SCPE_IERR;
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fprintf(st, "Units=%d", uptr->u3);
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return SCPE_OK;
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}
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t_stat
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hsdrm_attach(UNIT * uptr, CONST char *file)
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{
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t_stat r;
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if ((r = attach_unit(uptr, file)) != SCPE_OK)
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return r;
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sim_activate(uptr, us_to_ticks(100));
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return SCPE_OK;
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}
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t_stat
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hsdrm_detach(UNIT * uptr)
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{
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sim_cancel(uptr);
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return detach_unit(uptr);
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}
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t_stat
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hsdrm_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
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{
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fprintf (st, "%s\n\n", hsdrm_description(dptr));
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fprintf (st, "The High speed drum supports up to %d units of storage\n", NUM_UNITS_HD);
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fprintf (st, "Each unit held 265k words of data\n");
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help_set_chan_type(st, dptr, "High speed drum");
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fprint_set_help(st, dptr);
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fprint_show_help(st, dptr);
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return SCPE_OK;
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}
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const char *
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hsdrm_description (DEVICE *dptr)
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{
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return "IBM 7320A Drum for CTSS";
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}
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#endif
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