b5ea9ec38e
These include simulators for the IBM 701, IBM 702, IBM 704, IBM 705, IBM 705/3, IBM 709, IBM 1410/IBM 7010, IBM 7070, IBM 7080, IBM 7090 and IBM7094. These basically were a collection of machines that shared a common set it peripherals, Each group had its own instruction set, hence different simulators. IBM 701 -> i701 IBM 702/705/705/3/7080 -> i7080 IBM 7070/7074 -> i7070 IBM 1410/7010 -> i7010 IBM 704 -> i704 IBM 704/709/7090/7094 -> i7090 The i7090 can be set to simulate a IBM 704 however you end up disabling almost everything, since the 704 did not have any channels. A build option exists that allows this one to be built without all the extra features. The i7090 simulator’s implementation of the IBM 7094 is a more complete implementation of the IBM 7094 which can run CTSS while the existing simh I7094 can’t.
339 lines
11 KiB
C
339 lines
11 KiB
C
/* i7090_cdr.c: IBM 7090 Card Read.
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Copyright (c) 2005-2016, Richard Cornwell
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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RICHARD CORNWELL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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This is the standard card reader.
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*/
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#include "i7090_defs.h"
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#include "sim_card.h"
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#ifdef NUM_DEVS_CDR
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#define UNIT_CDR UNIT_ATTABLE | UNIT_RO | UNIT_DISABLE | UNIT_ROABLE |\
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MODE_026
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/* std devices. data structures
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chan_dev Channel device descriptor
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chan_unit Channel unit descriptor
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chan_reg Channel register list
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chan_mod Channel modifiers list
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*/
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/* Device status information stored in u5 */
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#define CDRSTA_EOR 002000 /* Hit end of record */
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#define CDRPOSMASK 0770000 /* Bit Mask to retrive drum position */
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#define CDRPOSSHIFT 12
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t_stat cdr_srv(UNIT *);
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t_stat cdr_boot(int32, DEVICE *);
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t_stat cdr_reset(DEVICE *);
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t_stat cdr_attach(UNIT *, CONST char *);
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t_stat cdr_detach(UNIT *);
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t_stat cdr_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag,
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const char *cptr);
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const char *cdr_description (DEVICE *dptr);
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UNIT cdr_unit[] = {
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#if NUM_DEVS_CDR > 1
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{UDATA(&cdr_srv, UNIT_S_CHAN(CHAN_A) | UNIT_CDR, 0), 3000}, /* A */
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#endif
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#if NUM_DEVS_CDR > 2
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{UDATA(&cdr_srv, UNIT_S_CHAN(CHAN_C) | UNIT_CDR, 0), 3000}, /* B */
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#endif
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#if NUM_DEVS_CDR > 3
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{UDATA(&cdr_srv, UNIT_S_CHAN(CHAN_E) | UNIT_CDR | UNIT_DIS, 0), 3000}, /* C */
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#endif
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{UDATA(&cdr_srv, UNIT_S_CHAN(CHAN_CHPIO) | UNIT_CDR, 0), 3000}, /* D */
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};
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MTAB cdr_mod[] = {
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{MTAB_XTD | MTAB_VUN, 0, "FORMAT", "FORMAT",
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&sim_card_set_fmt, &sim_card_show_fmt, NULL},
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#if NUM_CHAN != 1
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{MTAB_XTD | MTAB_VUN | MTAB_VALR, 0, "CHAN", "CHAN", &set_chan,
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&get_chan, NULL},
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#endif
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{0}
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};
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DEVICE cdr_dev = {
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"CDR", cdr_unit, NULL, cdr_mod,
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NUM_DEVS_CDR, 8, 15, 1, 8, 36,
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NULL, NULL, &cdr_reset, &cdr_boot, &cdr_attach, &cdr_detach,
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&cdr_dib, DEV_DISABLE | DEV_DEBUG, 0, crd_debug,
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NULL, NULL, &cdr_help, NULL, NULL, &cdr_description
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};
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uint32 cdr_cmd(UNIT * uptr, uint16 cmd, uint16 dev)
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{
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int chan = UNIT_G_CHAN(uptr->flags);
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if ((uptr->flags & UNIT_ATT) != 0 && cmd == IO_RDS) {
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int u = (uptr - cdr_unit);
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/* Start device */
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if ((uptr->u5 & URCSTA_CMD) == 0) {
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if ((uptr->u5 & (URCSTA_ON | URCSTA_IDLE)) ==
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(URCSTA_ON | URCSTA_IDLE) && (uptr->wait <= 60)) {
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uptr->wait += 100; /* Wait for next latch point */
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} else
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uptr->wait = 75; /* Startup delay */
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uptr->u5 |= URCSTA_READ | URCSTA_CMD | CDRPOSMASK;
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chan_set_sel(chan, 0);
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chan_clear_status(chan);
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sim_activate(uptr, us_to_ticks(1000)); /* activate */
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sim_debug(DEBUG_CMD, &cdr_dev, "RDS unit=%d\n", u);
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return SCPE_OK;
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}
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return SCPE_BUSY;
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}
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chan_set_attn(chan);
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return SCPE_NODEV;
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}
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t_stat cdr_srv(UNIT * uptr)
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{
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int chan = UNIT_G_CHAN(uptr->flags);
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int u = (uptr - cdr_unit);
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int pos, col, b;
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uint16 bit;
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t_uint64 mask, wd;
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struct _card_data *data;
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/* Channel has disconnected, abort current read. */
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if (uptr->u5 & URCSTA_CMD && chan_stat(chan, DEV_DISCO)) {
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uptr->u5 &= ~(URCSTA_READ | URCSTA_CMD);
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uptr->u5 |= CDRPOSMASK;
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chan_clear(chan, DEV_WEOR | DEV_SEL);
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sim_debug(DEBUG_CHAN, &cdr_dev, "unit=%d disconnecting\n", u);
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}
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/* Check to see if we have timed out */
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if (uptr->wait != 0) {
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/* If at end of record and channel is still active, do another read */
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if (uptr->wait == 30
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&& ((uptr->u5 & (URCSTA_CMD|URCSTA_IDLE|URCSTA_READ|URCSTA_ON))
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== (URCSTA_CMD | URCSTA_IDLE | URCSTA_ON))
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&& chan_test(chan, STA_ACTIVE)) {
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uptr->u5 |= URCSTA_READ;
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sim_debug(DEBUG_CHAN, &cdr_dev, "unit=%d restarting\n", u);
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}
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uptr->wait--;
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sim_activate(uptr, us_to_ticks(1000)); /* activate */
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return SCPE_OK;
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}
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/* If no read request, go to idle mode */
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if ((uptr->u5 & URCSTA_READ) == 0) {
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if ((uptr->u5 & URCSTA_EOF) || (uptr->u5 & URCSTA_IDLE)) {
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uptr->u5 &= ~(URCSTA_ON | URCSTA_IDLE); /* Turn motor off */
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} else {
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uptr->wait = 85; /* Delay 85ms */
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uptr->u5 |= URCSTA_IDLE; /* Go idle */
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sim_activate(uptr, us_to_ticks(1000));
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}
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return SCPE_OK;
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}
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/* Motor is up to speed now */
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uptr->u5 |= URCSTA_ON;
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uptr->u5 &= ~URCSTA_IDLE;
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pos = (uptr->u5 & CDRPOSMASK) >> CDRPOSSHIFT;
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if (pos == (CDRPOSMASK >> CDRPOSSHIFT)) {
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switch (sim_read_card(uptr)) {
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case SCPE_UNATT:
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case SCPE_IOERR:
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sim_debug(DEBUG_EXP, &cdr_dev, "unit=%d Setting ATTN\n", u);
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chan_set_error(chan);
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chan_set_attn(chan);
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uptr->u5 &= ~URCSTA_READ;
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sim_activate(uptr, us_to_ticks(1000));
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return SCPE_OK;
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case SCPE_EOF:
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sim_debug(DEBUG_EXP, &cdr_dev, "unit=%d EOF\n", u);
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chan_set_eof(chan);
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chan_set_attn(chan);
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uptr->u5 &= ~URCSTA_READ;
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sim_activate(uptr, us_to_ticks(1000));
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return SCPE_OK;
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case SCPE_OK:
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break;
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}
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pos = 0;
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}
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/* Check if everything read in, if so return EOR now */
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if (pos == 24) {
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sim_debug(DEBUG_CHAN, &cdr_dev, "unit=%d set EOR\n", u);
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chan_set(chan, DEV_REOR);
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uptr->u5 &= ~URCSTA_READ;
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uptr->u5 |= CDRSTA_EOR | CDRPOSMASK;
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uptr->wait = 86;
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sim_activate(uptr, us_to_ticks(1000));
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return SCPE_OK;
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}
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data = (struct _card_data *)uptr->up7;
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/* Bit flip into read buffer */
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bit = 1 << (pos / 2);
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mask = 1;
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wd = 0;
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b = (pos & 1)?36:0;
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for (col = 35; col >= 0; mask <<= 1) {
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if (data->image[col-- + b] & bit)
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wd |= mask;
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}
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switch (chan_write (chan, &wd,/* (pos == 23) ? DEV_REOR :*/ 0)) {
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case DATA_OK:
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sim_debug(DEBUG_DATA, &cdr_dev, "unit=%d read row %d %012llo\n", u,
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pos, wd);
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pos++;
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uptr->u5 &= ~CDRPOSMASK;
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uptr->u5 |= pos << CDRPOSSHIFT;
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uptr->wait = 0;
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sim_activate(uptr, (pos & 1) ? us_to_ticks(300) : us_to_ticks(8000));
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return SCPE_OK;
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case END_RECORD:
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sim_debug(DEBUG_CHAN, &cdr_dev, "unit=%d got EOR\n", u);
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uptr->u5 &= ~CDRPOSMASK;
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uptr->u5 |= 24 << CDRPOSSHIFT;
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uptr->wait = 8 * (12 - (pos / 2)) /*+ 86*/;
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break;
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case TIME_ERROR:
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sim_debug(DEBUG_EXP, &cdr_dev, "unit=%d no data\n", u);
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uptr->u5 &= ~CDRPOSMASK;
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uptr->u5 |= 24 << CDRPOSSHIFT;
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uptr->wait = 8 * (12 - (pos / 2)) /*+ 85*/;
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break;
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}
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sim_activate(uptr, us_to_ticks(1000));
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return SCPE_OK;
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}
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/* Boot from given device */
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t_stat
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cdr_boot(int32 unit_num, DEVICE * dptr)
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{
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UNIT *uptr = &dptr->units[unit_num];
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int chan = UNIT_G_CHAN(uptr->flags);
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t_stat r;
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int pos;
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struct _card_data *data;
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if ((uptr->flags & UNIT_ATT) == 0)
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return SCPE_UNATT; /* attached? */
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uptr->u5 = 0;
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/* Init for a read */
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if (cdr_cmd(uptr, IO_RDS, cdr_dib.addr) != SCPE_OK)
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return STOP_IONRDY;
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r = sim_read_card(uptr);
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if (r != SCPE_OK)
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return r;
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/* Copy first three records. */
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data = (struct _card_data *)uptr->up7;
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uptr->u5 &= ~CDRPOSMASK;
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for(pos = 0; pos <3; pos++) {
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uint16 bit = 1 << (pos / 2);
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t_uint64 mask = 1;
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int b = (pos & 1)?36:0;
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int col;
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if (pos == 2 && chan == 0)
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break;
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M[pos] = 0;
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for (col = 35; col >= 0; mask <<= 1) {
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if (data->image[col-- + b] & bit)
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M[pos] |= mask;
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}
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sim_debug(DEBUG_DATA, &cdr_dev, "boot read row %d %012llo\n",
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pos, M[pos]);
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}
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uptr->u5 |= pos << CDRPOSSHIFT;
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/* Make sure channel is set to start reading rest. */
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return chan_boot(unit_num, dptr);
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}
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t_stat
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cdr_reset(DEVICE * dptr)
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{
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return SCPE_OK;
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}
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t_stat
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cdr_attach(UNIT * uptr, CONST char *file)
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{
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t_stat r;
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if ((r = sim_card_attach(uptr, file)) != SCPE_OK)
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return r;
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uptr->u5 = 0;
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uptr->u4 = 0;
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return SCPE_OK;
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}
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t_stat
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cdr_detach(UNIT * uptr)
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{
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return sim_card_detach(uptr);
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}
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t_stat
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cdr_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
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{
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const char *cpu = cpu_description(&cpu_dev);
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fprintf (st, "%s\n\n", cdr_description(dptr));
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#if NUM_DEVS_CDR > 3
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fprintf (st, "The %s supports up to four card readers\n\n", cpu);
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#elif NUM_DEVS_CDR > 2
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fprintf (st, "The %s supports up to three card readers\n\n", cpu);
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#elif NUM_DEVS_CDR > 1
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fprintf (st, "The %s supports up to two card readers\n\n", cpu);
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#elif NUM_DEVS_CDR > 0
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fprintf (st, "The %s supports one card reader\n\n", cpu);
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#endif
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help_set_chan_type(st, dptr, "Card readers");
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fprint_set_help(st, dptr);
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fprint_show_help(st, dptr);
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fprintf (st, "\n");
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sim_card_attach_help(st, dptr, uptr, flag, cptr);
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return SCPE_OK;
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}
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const char *
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cdr_description(DEVICE *dptr)
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{
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return "711 Card Reader";
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}
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#endif
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