5531ccb175
These changes facilitate more robust parameter type checking and helps to identify unexpected coding errors. Most simulators can now also be compiled with a C++ compiler without warnings. Additionally, these changes have also been configured to facilitate easier backporting of simulator and device simulation modules to run under the simh v3.9+ SCP framework.
637 lines
21 KiB
C
637 lines
21 KiB
C
/* sage_stddev.c: Standard devices for sage-II system
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Copyright (c) 2009-2010 Holger Veit
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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Holger Veit BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Holger Veit et al shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Holger Veit et al.
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04-Oct-09 HV Initial version
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*/
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#include "sim_defs.h"
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#include "m68k_cpu.h"
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#include "sage_defs.h"
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/***********************************************************************************
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* 8259-5 interrupt controller
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*
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* IRQ output hardwired to Interrupt Priority Level 1 in the Sage
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* Level 2: from external bus (wired to HDC board, AUX devices)
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* Level 3: from external bus
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* Level 4: IEEE 488 Interrupt U6
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* Level 5: Console Uart U67 Receiver Interrupt
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* Level 6: FDI floppy controller
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* Level 7: nonmaskable RAM parity error (not possible in simh)
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*
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* hardwired inputs:
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* IR0 = Output 2 of U74 real time clock
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* IR1 = Modem Uart U58 Receiver Interrupt
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* IR2 = Console Uart U67 Transmitter Interrupt
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* IR3 = Modem Uart U58 Receiver Interrupt
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* IR4 = Modem Carrier Detect Interrupt U38
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* IR5 = LP Port Acknowledge U39/U38
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* IR6 = Output 0 of U74 real time clock
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* IR7 = Output C2 of U39
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*
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* Notes:
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* INTA- is hardwired to VCC, so vectoring is not possible
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* SP- is hardwired to VCC, so buffered mode is not possible, and device is a master.
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* CAS0-2 lines are open, no need to handle
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* UCSD bios and boot prom do not program the PIC for rotating priorities,
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* so effectively prio is always 7.
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*
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**********************************************************************************/
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extern DEVICE sagepic_dev;
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static t_stat sagepic_reset(DEVICE* dptr);
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static I8259 u73 = { {0,0,U73_ADDR,4,2},
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&sagepic_dev,NULL,NULL,i8259_reset
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};
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UNIT sagepic_unit = {
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UDATA (NULL, UNIT_IDLE, 0)
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};
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REG sagepic_reg[] = {
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{ DRDATA(STATE, u73.state, 8) },
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{ HRDATA(IRR, u73.irr, 8) },
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{ HRDATA(IMR, u73.imr, 8) },
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{ HRDATA(ISR, u73.isr, 8) },
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{ HRDATA(ICW1, u73.icw1, 8) },
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{ HRDATA(ICW2, u73.icw2, 8) },
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{ HRDATA(ICW4, u73.icw4, 8) },
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{ HRDATA(OCW2, u73.prio, 3) },
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{ NULL }
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};
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static MTAB sagepic_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 0, "IO", "IO", &set_iobase, &show_iobase, NULL },
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{ 0 }
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};
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DEVICE sagepic_dev = {
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"PIC", &sagepic_unit, sagepic_reg, sagepic_mod,
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1, 16, 32, 2, 16, 16,
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NULL, NULL, &sagepic_reset,
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NULL, NULL, NULL,
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&u73, DEV_DEBUG, 0,
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i8259_dt, NULL, NULL
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};
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static t_stat sagepic_reset(DEVICE* dptr)
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{
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t_stat rc;
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if ((rc = (dptr->flags & DEV_DIS) ?
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del_iohandler(dptr->ctxt) :
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add_iohandler(&sagepic_unit,dptr->ctxt,i8259_io)) != SCPE_OK) return rc;
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return u73.reset(&u73);
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}
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t_stat sage_raiseint(int level)
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{
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return i8259_raiseint(&u73,level);
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}
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/******************************************************************************************************
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* DIP switches at the back panel.
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*
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* In the technical manual, switches are layed out 12345678 left to right,
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* but here seen as two HEX digits 8765 4321, i.e. 0xc0 is bit 8 and bit 7 set on
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*
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* a "d" (down) means switch is off or "0", and a "u" (up) means switch is on or "1"
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*
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* Note that programatically dip switches are port a and b of the onboard 8255 U22
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* which also through port c serves part of the FDC signals
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*
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* group-a:
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* 8 7 6 5 4 3 2 1
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* | | | | | d d d--- 19,2K baud
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* | | | | | d d u--- 9600 baud
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* | | | | | d u d--- 4800 baud
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* | | | | | d u u--- 2400 baud
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* | | | | | u d d--- 1200 baud
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* | | | | | u d u--- 600 baud
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* | | | | | u u d--- 300 baud
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* | | | | | u u u--- reserved
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* | | | | d--------- even parity
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* | | | | u--------- parity disabled
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* | | d d----------- boot to debugger
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* | | d u----------- boot to floppy 0
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* | | u d----------- boot to harddisk 0 partition 0
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* | | u u----------- reserved
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* | d--------------- 96 tpi drive
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* | u--------------- 48 tpi drive
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* x----------------- reserved
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*
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* group-b:
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* 8 7 6 5 4 3 2 1
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* | | | +-+-+-+-+--- device talk and listen address
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* | | u------------- enable talk
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* | | d------------- disable talk
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* | u--------------- enable listen
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* | d--------------- disable listen
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* u----------------- 2 consecutive addresses
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* d----------------- 1 address
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*/
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#if defined(SAGE_IV)
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uint32 groupa = 0xd7; /* used by cons device, 19k2, no parity, boot floppy 0 */
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uint32 groupb = 0xf8; /* used by ieee device */
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#else
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uint32 groupa = 0xe7; /* used by cons device, 19k2, no parity, boot winchester 0 */
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uint32 groupb = 0xf8; /* used by ieee device */
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#endif
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static t_stat sagedip_reset(DEVICE* dptr);
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static t_stat set_groupa(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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static t_stat show_groupa(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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static t_stat set_groupb(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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static t_stat show_groupb(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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static t_stat u22_reset(I8255* chip);
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static t_stat u22_calla(I8255* chip,int rw);
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static t_stat u22_callb(I8255* chip,int rw);
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static t_stat u22_callc(I8255* chip,int rw);
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static t_stat u22_ckmode(I8255* chip,uint32 data);
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extern DEVICE sagedip_dev;
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static I8255 u22 = {
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{ 0,0,U22_ADDR,8,2 },
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&sagedip_dev,i8255_write,i8255_read,u22_reset,u22_calla,u22_callb,u22_callc,u22_ckmode
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};
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uint32* u22_portc = &u22.portc; /* this is used in the FD device as well, but whole 8255 is handled here */
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UNIT sagedip_unit = {
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UDATA (NULL, UNIT_IDLE, 0)
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};
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REG sagedip_reg[] = {
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{ HRDATA(PORTA, u22.porta, 8) },
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{ HRDATA(PORTB, u22.portb, 8) },
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{ HRDATA(PORTC, u22.portc, 8) },
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{ HRDATA(CTRL, u22.ctrl, 8) },
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{ NULL }
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};
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static MTAB sagedip_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 0, "IO", "IO", &set_iobase, &show_iobase, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "GROUPA", "GROUPA", &set_groupa, &show_groupa, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "GROUPB", "GROUPB", &set_groupb, &show_groupb, NULL },
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{ 0 }
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};
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/* Debug Flags */
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DEBTAB sagedip_dt[] = {
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{ "RDA", DBG_PP_RDA },
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{ "RDB", DBG_PP_RDB },
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{ "WRC", DBG_PP_WRC },
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{ "WRMODE", DBG_PP_MODE },
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{ NULL, 0 }
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};
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DEVICE sagedip_dev = {
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"DIP", &sagedip_unit, sagedip_reg, sagedip_mod,
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1, 16, 32, 2, 16, 16,
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NULL, NULL, &sagedip_reset,
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NULL, NULL, NULL,
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&u22, DEV_DEBUG, 0,
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sagedip_dt, NULL, NULL
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};
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static t_stat sagedip_reset(DEVICE* dptr)
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{
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t_stat rc;
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if ((rc = (dptr->flags & DEV_DIS) ? /* Disconnect I/O Ports */
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del_iohandler(dptr->ctxt) :
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add_iohandler(&sagedip_unit,dptr->ctxt,i8255_io)) != SCPE_OK) return rc;
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/* clear 8255 ctrl register */
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return u22.reset(&u22);
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}
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static t_stat set_gr(const char* cptr, uint32* sw)
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{
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int i;
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char c;
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if (!cptr) return SCPE_ARG;
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*sw = 0;
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for (i=0; *cptr && i<8; i++) {
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c = *cptr++;
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*sw <<= 1;
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if (c=='1') *sw |= 1;
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else if (c=='0') continue;
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else if (c==0) break;
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else return SCPE_ARG;
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}
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return SCPE_OK;
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}
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static t_stat set_groupa(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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return set_gr(cptr,&groupa);
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}
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static t_stat set_groupb(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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return set_gr(cptr,&groupb);
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}
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static t_stat show_gr(FILE* st, const char* prefix, uint32 gr)
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{
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int i;
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fputs(prefix, st);
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for (i = 0x80; i > 0; i = i >> 1)
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fprintf(st,"%c", gr&i ? '1' : '0');
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return SCPE_OK;
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}
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static t_stat show_groupa(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
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{
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return show_gr(st, "GROUPA=", groupa);
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}
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static t_stat show_groupb(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
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{
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return show_gr(st, "GROUPB=", groupb);
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}
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static t_stat u22_reset(I8255* chip)
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{
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chip->ctrl = 0;
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chip->portc = 0;
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return SCPE_OK;
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}
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extern I8272 u21;
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static t_stat u22_calla(I8255* chip,int rw)
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{
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if (rw==0) {
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chip->porta = groupa & 0xff;
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TRACE_PRINT1(DBG_PP_RDA,"WR PortA: 0x%x",groupa);
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}
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return SCPE_OK;
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}
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static t_stat u22_callb(I8255* chip,int rw)
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{
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if (rw==0) {
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chip->portb = groupb & 0xff;
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TRACE_PRINT1(DBG_PP_RDA,"WR PortB: 0x%x",groupb);
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}
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return SCPE_OK;
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}
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/* callback handler for FDC bits */
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static t_stat u22_callc(I8255* chip,int rw)
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{
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/* bit0: TC+ positive enforce that internal data counter of FDC is reset
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* bit1: RDY+ positive enable the FDC
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* bit2: FDIE+ positive enable FDC interrupt (handled directly by reading portc in sage_fd.c)
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* bit3: SL0- negative select of drive 0
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* bit4: SL1- negative select of drive 1
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* bit5: MOT- negative switch on drive motor (ignored)
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* bit6: PCRMP- negative precompensation (ignored)
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* bit7: FRES+ positive FDC reset
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*/
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if (I8255_ISSET(portc,U22C_TC)) { /* TC+ */
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i8272_finish(&u21); /* terminate a read/write in progress */
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}
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if (I8255_ISCLR(portc,U22C_RDY)) { /* RDY+ */
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i8272_abortio(&u21); /* abort current op */
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}
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if (I8255_ISCLR(portc,U22C_SL0)) { /* SL0- */
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u21.fdc_curdrv = 0;
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} else if (I8255_ISCLR(portc,U22C_SL1)) { /* SL1- */
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u21.fdc_curdrv = 1;
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} else if (I8255_ISSET(portc,U22C_SL0|U22C_SL1)) { /* deselect drives */
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u21.fdc_curdrv = 0;
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}
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if (I8255_ISSET(portc,U22C_FRES)) { /* FRES+ */
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i8272_reset(&u21);
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}
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TRACE_PRINT(DBG_PP_WRC,(sim_deb,"PORTC Flags: %s%s%s%s%s%s%s%s",
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I8255_ISSET(portc,U22C_TC)?"TC ":"",
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I8255_ISSET(portc,U22C_RDY)?"RDY ":"",
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I8255_ISSET(portc,U22C_FDIE)?"FDIE ":"",
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I8255_ISSET(portc,U22C_SL0)?"":"SL0 ",
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I8255_ISSET(portc,U22C_SL1)?"":"SL1 ",
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I8255_ISSET(portc,U22C_MOT)?"":"MOT ",
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I8255_ISSET(portc,U22C_PCRMP)?"":"PCRMP ",
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I8255_ISSET(portc,U22C_FRES)?"FRES ":""));
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return SCPE_OK;
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}
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static t_stat u22_ckmode(I8255* chip, uint32 data)
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{
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/* hardwired:
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* d7=1 -- mode set flag
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* d6=0 -+ group a mode 0: basic I/O
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* d5=0 -+
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* d4=1 -- porta = input
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* d3=0 -- portc upper = output
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* d2=0 -- group b mode 0: basic I/O
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* d1=1 -- portb = input
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* d0=0 -- portc lower = output
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*/
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TRACE_PRINT1(DBG_PP_MODE,"WR Mode: 0x%x",data);
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if (data != 0x92) {
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printf("u22_ckmode: unsupported ctrl=0x%02x\n",data);
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return STOP_IMPL;
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}
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return SCPE_OK;
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}
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/***********************************************************************************
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* Two 8553 timers U75 (TIMER1) and U74 (TIMER2)
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* Each contain three 8/16 bit timers
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* In the sage hardwired in the following way:
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*
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* +---------+
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* 615kHz--+->|Timer1 C1|---> Baud ser0
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* | +---------+
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* +->|Timer1 C2|---> Baud ser1
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* +---------+
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* +---------+ +---------+
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* 64kHz---+->|Timer1 C0|--->|Timer2 C0|--> PIC IR6
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* | |div 64000| |mode0 |
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* | +---------+ +---------+
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* | +---------+ +---------+
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* +->|Timer2 C1|--->|Timer2 C2|--> PIC IR0
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* | | | |
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* +---------+ +---------+
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*
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* NOT UNITS: Timer1 C1 and C2 are programmed in mode 2 as clock dividers for the USARTs
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* In this emulation we allow programming them, but since they don't produce interrupts,
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* their work is ignored.
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*
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* Timer1 C0 and timer2 C0 form a clock divider which produces an interrupt at PIC level 6
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* Likewise, timer2 C1 and timer2 C2 form a clock divider which produces an interrupt at PIC level 0
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*
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* Typically, the first one in cascade is programmed in mode 2, the second one in mode 0.
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* Timer1 C0 is explicitly programmed as a divider by 64k, so that it feeds timer2 C0
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* with a 1Hz clock.
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*
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* The way the timers are hardwired makes certain mode settings impossible: all GATE
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* inputs are set to VCC, so MODE1 and MODE5 are impossible, and MODE4 becomes a
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* variant of MODE0. MODE3 is used by the baudrate generators. The timers may run in
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* 8 bit mode, but analysis of existing BIOS code (BOOT PROM and UCSD BIOS) uncovered
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* they are used in 16 bit mode only.
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* So, this implementation only contains the most likely usages, and the other ones have
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* to be added when there is a necessity.
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*
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* Notes on actual implementation:
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* Since we know the input clocks, we have just to take care about the division factors
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* stored in T1C0 and T2C1. Whenever one of these timers are read out, the actual count
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* has to be calculated on the fly. The actual cnt registers only hold the count factors
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* programmed, but are never counted down, as, in the case of the 64kHz clock this would
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* mean to trigger sim_* events 64000 times a second.
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*
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***********************************************************************************/
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/************************************************************************************
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* timer 1
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***********************************************************************************/
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static t_stat sagetimer1_reset(DEVICE* dptr);
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static t_stat timer1_svc(UNIT* uptr);
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static t_stat u75_ckmode(I8253* chip, uint32 data);
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static t_stat u75_call0(I8253* chip,int addr, uint32* value);
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static t_stat sagetimer2_reset(DEVICE* dptr);
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static t_stat timer2_svc(UNIT* uptr);
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static t_stat u74_ckmode(I8253* chip, uint32 data);
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static t_stat u74_call1(I8253* chip,int addr, uint32* value);
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extern DEVICE sagetimer1_dev;
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extern DEVICE sagetimer2_dev;
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/* forward timer 2 */
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UNIT sagetimer2_unit = {
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UDATA (&timer2_svc, UNIT_IDLE, 0)
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};
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static I8253 u74 = { {0,0,U74_ADDR,8,2},
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&sagetimer2_dev,&sagetimer2_unit,i8253_reset,u74_ckmode,
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{ { 0, }, { u74_call1, }, { 0, } }
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};
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/* timer 1 */
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UNIT sagetimer1_unit = {
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UDATA (&timer1_svc, UNIT_IDLE, 1)
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};
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static I8253 u75 = { {0,0,U75_ADDR,8,2},
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&sagetimer1_dev,&sagetimer1_unit,i8253_reset,u75_ckmode,
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{ { u75_call0, }, { 0, }, { 0, } }
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};
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|
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REG sagetimer1_reg[] = {
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{ HRDATA(INIT, u75.init, 8), REG_HRO },
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{ HRDATA(STATE0,u75.cntr[0].state, 8),REG_HRO },
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{ HRDATA(STATE1,u75.cntr[1].state, 8),REG_HRO },
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{ HRDATA(STATE2,u75.cntr[2].state, 8),REG_HRO },
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{ HRDATA(MODE0, u75.cntr[0].mode, 8) },
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{ HRDATA(MODE1, u75.cntr[1].mode, 8) },
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{ HRDATA(MODE2, u75.cntr[2].mode, 8) },
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{ HRDATA(CNT0, u75.cntr[0].count, 16) },
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{ HRDATA(CNT1, u75.cntr[1].count, 16) },
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{ HRDATA(CNT2, u75.cntr[2].count, 16) },
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{ HRDATA(LATCH0,u75.cntr[0].latch, 16) },
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{ HRDATA(LATCH1,u75.cntr[1].latch, 16) },
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{ HRDATA(LATCH2,u75.cntr[2].latch, 16) },
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{ HRDATA(DIV0, u75.cntr[0].divider, 16),REG_HRO },
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{ HRDATA(DIV1, u75.cntr[1].divider, 16),REG_HRO },
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{ HRDATA(DIV2, u75.cntr[2].divider, 16),REG_HRO },
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{ NULL }
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};
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|
|
|
static MTAB sagetimer1_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 0, "IO", "IO", &set_iobase, &show_iobase, NULL },
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{ 0 }
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};
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|
|
|
DEVICE sagetimer1_dev = {
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"TIMER1", &sagetimer1_unit, sagetimer1_reg, sagetimer1_mod,
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1, 16, 32, 2, 16, 16,
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NULL, NULL, &sagetimer1_reset,
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NULL, NULL, NULL,
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&u75, DEV_DEBUG, 0,
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i8253_dt, NULL, NULL
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|
};
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|
|
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static t_stat sagetimer1_reset(DEVICE* dptr)
|
|
{
|
|
t_stat rc;
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|
|
|
if (dptr->flags & DEV_DIS)
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rc = del_iohandler(dptr->ctxt);
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|
else
|
|
rc = add_iohandler(&sagetimer1_unit,dptr->ctxt,i8253_io);
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if (rc != SCPE_OK)
|
|
return rc;
|
|
return u75.reset(&u75);
|
|
}
|
|
|
|
static t_stat timer1_svc(UNIT* uptr)
|
|
{
|
|
int32 wait;
|
|
I8253CNTR* t1c0 = &u75.cntr[0];
|
|
I8253CNTR* t2c0 = &u74.cntr[0];
|
|
|
|
// fprintf(sim_deb,"TIMER1: timer1_svc called T1C0=%d T2C0=%d\n",t1c0->count,t2c0->count);
|
|
/* we call this service 64000 times a second to decrement counter T1C0.
|
|
* When T1C0 reaches 0, it will decrement T2C0 */
|
|
t1c0->count--;
|
|
if (t1c0->count <= 0) {
|
|
/* reload from divider */
|
|
t1c0->count = t1c0->divider;
|
|
/* decrement T2C0 counter and raise interrupt 6 if counter is zero */
|
|
if (t2c0->count == 0) {
|
|
sage_raiseint(TIMER2C0_PICINT);
|
|
// printf("timer1 heartbeat\n");
|
|
t2c0->count = 65536;
|
|
}
|
|
t2c0->count--;
|
|
}
|
|
|
|
/* adjust timing */
|
|
wait = sim_rtcn_calb(64000,TMR_RTC1);
|
|
sim_activate(u75.unit,wait); /* 64000 ticks per second */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
static t_stat u75_ckmode(I8253* chip,uint32 mode)
|
|
{
|
|
/* @TODO check valid modes */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
static t_stat u75_call0(I8253* chip,int rw,uint32* value)
|
|
{
|
|
if (rw==1) {
|
|
I8253CNTR* cntr = &chip->cntr[0];
|
|
if ((cntr->mode & I8253_BOTH) && (cntr->state & I8253_ST_MSBNEXT)) {
|
|
sim_cancel(chip->unit);
|
|
return SCPE_OK; /* not fully loaded yet */
|
|
} else {
|
|
/* start the CK0 clock at 64000Hz */
|
|
sim_activate(chip->unit,sim_rtcn_init(64000,TMR_RTC1)); /* use timer1 C0 for this clock */
|
|
}
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
|
|
/************************************************************************************
|
|
* timer 2
|
|
***********************************************************************************/
|
|
|
|
REG sagetimer2_reg[] = {
|
|
{ HRDATA(INIT, u74.init, 8), REG_HRO },
|
|
{ HRDATA(STATE0,u74.cntr[0].state, 8),REG_HRO },
|
|
{ HRDATA(STATE1,u74.cntr[1].state, 8),REG_HRO },
|
|
{ HRDATA(STATE2,u74.cntr[2].state, 8),REG_HRO },
|
|
{ HRDATA(MODE0, u74.cntr[0].mode, 8) },
|
|
{ HRDATA(MODE1, u74.cntr[1].mode, 8) },
|
|
{ HRDATA(MODE2, u74.cntr[2].mode, 8) },
|
|
{ HRDATA(CNT0, u74.cntr[0].count, 16) },
|
|
{ HRDATA(CNT1, u74.cntr[1].count, 16) },
|
|
{ HRDATA(CNT2, u74.cntr[2].count, 16) },
|
|
{ HRDATA(LATCH0,u74.cntr[0].latch, 16) },
|
|
{ HRDATA(LATCH1,u74.cntr[1].latch, 16) },
|
|
{ HRDATA(LATCH2,u74.cntr[2].latch, 16) },
|
|
{ HRDATA(DIV0, u74.cntr[0].divider, 16),REG_HRO },
|
|
{ HRDATA(DIV1, u74.cntr[1].divider, 16),REG_HRO },
|
|
{ HRDATA(DIV2, u74.cntr[2].divider, 16),REG_HRO },
|
|
{ NULL }
|
|
};
|
|
|
|
static MTAB sagetimer2_mod[] = {
|
|
{ MTAB_XTD|MTAB_VDV, 0, "IO", "IO", &set_iobase, &show_iobase, NULL },
|
|
{ 0 }
|
|
};
|
|
|
|
DEVICE sagetimer2_dev = {
|
|
"TIMER2", &sagetimer2_unit, sagetimer2_reg, sagetimer2_mod,
|
|
1, 16, 32, 2, 16, 16,
|
|
NULL, NULL, &sagetimer2_reset,
|
|
NULL, NULL, NULL,
|
|
&u74, DEV_DEBUG, 0,
|
|
i8253_dt, NULL, NULL
|
|
};
|
|
|
|
static t_stat sagetimer2_reset(DEVICE* dptr)
|
|
{
|
|
t_stat rc;
|
|
if ((rc = (dptr->flags & DEV_DIS) ?
|
|
del_iohandler(dptr->ctxt) :
|
|
add_iohandler(&sagetimer2_unit,dptr->ctxt,i8253_io)) != SCPE_OK) return rc;
|
|
return u74.reset(&u74);
|
|
}
|
|
|
|
static t_stat u74_ckmode(I8253* chip,uint32 mode)
|
|
{
|
|
/* @TODO check valid modes */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
static t_stat u74_call1(I8253* chip,int rw,uint32* value)
|
|
{
|
|
if (rw==1) {
|
|
I8253CNTR* cntr = &chip->cntr[1];
|
|
if ((cntr->mode & I8253_BOTH) && (cntr->state & I8253_ST_MSBNEXT)) {
|
|
sim_cancel(chip->unit);
|
|
return SCPE_OK; /* not fully loaded yet */
|
|
} else {
|
|
/* start the CK0 clock at 64000Hz */
|
|
sim_activate(chip->unit,sim_rtcn_init(64000,TMR_RTC1)); /* use timer1 C0 for this clock */
|
|
}
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
static t_stat timer2_svc(UNIT* uptr)
|
|
{
|
|
int32 wait;
|
|
I8253CNTR* t2c1 = &u74.cntr[1];
|
|
I8253CNTR* t2c2 = &u74.cntr[2];
|
|
|
|
/* we call this service 64000 times a second to decrement counter T2C1.
|
|
* When T2C1 reaches 0, it will decrement T2C2 */
|
|
t2c1->count--;
|
|
if (t2c1->count <= 0) {
|
|
/* reload from divider */
|
|
t2c1->count = t2c1->divider;
|
|
/* decrement T2C2 counter and raise interrupt 0 if counter is zero */
|
|
if (t2c2->count == 0) {
|
|
// printf("timer2 heartbeat\n");
|
|
sage_raiseint(TIMER2C2_PICINT);
|
|
}
|
|
t2c2->count--;
|
|
}
|
|
|
|
/* adjust timing */
|
|
wait = sim_rtcn_calb(64000,TMR_RTC1);
|
|
sim_activate(u74.unit,wait); /* 64000 ticks per second */
|
|
return SCPE_OK;
|
|
}
|