798 lines
25 KiB
C
798 lines
25 KiB
C
/* vax630_io.c: MicroVAX II Qbus IO simulator
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Copyright (c) 2009-2012, Matt Burke
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This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name(s) of the author(s) shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from the author(s).
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qba Qbus adapter
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08-Nov-2012 MB First version
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*/
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#include "vax_defs.h"
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/* Qbus IPC register */
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#define QBIPC_QPE 0x00008000 /* Qbus dma parity err */
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#define QBIPC_AHLT 0x00000100 /* aux halt NI */
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#define QBIPC_DBIE 0x00000040 /* dbell int enb NI */
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#define QBIPC_LME 0x00000020 /* local mem enb */
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#define QBIPC_DB 0x00000001 /* doorbell req NI */
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#define QBIPC_RW (QBIPC_AHLT | QBIPC_DBIE | QBIPC_LME | QBIPC_DB)
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#define QBIPC_MASK (QBIPC_RW | QBIPC_QPE )
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BITFIELD qb_ipc_bits[] = {
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BIT(DB), /* doorbell req NI */
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BITNCF(4), /* Unused */
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BIT(LME), /* local mem enb */
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BIT(DBIE), /* dbell int enb NI */
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BITNCF(1), /* Unused */
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BIT(AHLT), /* aux halt NI */
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BITNCF(6), /* Unused */
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BIT(QPE), /* Qbus dma parity err */
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ENDBITS
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};
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/* Qbus map registers */
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#define QBNMAPR 8192 /* number of map reg */
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#define QBMAP_VLD 0x80000000 /* valid */
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#define QBMAP_PAG 0x00007FFF /* mem page */
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#define QBMAP_RD (QBMAP_VLD | QBMAP_PAG)
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#define QBMAP_WR (QBMAP_VLD | QBMAP_PAG)
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#define QB_VEC_MASK 0x1FC /* Interrupt Vector value mask */
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/* KA630 Memory system error register */
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#define MSER_NXM 0x00000080 /* CPU NXM */
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int32 int_req[IPL_HLVL] = { 0 }; /* intr, IPL 14-17 */
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int32 int_vec_set[IPL_HLVL][32] = { 0 }; /* bits to set in vector */
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int32 qb_ipc = 0; /* IPC */
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int32 qb_map[QBNMAPR] = { 0 }; /* map registers */
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int32 autcon_enb = 1; /* autoconfig enable */
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extern int32 ka_mser; /* KA630 mem sys err */
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extern int32 sys_model;
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t_stat dbl_rd (int32 *data, int32 addr, int32 access);
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t_stat dbl_wr (int32 data, int32 addr, int32 access);
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int32 eval_int (void);
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t_stat qba_reset (DEVICE *dptr);
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t_stat qba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
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t_stat qba_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
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t_bool qba_map_addr (uint32 qa, uint32 *ma);
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t_bool qba_map_addr_c (uint32 qa, uint32 *ma);
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t_stat set_autocon (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat show_autocon (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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t_stat show_iospace (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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t_stat qba_show_virt (FILE *of, UNIT *uptr, int32 val, CONST void *desc);
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t_stat qba_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
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const char *qba_description (DEVICE *dptr);
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extern int32 va_mem_rd (int32 pa);
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extern void va_mem_wr (int32 pa, int32 val, int32 lnt);
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extern int32 vc_mem_rd (int32 pa);
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extern void vc_mem_wr (int32 pa, int32 val, int32 lnt);
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/* Qbus adapter data structures
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qba_dev QBA device descriptor
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qba_unit QBA units
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qba_reg QBA register list
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*/
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#define IOLN_DBL 002
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DIB qba_dib = { IOBA_AUTO, IOLN_DBL, &dbl_rd, &dbl_wr, 0 };
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UNIT qba_unit = { UDATA (NULL, 0, 0) };
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REG qba_reg[] = {
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{ HRDATAD (IPC, qb_ipc, 16, "interprocessor communications register") },
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{ HRDATAD (IPL17, int_req[3], 32, "IPL 17 interrupt flags"), REG_RO },
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{ HRDATAD (IPL16, int_req[2], 32, "IPL 16 interrupt flags"), REG_RO },
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{ HRDATAD (IPL15, int_req[1], 32, "IPL 15 interrupt flags"), REG_RO },
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{ HRDATAD (IPL14, int_req[0], 32, "IPL 14 interrupt flags"), REG_RO },
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{ BRDATAD (MAP, qb_map, 16, 32, QBNMAPR, "map registers") },
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{ FLDATA (AUTOCON, autcon_enb, 0), REG_HRO },
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{ NULL }
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};
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MTAB qba_mod[] = {
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
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NULL, &show_iospace, NULL, "Display I/O space address map" },
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{ MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG",
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&set_autocon, &show_autocon, NULL, "Enable/Display autoconfiguration" },
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{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG",
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&set_autocon, NULL, NULL, "Disable autoconfiguration" },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL,
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NULL, &qba_show_virt, NULL, "Display translation for Qbus address arg" },
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{ 0 }
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};
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/* debugging bitmaps */
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#define DBG_REG 0x0001 /* trace read/write registers */
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#define DBG_IPL 0x0002 /* trace Interrupt */
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#define DBG_MAP 0x0004 /* trace Map register changes */
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DEBTAB qba_debug[] = {
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{"REG", DBG_REG},
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{"IPL", DBG_IPL},
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{"MAP", DBG_MAP},
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{0}
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};
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DEVICE qba_dev = {
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"QBA", &qba_unit, qba_reg, qba_mod,
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1, 16, QBMAWIDTH, 2, 16, 16,
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&qba_ex, &qba_dep, &qba_reset,
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NULL, NULL, NULL,
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&qba_dib, DEV_QBUS | DEV_DEBUG, 0, qba_debug, NULL, NULL, &qba_help, NULL, NULL,
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&qba_description
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};
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/* IO page dispatches */
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t_stat (*iodispR[IOPAGESIZE >> 1])(int32 *dat, int32 ad, int32 md);
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t_stat (*iodispW[IOPAGESIZE >> 1])(int32 dat, int32 ad, int32 md);
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DIB *iodibp[IOPAGESIZE >> 1];
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/* Interrupt request to interrupt action map */
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int32 (*int_ack[IPL_HLVL][32])(void); /* int ack routines */
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/* Interrupt request to vector map */
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int32 int_vec[IPL_HLVL][32]; /* int req to vector */
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/* The KA620/KA630 handles errors in I/O space as follows
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- read: machine check
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- write: machine check (?)
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*/
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int32 ReadQb (uint32 pa)
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{
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int32 idx, val;
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idx = (pa & IOPAGEMASK) >> 1;
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if (iodispR[idx]) {
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iodispR[idx] (&val, pa, READ);
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return val;
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}
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MACH_CHECK (MCHK_READ);
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return 0;
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}
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void WriteQb (uint32 pa, int32 val, int32 mode)
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{
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int32 idx;
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idx = (pa & IOPAGEMASK) >> 1;
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if (iodispW[idx]) {
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iodispW[idx] (val, pa, mode);
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return;
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}
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MACH_CHECK (MCHK_WRITE);
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return;
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}
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/* ReadIO - read I/O space - aligned access
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Inputs:
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pa = physical address
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lnt = length (BWLQ)
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Output:
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longword of data
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*/
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int32 ReadIO (uint32 pa, int32 lnt)
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{
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int32 iod;
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iod = ReadQb (pa); /* wd from Qbus */
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if (lnt < L_LONG) /* bw? position */
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iod = iod << ((pa & 2)? 16: 0);
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else iod = (ReadQb (pa + 2) << 16) | iod; /* lw, get 2nd wd */
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SET_IRQL;
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return iod;
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}
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/* ReadIOU - read I/O space - unaligned access
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Inputs:
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pa = physical address
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lnt = length (1, 2, 3 bytes)
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Output:
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data, not shifted
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Note that all of these cases are presented to the existing aligned IO routine:
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bo = 0, byte, word, or longword length
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bo = 2, word
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bo = 1, 2, 3, byte length
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All the other cases are end up at ReadIOU and WriteIOU, and they must turn
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the request into the exactly correct number of Qbus accesses AND NO MORE,
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because Qbus reads can have side-effects, and word read-modify-write is NOT
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the same as a byte write.
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Note that the sum of the pa offset and the length cannot be greater than 4.
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The read cases are:
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bo = 0, byte or word - read one word
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bo = 0, tribyte - read two words
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bo = 1, byte - read one word
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bo = 1, word or tribyte - read two words
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bo = 2, byte or word - read one word
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bo = 3, byte - read one word
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*/
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int32 ReadIOU (uint32 pa, int32 lnt)
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{
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int32 iod;
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iod = ReadQb (pa); /* wd from Qbus */
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if ((lnt + (pa & 1)) <= 2) /* byte or (word & even) */
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iod = iod << ((pa & 2)? 16: 0); /* one op */
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else iod = (ReadQb (pa + 2) << 16) | iod; /* two ops, get 2nd wd */
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SET_IRQL;
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return iod;
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}
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/* WriteIO - write I/O space - aligned access
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Inputs:
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pa = physical address
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val = data to write, right justified in 32b longword
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lnt = length (BWLQ)
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Outputs:
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none
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*/
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void WriteIO (uint32 pa, int32 val, int32 lnt)
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{
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if (lnt == L_BYTE)
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WriteQb (pa, val, WRITEB);
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else if (lnt == L_WORD)
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WriteQb (pa, val, WRITE);
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else {
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WriteQb (pa, val & 0xFFFF, WRITE);
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WriteQb (pa + 2, (val >> 16) & 0xFFFF, WRITE);
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}
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SET_IRQL;
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return;
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}
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/* WriteIOU - write I/O space
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Inputs:
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pa = physical address
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val = data to write, right justified in 32b longword
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lnt = length (1, 2, or 3 bytes)
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Outputs:
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none
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The write cases are:
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bo = x, lnt = byte - write one byte
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bo = 0 or 2, lnt = word - write one word
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bo = 1, lnt = word - write two bytes
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bo = 0, lnt = tribyte - write word, byte
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bo = 1, lnt = tribyte - write byte, word
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*/
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void WriteIOU (uint32 pa, int32 val, int32 lnt)
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{
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switch (lnt) {
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case L_BYTE: /* byte */
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WriteQb (pa, val & BMASK, WRITEB);
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break;
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case L_WORD: /* word */
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if (pa & 1) { /* odd addr? */
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WriteQb (pa, val & BMASK, WRITEB);
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WriteQb (pa + 1, (val >> 8) & BMASK, WRITEB);
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}
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else WriteQb (pa, val & WMASK, WRITE);
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break;
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case 3: /* tribyte */
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if (pa & 1) { /* odd addr? */
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WriteQb (pa, val & BMASK, WRITEB); /* byte then word */
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WriteQb (pa + 1, (val >> 8) & WMASK, WRITE);
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}
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else { /* even */
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WriteQb (pa, val & WMASK, WRITE); /* word then byte */
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WriteQb (pa + 2, (val >> 16) & BMASK, WRITEB);
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}
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break;
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}
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SET_IRQL;
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return;
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}
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/* Find highest priority outstanding interrupt */
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int32 eval_int (void)
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{
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int32 ipl = PSL_GETIPL (PSL);
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int32 i, t;
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static const int32 sw_int_mask[IPL_SMAX] = {
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0xFFFE, 0xFFFC, 0xFFF8, 0xFFF0, /* 0 - 3 */
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0xFFE0, 0xFFC0, 0xFF80, 0xFF00, /* 4 - 7 */
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0xFE00, 0xFC00, 0xF800, 0xF000, /* 8 - B */
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0xE000, 0xC000, 0x8000 /* C - E */
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};
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if (hlt_pin) /* hlt pin int */
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return IPL_HLTPIN;
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for (i = IPL_HMAX; i >= IPL_HMIN; i--) { /* chk hwre int */
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if (i <= ipl) /* at ipl? no int */
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return 0;
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if (int_req[i - IPL_HMIN]) /* req != 0? int */
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return i;
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}
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if (ipl >= IPL_SMAX) /* ipl >= sw max? */
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return 0;
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if ((t = SISR & sw_int_mask[ipl]) == 0) /* eligible req */
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return 0;
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for (i = IPL_SMAX; i > ipl; i--) { /* check swre int */
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if ((t >> i) & 1) /* req != 0? int */
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return i;
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}
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return 0;
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}
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/* Return vector for highest priority hardware interrupt at IPL lvl */
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int32 get_vector (int32 lvl)
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{
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int32 i;
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int32 l = lvl - IPL_HMIN;
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if (lvl > IPL_HMAX) { /* error req lvl? */
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ABORT (STOP_UIPL); /* unknown intr */
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}
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for (i = 0; int_req[l] && (i < 32); i++) {
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if ((int_req[l] >> i) & 1) {
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int32 vec;
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int_req[l] = int_req[l] & ~(1u << i);
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if (int_ack[l][i])
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vec =int_ack[l][i]();
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else
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vec = int_vec[l][i];
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vec |= int_vec_set[l][i];
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vec &= (int_vec_set[l][i] | QB_VEC_MASK);
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return vec;
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}
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}
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return 0;
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}
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/* I/O page routines */
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t_stat dbl_rd (int32 *data, int32 addr, int32 access)
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{
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*data = qb_ipc & QBIPC_MASK;
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sim_debug(DBG_REG, &qba_dev, "dbl_rd(addr=0x%08X, data=0x%X) ", addr, *data);
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sim_debug_bits(DBG_REG, &qba_dev, qb_ipc_bits, (uint32)*data, (uint32)*data, TRUE);
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return SCPE_OK;
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}
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t_stat dbl_wr (int32 data, int32 addr, int32 access)
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{
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int32 sc = (addr & 3) << 3;
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int32 nval = data << sc;
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int32 old_val = qb_ipc;
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qb_ipc = nval & QBIPC_RW;
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if ((addr & 3) == 0) /* low byte only */
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qb_ipc = ((qb_ipc & ~QBIPC_RW) | (data & QBIPC_RW)) & QBIPC_MASK;
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qb_ipc = qb_ipc & ~QBIPC_AHLT; /* Read only on arbiter */
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if (!(qb_ipc & QBIPC_DBIE))
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qb_ipc = qb_ipc & ~QBIPC_DB; /* Read only when not DBIE */
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sim_debug(DBG_REG, &qba_dev, "qba_wr(addr=0x%08X, data=0x%X) ", addr, data);
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sim_debug_bits(DBG_REG, &qba_dev, qb_ipc_bits, (uint32)old_val, (uint32)qb_ipc, TRUE);
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return SCPE_OK;
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}
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/* Qbus map read and write
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Read error: machine check?
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Write error: machine check?
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*/
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int32 qbmap_rd (int32 pa)
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{
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int32 idx = ((pa - QBMAPBASE) >> 2);
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return qb_map[idx] & QBMAP_RD;
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}
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void qbmap_wr (int32 pa, int32 val, int32 lnt)
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{
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int32 idx = ((pa - QBMAPBASE) >> 2);
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if (idx < QBNMAPR) {
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if (lnt < L_LONG) {
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int32 sc = (pa & 3) << 3;
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int32 mask = (lnt == L_WORD)? 0xFFFF: 0xFF;
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int32 t = qb_map[idx];
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val = ((val & mask) << sc) | (t & ~(mask << sc));
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}
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qb_map[idx] = val & QBMAP_WR;
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}
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else
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ka_mser |= MSER_NXM;
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return;
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}
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/* Qbus memory read and write (reflects to main memory)
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May give master or slave error, depending on where the failure occurs
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*/
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int32 qbmem_rd (int32 pa)
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{
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int32 qa = pa & QBMAMASK; /* Qbus addr */
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uint32 ma;
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#if !defined(VAX_620)
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if (sys_model == 1) { /* VAXstation II? */
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if ((pa >= QVMBASE) && (pa < QVMBASE+QVMSIZE))
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return vc_mem_rd (pa); /* read QVSS */
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}
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else if (sys_model == 2) { /* VAXstation II/GPX? */
|
|
if ((pa >= QDMBASE) && (pa < QDMBASE+QDMSIZE))
|
|
return va_mem_rd (pa); /* read QDSS */
|
|
}
|
|
#endif
|
|
if (qba_map_addr (qa, &ma)) { /* map addr */
|
|
return ReadW (ma);
|
|
}
|
|
MACH_CHECK (MCHK_READ); /* err? mcheck */
|
|
return 0;
|
|
}
|
|
|
|
void qbmem_wr (int32 pa, int32 val, int32 lnt)
|
|
{
|
|
int32 qa = pa & QBMAMASK; /* Qbus addr */
|
|
uint32 ma;
|
|
|
|
#if !defined(VAX_620)
|
|
if (sys_model == 1) { /* VAXstation II? */
|
|
if ((pa >= QVMBASE) && (pa < QVMBASE+QVMSIZE))
|
|
vc_mem_wr (pa, val, lnt); /* write QVSS */
|
|
return;
|
|
}
|
|
else if (sys_model == 2) { /* VAXstation II/GPX? */
|
|
if ((pa >= QDMBASE) && (pa < QDMBASE+QDMSIZE))
|
|
va_mem_wr (pa, val, lnt); /* write QDSS */
|
|
return;
|
|
}
|
|
#endif
|
|
if (qba_map_addr (qa, &ma)) { /* map addr */
|
|
if (lnt < L_LONG) {
|
|
int32 sc = (pa & 3) << 3;
|
|
int32 mask = (lnt == L_WORD)? 0xFFFF: 0xFF;
|
|
int32 t = M[ma >> 2];
|
|
val = ((val & mask) << sc) | (t & ~(mask << sc));
|
|
}
|
|
WriteW (ma, val);
|
|
}
|
|
else mem_err = 1;
|
|
return;
|
|
}
|
|
|
|
/* Map an address via the translation map */
|
|
|
|
t_bool qba_map_addr (uint32 qa, uint32 *ma)
|
|
{
|
|
int32 qblk = (qa >> VA_V_VPN); /* Qbus blk */
|
|
|
|
if (qblk < QBNMAPR) {
|
|
int32 qmap = qb_map[qblk];
|
|
if (qmap & QBMAP_VLD) { /* valid? */
|
|
*ma = ((qmap & QBMAP_PAG) << VA_V_VPN) + VA_GETOFF (qa);
|
|
if (ADDR_IS_MEM (*ma)) /* legit addr */
|
|
return TRUE;
|
|
ka_mser |= MSER_NXM;
|
|
return FALSE;
|
|
}
|
|
ka_mser |= MSER_NXM;
|
|
return FALSE;
|
|
}
|
|
ka_mser |= MSER_NXM;
|
|
return FALSE;
|
|
}
|
|
|
|
/* Map an address via the translation map - console version (no status changes) */
|
|
|
|
t_bool qba_map_addr_c (uint32 qa, uint32 *ma)
|
|
{
|
|
int32 qblk = (qa >> VA_V_VPN); /* Qbus blk */
|
|
|
|
if (qblk < QBNMAPR) {
|
|
int32 qmap = qb_map[qblk];
|
|
if (qmap & QBMAP_VLD) { /* valid? */
|
|
*ma = ((qmap & QBMAP_PAG) << VA_V_VPN) + VA_GETOFF (qa);
|
|
return TRUE;
|
|
}
|
|
}
|
|
return FALSE;
|
|
}
|
|
|
|
/* Reset I/O bus */
|
|
|
|
void ioreset_wr (int32 data)
|
|
{
|
|
reset_all (5); /* from qba on... */
|
|
return;
|
|
}
|
|
|
|
/* Reset Qbus */
|
|
|
|
t_stat qba_reset (DEVICE *dptr)
|
|
{
|
|
int32 i;
|
|
|
|
for (i = 0; i < IPL_HLVL; i++)
|
|
int_req[i] = 0;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Qbus I/O buffer routines, aligned access
|
|
|
|
Map_ReadB - fetch byte buffer from memory
|
|
Map_ReadW - fetch word buffer from memory
|
|
Map_WriteB - store byte buffer into memory
|
|
Map_WriteW - store word buffer into memory
|
|
*/
|
|
|
|
int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf)
|
|
{
|
|
int32 i;
|
|
uint32 ma, dat;
|
|
|
|
if ((ba | bc) & 03) { /* check alignment */
|
|
for (i = ma = 0; i < bc; i++, buf++) { /* by bytes */
|
|
if ((ma & VA_M_OFF) == 0) { /* need map? */
|
|
if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */
|
|
return (bc - i);
|
|
}
|
|
*buf = (uint8)ReadB (ma);
|
|
ma = ma + 1;
|
|
}
|
|
}
|
|
else {
|
|
for (i = ma = 0; i < bc; i = i + 4, buf++) { /* by longwords */
|
|
if ((ma & VA_M_OFF) == 0) { /* need map? */
|
|
if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */
|
|
return (bc - i);
|
|
}
|
|
dat = ReadL (ma); /* get lw */
|
|
*buf++ = dat & BMASK; /* low 8b */
|
|
*buf++ = (dat >> 8) & BMASK; /* next 8b */
|
|
*buf++ = (dat >> 16) & BMASK; /* next 8b */
|
|
*buf = (dat >> 24) & BMASK;
|
|
ma = ma + 4;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf)
|
|
{
|
|
int32 i;
|
|
uint32 ma,dat;
|
|
|
|
ba = ba & ~01;
|
|
bc = bc & ~01;
|
|
if ((ba | bc) & 03) { /* check alignment */
|
|
for (i = ma = 0; i < bc; i = i + 2, buf++) { /* by words */
|
|
if ((ma & VA_M_OFF) == 0) { /* need map? */
|
|
if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */
|
|
return (bc - i);
|
|
}
|
|
*buf = (uint16)ReadW (ma);
|
|
ma = ma + 2;
|
|
}
|
|
}
|
|
else {
|
|
for (i = ma = 0; i < bc; i = i + 4, buf++) { /* by longwords */
|
|
if ((ma & VA_M_OFF) == 0) { /* need map? */
|
|
if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */
|
|
return (bc - i);
|
|
}
|
|
dat = ReadL (ma); /* get lw */
|
|
*buf++ = dat & WMASK; /* low 16b */
|
|
*buf = (dat >> 16) & WMASK; /* high 16b */
|
|
ma = ma + 4;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int32 Map_WriteB (uint32 ba, int32 bc, const uint8 *buf)
|
|
{
|
|
int32 i;
|
|
uint32 ma, dat;
|
|
|
|
if ((ba | bc) & 03) { /* check alignment */
|
|
for (i = ma = 0; i < bc; i++, buf++) { /* by bytes */
|
|
if ((ma & VA_M_OFF) == 0) { /* need map? */
|
|
if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */
|
|
return (bc - i);
|
|
}
|
|
WriteB (ma, *buf);
|
|
ma = ma + 1;
|
|
}
|
|
}
|
|
else {
|
|
for (i = ma = 0; i < bc; i = i + 4, buf++) { /* by longwords */
|
|
if ((ma & VA_M_OFF) == 0) { /* need map? */
|
|
if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */
|
|
return (bc - i);
|
|
}
|
|
dat = (uint32) *buf++; /* get low 8b */
|
|
dat = dat | (((uint32) *buf++) << 8); /* merge next 8b */
|
|
dat = dat | (((uint32) *buf++) << 16); /* merge next 8b */
|
|
dat = dat | (((uint32) *buf) << 24); /* merge hi 8b */
|
|
WriteL (ma, dat); /* store lw */
|
|
ma = ma + 4;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int32 Map_WriteW (uint32 ba, int32 bc, const uint16 *buf)
|
|
{
|
|
int32 i;
|
|
uint32 ma, dat;
|
|
|
|
ba = ba & ~01;
|
|
bc = bc & ~01;
|
|
if ((ba | bc) & 03) { /* check alignment */
|
|
for (i = ma = 0; i < bc; i = i + 2, buf++) { /* by words */
|
|
if ((ma & VA_M_OFF) == 0) { /* need map? */
|
|
if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */
|
|
return (bc - i);
|
|
}
|
|
WriteW (ma, *buf);
|
|
ma = ma + 2;
|
|
}
|
|
}
|
|
else {
|
|
for (i = ma = 0; i < bc; i = i + 4, buf++) { /* by longwords */
|
|
if ((ma & VA_M_OFF) == 0) { /* need map? */
|
|
if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */
|
|
return (bc - i);
|
|
}
|
|
dat = (uint32) *buf++; /* get low 16b */
|
|
dat = dat | (((uint32) *buf) << 16); /* merge hi 16b */
|
|
WriteL (ma, dat); /* store lw */
|
|
ma = ma + 4;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* Memory examine via map (word only) */
|
|
|
|
t_stat qba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw)
|
|
{
|
|
uint32 qa = (uint32) exta, pa;
|
|
|
|
if ((vptr == NULL) || (qa >= QBMSIZE))
|
|
return SCPE_ARG;
|
|
if (qba_map_addr_c (qa, &pa) && ADDR_IS_MEM (pa)) {
|
|
*vptr = (uint32) ReadW (pa);
|
|
return SCPE_OK;
|
|
}
|
|
return SCPE_NXM;
|
|
}
|
|
|
|
/* Memory deposit via map (word only) */
|
|
|
|
t_stat qba_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw)
|
|
{
|
|
uint32 qa = (uint32) exta, pa;
|
|
|
|
if (qa >= QBMSIZE)
|
|
return SCPE_ARG;
|
|
if (qba_map_addr_c (qa, &pa) && ADDR_IS_MEM (pa)) {
|
|
WriteW (pa, (int32) val);
|
|
return SCPE_OK;
|
|
}
|
|
return SCPE_NXM;
|
|
}
|
|
|
|
/* Build dib_tab from device list */
|
|
|
|
t_stat build_dib_tab (void)
|
|
{
|
|
int32 i;
|
|
DEVICE *dptr;
|
|
DIB *dibp;
|
|
t_stat r;
|
|
|
|
init_ubus_tab (); /* init bus tables */
|
|
for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */
|
|
dibp = (DIB *) dptr->ctxt; /* get DIB */
|
|
if (dibp && !(dptr->flags & DEV_DIS)) { /* defined, enabled? */
|
|
r = build_ubus_tab (dptr, dibp); /* add to bus tab */
|
|
if (r)
|
|
return r;
|
|
} /* end if enabled */
|
|
} /* end for */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Show QBA virtual address */
|
|
|
|
t_stat qba_show_virt (FILE *of, UNIT *uptr, int32 val, CONST void *desc)
|
|
{
|
|
t_stat r;
|
|
const char *cptr = (const char *) desc;
|
|
uint32 qa, pa;
|
|
|
|
if (cptr) {
|
|
qa = (uint32) get_uint (cptr, 16, QBMSIZE - 1, &r);
|
|
if (r == SCPE_OK) {
|
|
if (qba_map_addr_c (qa, &pa))
|
|
fprintf (of, "Qbus %-X = physical %-X\n", qa, pa);
|
|
else fprintf (of, "Qbus %-X: invalid mapping\n", qa);
|
|
return SCPE_OK;
|
|
}
|
|
}
|
|
fprintf (of, "Invalid argument\n");
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat qba_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
|
|
{
|
|
fprintf (st, "Qbus Adapter (QBA)\n\n");
|
|
fprintf (st, "The Qbus adapter (QBA) simulates the CQBIC Qbus adapter chip.\n");
|
|
fprint_set_help (st, dptr);
|
|
fprint_show_help (st, dptr);
|
|
fprintf (st, "\nThe QBA implements main memory examination and modification via the Qbus\n");
|
|
fprintf (st, "map. The data width is always 16b:\n\n");
|
|
fprintf (st, "EXAMINE QBA 0/10 examine main memory words corresponding\n");
|
|
fprintf (st, " to Qbus addresses 0-10\n");
|
|
fprint_reg_help (st, dptr);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
const char *qba_description (DEVICE *dptr)
|
|
{
|
|
return "Qbus adapter";
|
|
}
|