121 lines
4 KiB
C
121 lines
4 KiB
C
/* pdp8_clk.c: PDP-8 real-time clock simulator
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Copyright (c) 1993-2001, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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clk real time clock
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05-Mar-01 RMS Added clock calibration support
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Note: includes the IOT's for both the PDP-8/E and PDP-8/A clocks
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*/
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#include "pdp8_defs.h"
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extern int32 int_req, int_enable, dev_done, stop_inst;
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t_stat clk_svc (UNIT *uptr);
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t_stat clk_reset (DEVICE *dptr);
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extern int32 sim_rtc_calb (int32 tps);
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int32 clk_tps = 60;
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/* CLK data structures
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clk_dev CLK device descriptor
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clk_unit CLK unit descriptor
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clk_reg CLK register list
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*/
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UNIT clk_unit = { UDATA (&clk_svc, 0, 0), 16000 };
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REG clk_reg[] = {
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{ FLDATA (DONE, dev_done, INT_V_CLK) },
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{ FLDATA (ENABLE, int_enable, INT_V_CLK) },
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{ FLDATA (INT, int_req, INT_V_CLK) },
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{ DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },
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{ DRDATA (TPS, clk_tps, 8), REG_NZ + PV_LEFT },
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{ NULL } };
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DEVICE clk_dev = {
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"CLK", &clk_unit, clk_reg, NULL,
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1, 0, 0, 0, 0, 0,
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NULL, NULL, &clk_reset,
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NULL, NULL, NULL };
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/* IOT routine
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IOT's 6131-6133 are the PDP-8/E clock
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IOT's 6135-6137 the PDP-8/A clock
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*/
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int32 clk (int32 pulse, int32 AC)
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{
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switch (pulse) { /* decode IR<9:11> */
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case 1: /* CLEI */
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int_enable = int_enable | INT_CLK; /* enable clk ints */
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int_req = INT_UPDATE; /* update interrupts */
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return AC;
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case 2: /* CLDI */
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int_enable = int_enable & ~INT_CLK; /* disable clk ints */
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int_req = int_req & ~INT_CLK; /* update interrupts */
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return AC;
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case 3: /* CLSC */
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if (dev_done & INT_CLK) { /* flag set? */
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dev_done = dev_done & ~INT_CLK; /* clear flag */
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int_req = int_req & ~INT_CLK; /* clear int req */
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return IOT_SKP + AC; }
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return AC;
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case 5: /* CLLE */
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if (AC & 1) int_enable = int_enable | INT_CLK; /* test AC<11> */
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else int_enable = int_enable & ~INT_CLK;
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int_req = INT_UPDATE; /* update interrupts */
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return AC;
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case 6: /* CLCL */
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dev_done = dev_done & ~INT_CLK; /* clear flag */
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int_req = int_req & ~INT_CLK; /* clear int req */
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return AC;
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case 7: /* CLSK */
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return (dev_done & INT_CLK)? IOT_SKP + AC: AC;
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default:
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return (stop_inst << IOT_V_REASON) + AC; } /* end switch */
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}
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/* Unit service */
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t_stat clk_svc (UNIT *uptr)
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{
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dev_done = dev_done | INT_CLK; /* set done */
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int_req = INT_UPDATE; /* update interrupts */
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sim_activate (&clk_unit, sim_rtc_calb (clk_tps)); /* reactivate unit */
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat clk_reset (DEVICE *dptr)
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{
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dev_done = dev_done & ~INT_CLK; /* clear done, int */
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int_req = int_req & ~INT_CLK;
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int_enable = int_enable & ~INT_CLK; /* clear enable */
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sim_activate (&clk_unit, clk_unit.wait); /* activate unit */
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return SCPE_OK;
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}
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