439 lines
16 KiB
C
439 lines
16 KiB
C
/* pdp8_rx.c: RX8E/RX01 floppy disk simulator
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Copyright (c) 1993-2001, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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rx RX8E/RX01 floppy disk
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26-Apr-01 RMS Added device enable/disable support
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13-Apr-01 RMS Revised for register arrays
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14-Apr-99 RMS Changed t_addr to unsigned
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15-Aug-96 RMS Fixed bug in LCD
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An RX01 diskette consists of 77 tracks, each with 26 sectors of 128B.
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Tracks are numbered 0-76, sectors 1-26. The RX8E can store data in
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8b mode or 12b mode. In 8b mode, the controller reads or writes
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128 bytes per sector. In 12b mode, the reads or writes 64 12b words
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per sector. The 12b words are bit packed into the first 96 bytes
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of the sector; the last 32 bytes are zeroed on writes.
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*/
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#include "pdp8_defs.h"
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#define RX_NUMTR 77 /* tracks/disk */
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#define RX_M_TRACK 0377
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#define RX_NUMSC 26 /* sectors/track */
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#define RX_M_SECTOR 0177 /* cf Jones!! */
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#define RX_NUMBY 128 /* bytes/sector */
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#define RX_NUMWD (RX_NUMBY / 2) /* words/sector */
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#define RX_SIZE (RX_NUMTR * RX_NUMSC * RX_NUMBY) /* bytes/disk */
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#define RX_NUMDR 2 /* drives/controller */
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#define RX_M_NUMDR 01
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#define UNIT_V_WLK (UNIT_V_UF) /* write locked */
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#define UNIT_WLK (1 << UNIT_V_UF)
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#define IDLE 0 /* idle state */
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#define RWDS 1 /* rw, sect next */
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#define RWDT 2 /* rw, track next */
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#define FILL 3 /* fill buffer */
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#define EMPTY 4 /* empty buffer */
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#define CMD_COMPLETE 5 /* set done next */
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#define INIT_COMPLETE 6 /* init compl next */
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#define RXCS_V_FUNC 1 /* function */
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#define RXCS_M_FUNC 7
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#define RXCS_FILL 0 /* fill buffer */
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#define RXCS_EMPTY 1 /* empty buffer */
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#define RXCS_WRITE 2 /* write sector */
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#define RXCS_READ 3 /* read sector */
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#define RXCS_RXES 5 /* read status */
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#define RXCS_WRDEL 6 /* write del data */
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#define RXCS_ECODE 7 /* read error code */
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#define RXCS_DRV 0020 /* drive */
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#define RXCS_MODE 0100 /* mode */
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#define RXCS_MAINT 0200 /* maintenance */
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#define RXES_CRC 0001 /* CRC error */
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#define RXES_PAR 0002 /* parity error */
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#define RXES_ID 0004 /* init done */
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#define RXES_WLK 0010 /* write protect */
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#define RXES_DD 0100 /* deleted data */
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#define RXES_DRDY 0200 /* drive ready */
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#define TRACK u3 /* current track */
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#define READ_RXDBR ((rx_csr & RXCS_MODE)? AC | (rx_dbr & 0377): rx_dbr)
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#define CALC_DA(t,s) (((t) * RX_NUMSC) + ((s) - 1)) * RX_NUMBY
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extern int32 int_req, int_enable, dev_done, dev_enb;
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int32 rx_tr = 0; /* xfer ready flag */
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int32 rx_err = 0; /* error flag */
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int32 rx_csr = 0; /* control/status */
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int32 rx_dbr = 0; /* data buffer */
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int32 rx_esr = 0; /* error status */
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int32 rx_ecode = 0; /* error code */
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int32 rx_track = 0; /* desired track */
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int32 rx_sector = 0; /* desired sector */
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int32 rx_state = IDLE; /* controller state */
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int32 rx_cwait = 100; /* command time */
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int32 rx_swait = 10; /* seek, per track */
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int32 rx_xwait = 1; /* tr set time */
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int32 rx_stopioe = 1; /* stop on error */
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uint8 rx_buf[RX_NUMBY] = { 0 }; /* sector buffer */
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int32 bufptr = 0; /* buffer pointer */
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t_stat rx_svc (UNIT *uptr);
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t_stat rx_reset (DEVICE *dptr);
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t_stat rx_boot (int32 unitno);
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/* RX8E data structures
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rx_dev RX device descriptor
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rx_unit RX unit list
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rx_reg RX register list
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rx_mod RX modifier list
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*/
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UNIT rx_unit[] = {
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{ UDATA (&rx_svc,
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UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, RX_SIZE) },
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{ UDATA (&rx_svc,
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UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, RX_SIZE) } };
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REG rx_reg[] = {
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{ ORDATA (RXCS, rx_csr, 12) },
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{ ORDATA (RXDB, rx_dbr, 12) },
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{ ORDATA (RXES, rx_esr, 8) },
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{ ORDATA (RXERR, rx_ecode, 8) },
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{ ORDATA (RXTA, rx_track, 8) },
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{ ORDATA (RXSA, rx_sector, 8) },
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{ ORDATA (STAPTR, rx_state, 3), REG_RO },
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{ ORDATA (BUFPTR, bufptr, 7) },
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{ FLDATA (TR, rx_tr, 0) },
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{ FLDATA (ERR, rx_err, 0) },
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{ FLDATA (DONE, dev_done, INT_V_RX) },
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{ FLDATA (ENABLE, int_enable, INT_V_RX) },
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{ FLDATA (INT, int_req, INT_V_RX) },
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{ DRDATA (CTIME, rx_cwait, 24), PV_LEFT },
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{ DRDATA (STIME, rx_swait, 24), PV_LEFT },
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{ DRDATA (XTIME, rx_xwait, 24), PV_LEFT },
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{ FLDATA (FLG0, rx_unit[0].flags, UNIT_V_WLK), REG_HRO },
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{ FLDATA (FLG1, rx_unit[1].flags, UNIT_V_WLK), REG_HRO },
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{ FLDATA (STOP_IOE, rx_stopioe, 0) },
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{ BRDATA (SBUF, rx_buf, 8, 8, RX_NUMBY) },
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{ FLDATA (*DEVENB, dev_enb, INT_V_RX), REG_HRO },
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{ NULL } };
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MTAB rx_mod[] = {
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{ UNIT_WLK, 0, "write enabled", "ENABLED", NULL },
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{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
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{ 0 } };
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DEVICE rx_dev = {
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"RX", rx_unit, rx_reg, rx_mod,
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RX_NUMDR, 8, 20, 1, 8, 8,
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NULL, NULL, &rx_reset,
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&rx_boot, NULL, NULL };
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/* IOT routine */
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int32 rx (int32 pulse, int32 AC)
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{
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int32 drv;
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switch (pulse) { /* decode IR<9:11> */
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case 0: /* unused */
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return AC;
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case 1: /* LCD */
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if (rx_state != IDLE) return AC; /* ignore if busy */
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rx_dbr = rx_csr = AC; /* save new command */
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dev_done = dev_done & ~INT_RX; /* clear done, int */
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int_req = int_req & ~INT_RX;
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rx_tr = rx_err = 0; /* clear flags */
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bufptr = 0; /* clear buf pointer */
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switch ((AC >> RXCS_V_FUNC) & RXCS_M_FUNC) { /* decode command */
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case RXCS_FILL:
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rx_state = FILL; /* state = fill */
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rx_tr = 1; /* xfer is ready */
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break;
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case RXCS_EMPTY:
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rx_state = EMPTY; /* state = empty */
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sim_activate (&rx_unit[0], rx_xwait); /* sched xfer */
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break;
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case RXCS_READ: case RXCS_WRITE: case RXCS_WRDEL:
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rx_state = RWDS; /* state = get sector */
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rx_tr = 1; /* xfer is ready */
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rx_esr = rx_esr & RXES_ID; /* clear errors */
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break;
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default:
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rx_state = CMD_COMPLETE; /* state = cmd compl */
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drv = (rx_csr & RXCS_DRV) > 0; /* get drive number */
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sim_activate (&rx_unit[drv], rx_cwait); /* sched done */
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break; } /* end switch func */
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return 0; /* clear AC */
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case 2: /* XDR */
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switch (rx_state & 07) { /* case on state */
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default: /* default */
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return READ_RXDBR; /* return data reg */
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case EMPTY: /* emptying buffer */
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sim_activate (&rx_unit[0], rx_xwait); /* sched xfer */
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return READ_RXDBR; /* return data reg */
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case RWDS: /* sector */
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rx_sector = AC & RX_M_SECTOR; /* save sector */
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case FILL: /* fill */
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rx_dbr = AC; /* save data */
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sim_activate (&rx_unit[0], rx_xwait); /* sched xfer */
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break;
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case RWDT: /* track */
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rx_track = AC & RX_M_TRACK; /* save track */
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rx_dbr = AC; /* save data */
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drv = (rx_csr & RXCS_DRV) > 0; /* get drive number */
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sim_activate (&rx_unit[drv], /* sched done */
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rx_swait * abs (rx_track - rx_unit[drv].TRACK));
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break; } /* end switch state */
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return AC;
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case 3: /* STR */
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if (rx_tr != 0) {
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rx_tr = 0;
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return IOT_SKP + AC; }
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return AC;
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case 4: /* SER */
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if (rx_err != 0) {
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rx_err = 0;
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return IOT_SKP + AC; }
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return AC;
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case 5: /* SDN */
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if ((dev_done & INT_RX) != 0) {
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dev_done = dev_done & ~INT_RX;
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int_req = int_req & ~INT_RX;
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return IOT_SKP + AC; }
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return AC;
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case 6: /* INTR */
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if (AC & 1) int_enable = int_enable | INT_RX;
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else int_enable = int_enable & ~INT_RX;
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int_req = INT_UPDATE;
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return AC;
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case 7: /* INIT */
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rx_reset (&rx_dev); /* reset device */
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return AC; } /* end case pulse */
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}
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/* Unit service; the action to be taken depends on the transfer state:
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IDLE Should never get here, treat as unknown command
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RWDS Just transferred sector, wait for track, set tr
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RWDT Just transferred track, do read or write, finish command
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FILL copy dbr to rx_buf[bufptr], advance ptr
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if bufptr > max, finish command, else set tr
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EMPTY if bufptr > max, finish command, else
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copy rx_buf[bufptr] to dbr, advance ptr, set tr
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CMD_COMPLETE copy requested data to dbr, finish command
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INIT_COMPLETE read drive 0, track 1, sector 1 to buffer, finish command
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For RWDT and CMD_COMPLETE, the input argument is the selected drive;
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otherwise, it is drive 0.
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*/
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t_stat rx_svc (UNIT *uptr)
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{
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int32 i, func, byptr;
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t_addr da;
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t_stat rval;
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void rx_done (int32 new_dbr, int32 new_ecode);
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#define PTR12(x) (((x) + (x) + (x)) >> 1)
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rval = SCPE_OK; /* assume ok */
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func = (rx_csr >> RXCS_V_FUNC) & RXCS_M_FUNC; /* get function */
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switch (rx_state) { /* case on state */
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case IDLE: /* idle */
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rx_done (rx_esr, 0); /* done */
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break;
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case EMPTY: /* empty buffer */
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if (rx_csr & RXCS_MODE) { /* 8b xfer? */
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if (bufptr >= RX_NUMBY) { /* done? */
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rx_done (rx_esr, 0); /* set done */
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break; } /* and exit */
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rx_dbr = rx_buf[bufptr]; } /* else get data */
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else { byptr = PTR12 (bufptr); /* 12b xfer */
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if (bufptr >= RX_NUMWD) { /* done? */
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rx_done (rx_esr, 0); /* set done */
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break; } /* and exit */
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rx_dbr = (bufptr & 1)? /* get data */
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((rx_buf[byptr] & 017) << 8) | rx_buf[byptr + 1]:
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(rx_buf[byptr] << 4) | ((rx_buf[byptr + 1] >> 4) & 017); }
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bufptr = bufptr + 1;
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rx_tr = 1;
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break;
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case FILL: /* fill buffer */
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if (rx_csr & RXCS_MODE) { /* 8b xfer? */
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rx_buf[bufptr] = rx_dbr; /* fill buffer */
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bufptr = bufptr + 1;
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if (bufptr < RX_NUMBY) rx_tr = 1; /* if more, set xfer */
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else rx_done (rx_esr, 0); } /* else done */
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else { byptr = PTR12 (bufptr); /* 12b xfer */
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if (bufptr & 1) { /* odd or even? */
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rx_buf[byptr] = (rx_buf[byptr] & 0360) | ((rx_dbr >> 8) & 017);
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rx_buf[byptr + 1] = rx_dbr & 0377; }
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else {
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rx_buf[byptr] = (rx_dbr >> 4) & 0377;
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rx_buf[byptr + 1] = (rx_dbr & 017) << 4; }
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bufptr = bufptr + 1;
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if (bufptr < RX_NUMWD) rx_tr = 1; /* if more, set xfer */
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else { for (i = PTR12 (RX_NUMWD); i < RX_NUMBY; i++)
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rx_buf[i] = 0; /* else fill sector */
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rx_done (rx_esr, 0); } } /* set done */
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break;
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case RWDS: /* wait for sector */
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rx_tr = 1; /* set xfer ready */
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rx_state = RWDT; /* advance state */
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break;
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case RWDT: /* wait for track */
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if (rx_track >= RX_NUMTR) { /* bad track? */
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rx_done (rx_esr, 0040); /* done, error */
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break; }
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uptr -> TRACK = rx_track; /* now on track */
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if ((rx_sector == 0) || (rx_sector > RX_NUMSC)) { /* bad sect? */
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rx_done (rx_esr, 0070); /* done, error */
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break; }
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if ((uptr -> flags & UNIT_BUF) == 0) { /* not buffered? */
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rx_done (rx_esr, 0110); /* done, error */
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rval = SCPE_UNATT; /* return error */
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break; }
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da = CALC_DA (rx_track, rx_sector); /* get disk address */
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if (func == RXCS_WRDEL) rx_esr = rx_esr | RXES_DD; /* del data? */
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if (func == RXCS_READ) { /* read? */
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for (i = 0; i < RX_NUMBY; i++)
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rx_buf[i] = *(((int8 *) uptr -> filebuf) + da + i); }
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else { if (uptr -> flags & UNIT_WLK) { /* write and locked? */
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rx_esr = rx_esr | RXES_WLK; /* flag error */
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rx_done (rx_esr, 0100); /* done, error */
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break; }
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for (i = 0; i < RX_NUMBY; i++) /* write */
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*(((int8 *) uptr -> filebuf) + da + i) = rx_buf[i];
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da = da + RX_NUMBY;
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if (da > uptr -> hwmark) uptr -> hwmark = da; }
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rx_done (rx_esr, 0); /* done */
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break;
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case CMD_COMPLETE: /* command complete */
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if (func == RXCS_ECODE) rx_done (rx_ecode, 0);
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else if (uptr -> flags & UNIT_ATT) rx_done (rx_esr | RXES_DRDY, 0);
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else rx_done (rx_esr, 0);
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break;
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case INIT_COMPLETE: /* init complete */
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rx_unit[0].TRACK = 1; /* drive 0 to trk 1 */
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rx_unit[1].TRACK = 0; /* drive 1 to trk 0 */
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if ((rx_unit[0].flags & UNIT_BUF) == 0) { /* not buffered? */
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rx_done (rx_esr | RXES_ID, 0010); /* init done, error */
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break; }
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da = CALC_DA (1, 1); /* track 1, sector 1 */
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for (i = 0; i < RX_NUMBY; i++) /* read sector */
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rx_buf[i] = *(((int8 *) uptr -> filebuf) + da + i);
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rx_done (rx_esr | RXES_ID | RXES_DRDY, 0); /* set done */
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if ((rx_unit[1].flags & UNIT_ATT) == 0) rx_ecode = 0020;
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break; } /* end case state */
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return IORETURN (rx_stopioe, rval);
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}
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/* Command complete. Set done and put final value in interface register,
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return to IDLE state.
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*/
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void rx_done (int32 new_dbr, int32 new_ecode)
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{
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dev_done = dev_done | INT_RX; /* set done */
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int_req = INT_UPDATE; /* update ints */
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rx_dbr = new_dbr; /* update buffer */
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if (new_ecode != 0) { /* test for error */
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rx_ecode = new_ecode;
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rx_err = 1; }
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rx_state = IDLE; /* now idle */
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return;
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}
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/* Reset routine. The RX is one of the few devices that schedules
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an I/O transfer as part of its initialization.
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*/
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t_stat rx_reset (DEVICE *dptr)
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{
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rx_esr = rx_ecode = 0; /* clear error */
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rx_tr = rx_err = 0; /* clear flags */
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dev_done = dev_done & ~INT_RX; /* clear done, int */
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int_req = int_req & ~INT_RX;
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int_enable = int_enable & ~INT_RX;
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rx_dbr = rx_csr = 0; /* 12b mode, drive 0 */
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sim_cancel (&rx_unit[1]); /* cancel drive 1 */
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if (rx_unit[0].flags & UNIT_BUF) { /* attached? */
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rx_state = INIT_COMPLETE; /* yes, sched init */
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sim_activate (&rx_unit[0], rx_swait * abs (1 - rx_unit[0].TRACK)); }
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else rx_done (rx_esr | RXES_ID, 0010); /* no, error */
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return SCPE_OK;
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}
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/* Bootstrap routine */
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#define BOOT_START 022
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#define BOOT_INST 060
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#define BOOT_LEN (sizeof (boot_rom) / sizeof (int))
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static const int32 boot_rom[] = {
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06755, /* 22, SDN */
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05022, /* 23, JMP .-1 */
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07126, /* 24, CLL CML RTL ; read command + */
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01060, /* 25, TAD UNIT ; unit no */
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06751, /* 26, LCD ; load read+unit */
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07201, /* 27, CLL IAC ; AC = 1 */
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04053, /* 30, JMS 053 ; load sector */
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04053, /* 31, JMS 053 ; load track */
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07104, /* 32, CLL RAL ; AC = 2 */
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06755, /* 33, SDN */
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05054, /* 34, JMP 54 */
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06754, /* 35, SER */
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07450, /* 36, SNA ; more to do? */
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07610, /* 37, CLA SKP ; error */
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05046, /* 40, JMP 46 ; go empty */
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07402, 07402, /* 41-45, HALT ; error */
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07402, 07402, 07402,
|
||
06751, /* 46, LCD ; load empty */
|
||
04053, /* 47, JMS 53 ; get data */
|
||
03002, /* 50, DCA 2 ; store */
|
||
02050, /* 51, ISZ 50 ; incr store */
|
||
05047, /* 52, JMP 47 ; loop until done */
|
||
00000, /* 53, 0 */
|
||
06753, /* 54, STR */
|
||
05033, /* 55, JMP 33 */
|
||
06752, /* 56, XDR */
|
||
05453, /* 57, JMP I 53 */
|
||
07024, /* UNIT, CML RAL ; for unit 1 */
|
||
06030 /* 61, KCC */
|
||
};
|
||
|
||
t_stat rx_boot (int32 unitno)
|
||
{
|
||
int32 i;
|
||
extern int32 saved_PC;
|
||
extern uint16 M[];
|
||
|
||
for (i = 0; i < BOOT_LEN; i++) M[BOOT_START + i] = boot_rom[i];
|
||
M[BOOT_INST] = unitno? 07024: 07004;
|
||
saved_PC = BOOT_START;
|
||
return SCPE_OK;
|
||
}
|