WARNING: V2.10 has reorganized and renamed some of the definition files for the PDP-10, PDP-11, and VAX. Be sure to delete all previous source files before you unpack the Zip archive, or unpack it into a new directory structure. WARNING: V2.10 has a new, more comprehensive save file format. Restoring save files from previous releases will cause 'invalid register' errors and loss of CPU option flags, device enable/ disable flags, unit online/offline flags, and unit writelock flags. WARNING: If you are using Visual Studio .NET through the IDE, be sure to turn off the /Wp64 flag in the project settings, or dozens of spurious errors will be generated. WARNING: Compiling Ethernet support under Windows requires extra steps; see the Ethernet readme file. Ethernet support is currently available only for Windows, Linux, NetBSD, and OpenBSD. 1. New Features 1.1 SCP and Libraries - The VT emulation package has been replaced by the capability to remote the console to a Telnet session. Telnet clients typically have more complete and robust VT100 emulation. - Simulated devices may now have statically allocated buffers, in addition to dynamically allocated buffers or disk-based data stores. - The DO command now takes substitutable arguments (max 9). In command files, %n represents substitutable argument n. - The initial command line is now interpreted as the command name and substitutable arguments for a DO command. This is backward compatible to prior versions. - The initial command line parses switches. -Q is interpreted as quiet mode; informational messages are suppressed. - The HELP command now takes an optional argument. HELP <cmd> types help on the specified command. - Hooks have been added for implementing GUI-based consoles, as well as simulator-specific command extensions. A few internal data structures and definitions have changed. - Two new routines (tmxr_open_master, tmxr_close_master) have been added to sim_tmxr.c. The calling sequence for sim_accept_conn has been changed in sim_sock.c. - The calling sequence for the VM boot routine has been modified to add an additional parameter. - SAVE now saves, and GET now restores, controller and unit flags. - Library sim_ether.c has been added for Ethernet support. 1.2 VAX - Non-volatile RAM (NVR) can behave either like a memory or like a disk-based peripheral. If unattached, it behaves like memory and is saved and restored by SAVE and RESTORE, respectively. If attached, its contents are loaded from disk by ATTACH and written back to disk at DETACH and EXIT. - SHOW <device> VECTOR displays the device's interrupt vector. A few devices allow the vector to be changed with SET <device> VECTOR=nnn. - SHOW CPU IOSPACE displays the I/O space address map. - The TK50 (TMSCP tape) has been added. - The DEQNA/DELQA (Qbus Ethernet controllers) have been added. - Autoconfiguration support has been added. - The paper tape reader has been removed from vax_stddev.c and now references a common implementation file, dec_pt.h. - Examine and deposit switches now work on all devices, not just the CPU. - Device address conflicts are not detected until simulation starts. 1.3 PDP-11 - SHOW <device> VECTOR displays the device's interrupt vector. Most devices allow the vector to be changed with SET <device> VECTOR=nnn. - SHOW CPU IOSPACE displays the I/O space address map. - The TK50 (TMSCP tape), RK611/RK06/RK07 (cartridge disk), RX211 (double density floppy), and KW11P programmable clock have been added. - The DEQNA/DELQA (Qbus Ethernet controllers) have been added. - Autoconfiguration support has been added. - The paper tape reader has been removed from pdp11_stddev.c and now references a common implementation file, dec_pt.h. - Device bootstraps now use the actual CSR specified by the SET ADDRESS command, rather than just the default CSR. Note that PDP-11 operating systems may NOT support booting with non-standard addresses. - Specifying more than 256KB of memory, or changing the bus configuration, causes all peripherals that are not compatible with the current bus configuration to be disabled. - Device address conflicts are not detected until simulation starts. 1.4 PDP-10 - SHOW <device> VECTOR displays the device's interrupt vector. A few devices allow the vector to be changed with SET <device> VECTOR=nnn. - SHOW CPU IOSPACE displays the I/O space address map. - The RX211 (double density floppy) has been added; it is off by default. - The paper tape now references a common implementation file, dec_pt.h. - Device address conflicts are not detected until simulation starts. 1.5 PDP-1 - DECtape (then known as MicroTape) support has been added. - The line printer and DECtape can be disabled and enabled. 1.6 PDP-8 - The RX28 (double density floppy) has been added as an option to the existing RX8E controller. - SHOW <device> DEVNO displays the device's device number. Most devices allow the device number to be changed with SET <device> DEVNO=nnn. - Device number conflicts are not detected until simulation starts. 1.7 IBM 1620 - The IBM 1620 simulator has been released. 1.8 AltairZ80 - A hard drive has been added for increased storage. - Several bugs have been fixed. 1.9 HP 2100 - The 12845A has been added and made the default line printer (LPT). The 12653A has been renamed LPS and is off by default. It also supports the diagnostic functions needed to run the DCPC and DMS diagnostics. - The 12557A/13210A disk defaults to the 13210A (7900/7901). - The 12559A magtape is off by default. - New CPU options (EAU/NOEAU) enable/disable the extended arithmetic instructions for the 2116. These instructions are standard on the 2100 and 21MX. - New CPU options (MPR/NOMPR) enable/disable memory protect for the 2100 and 21MX. - New CPU options (DMS/NODMS) enable/disable the dynamic mapping instructions for the 21MX. - The 12539 timebase generator autocalibrates. 1.10 Simulated Magtapes - Simulated magtapes recognize end of file and the marker 0xFFFFFFFF as end of medium. Only the TMSCP tape simulator can generate an end of medium marker. - The error handling in simulated magtapes was overhauled to be consistent through all simulators. 1.11 Simulated DECtapes - Added support for RT11 image file format (256 x 16b) to DECtapes. 2. Release Notes 2.1 Bugs Fixed - TS11/TSV05 was not simulating the XS0_MOT bit, causing failures under VMS. In addition, two of the CTL options were coded interchanged. - IBM 1401 tape was not setting a word mark under group mark for load mode reads. This caused the diagnostics to crash. - SCP bugs in ssh_break and set_logon were fixed (found by Dave Hittner). - Numerous bugs in the HP 2100 extended arithmetic, floating point, 21MX, DMS, and IOP instructions were fixed. Bugs were also fixed in the memory protect and DMS functions. The moving head disks (DP, DQ) were revised to simulate the hardware more accurately. Missing functions in DQ (address skip, read address) were added. 2.2 HP 2100 Debugging - The HP 2100 CPU nows runs all of the CPU diagnostics. - The peripherals run most of the peripheral diagnostics. There is still a problem in overlapped seek operation on the disks. See the file hp2100_diag.txt for details. 3. In Progress These simulators are not finished and are available in a separate Zip archive distribution. - Interdata 16b/32b: coded, partially tested. See the file id_diag.txt for details. - SDS 940: coded, partially tested.
1042 lines
34 KiB
C
1042 lines
34 KiB
C
/* pdp11_ts.c: TS11/TSV05 magnetic tape simulator
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Copyright (c) 1993-2002, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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ts TS11/TSV05 magtape
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30-Sep-02 RMS Added variable address support to bootstrap
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Added vector change/display support
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Fixed CTL unload/clean decode
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Implemented XS0_MOT in extended status
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New data structures, revamped error recovery
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28-Aug-02 RMS Added end of medium support
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30-May-02 RMS Widened POS to 32b
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22-Apr-02 RMS Added maximum record length protection
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04-Apr-02 RMS Fixed bug in residual frame count after space operation
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16-Feb-02 RMS Fixed bug in message header logic
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26-Jan-02 RMS Revised bootstrap to conform to M9312
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06-Jan-02 RMS Revised enable/disable support
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30-Nov-01 RMS Added read only unit, extended SET/SHOW support
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09-Nov-01 RMS Added bus map, VAX support
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15-Oct-01 RMS Integrated debug logging across simulator
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27-Sep-01 RMS Implemented extended characteristics and status
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Fixed bug in write characteristics status return
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19-Sep-01 RMS Fixed bug in bootstrap
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15-Sep-01 RMS Fixed bug in NXM test
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07-Sep-01 RMS Revised device disable and interrupt mechanism
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13-Jul-01 RMS Fixed bug in space reverse (found by Peter Schorn)
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Magnetic tapes are represented as a series of variable 8b records
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of the form:
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32b record length in bytes - exact number
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byte 0
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byte 1
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:
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byte n-2
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byte n-1
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32b record length in bytes - exact number
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If the byte count is odd, the record is padded with an extra byte
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of junk. File marks are represented by a single record length of 0.
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End of tape is two consecutive end of file marks.
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The TS11 functions in three environments:
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- PDP-11 Q22 systems - the I/O map is one for one, so it's safe to
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go through the I/O map
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- PDP-11 Unibus 22b systems - the TS11 behaves as an 18b Unibus
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peripheral and must go through the I/O map
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- VAX Q22 systems - the TS11 must go through the I/O map
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*/
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#if defined (USE_INT64) /* VAX version */
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#include "vax_defs.h"
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#define VM_VAX 1
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#define TS_RDX 16
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#define TS_DIS 0 /* on by default */
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#define ADDRTEST 0177700
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#define DMASK 0xFFFF
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extern int32 ReadB (t_addr pa);
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extern void WriteB (t_addr pa, int32 val);
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extern int32 ReadW (t_addr pa);
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extern void WriteW (t_addr pa, int32 val);
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#else /* PDP11 version */
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#include "pdp11_defs.h"
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#define VM_PDP11 1
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#define TS_RDX 8
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#define TS_DIS DEV_DIS /* off by default */
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#define ADDRTEST (UNIBUS? 0177774: 0177700)
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extern uint16 *M;
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extern int32 cpu_18b, cpu_ubm;
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#define ReadB(p) ((M[(p) >> 1] >> (((p) & 1)? 8: 0)) & 0377)
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#define WriteB(p,v) M[(p) >> 1] = ((p) & 1)? \
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((M[(p) >> 1] & 0377) | ((v) << 8)): \
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((M[(p) >> 1] & ~0377) | (v))
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#define ReadW(p) M[(p) >> 1]
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#define WriteW(p,v) M[(p) >> 1] = (v)
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#endif
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#define UNIT_V_WLK (UNIT_V_UF + 0) /* write locked */
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#define UNIT_WLK (1 << UNIT_V_WLK)
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#define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write protect */
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/* TSBA/TSDB - 17772520: base address/data buffer register
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read: most recent memory address
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write word: initiate command
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write byte: diagnostic use
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*/
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/* TSSR - 17772522: subsystem status register
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TSDBX - 17772523: extended address register
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read: return status
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write word: initialize
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write byte: if odd, set extended packet address register
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*/
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#define TSSR_SC 0100000 /* special condition */
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#define TSSR_RMR 0010000 /* reg mod refused */
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#define TSSR_NXM 0004000 /* nxm */
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#define TSSR_NBA 0002000 /* need buf addr */
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#define TSSR_V_EMA 8 /* mem addr<17:16> */
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#define TSSR_EMA 0001400
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#define TSSR_SSR 0000200 /* subsystem ready */
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#define TSSR_OFL 0000100 /* offline */
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#define TSSR_V_TC 1 /* term class */
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#define TSSR_M_TC 07
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#define TSSR_TC (TSSR_M_TC << TSSR_V_TC)
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#define TC0 (0 << TSSR_V_TC) /* ok */
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#define TC1 (1 << TSSR_V_TC) /* attention */
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#define TC2 (2 << TSSR_V_TC) /* status alert */
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#define TC3 (3 << TSSR_V_TC) /* func reject */
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#define TC4 (4 << TSSR_V_TC) /* retry, moved */
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#define TC5 (5 << TSSR_V_TC) /* retry */
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#define TC6 (6 << TSSR_V_TC) /* pos lost */
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#define TC7 (7 << TSSR_V_TC) /* fatal err */
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#define TSSR_MBZ 0060060
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#define GET_TC(x) (((x) >> TSSR_V_TC) & TSSR_M_TC)
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#define TSDBX_M_XA 017 /* ext addr */
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#define TSDBX_BOOT 0000200 /* boot */
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/* Command packet offsets */
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#define CMD_PLNT 4 /* cmd pkt length */
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#define cmdhdr tscmdp[0] /* header */
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#define cmdadl tscmdp[1] /* address low */
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#define cmdadh tscmdp[2] /* address high */
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#define cmdlnt tscmdp[3] /* length */
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/* Command packet header */
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#define CMD_ACK 0100000 /* acknowledge */
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#define CMD_CVC 0040000 /* clear vol chk */
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#define CMD_OPP 0020000 /* opposite */
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#define CMD_SWP 0010000 /* swap bytes */
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#define CMD_V_MODE 8 /* mode */
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#define CMD_M_MODE 017
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#define CMD_IE 0000200 /* int enable */
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#define CMD_V_FNC 0 /* function */
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#define CMD_M_FNC 037 /* function */
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#define CMD_N_FNC (CMD_M_FNC + 1)
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#define FNC_READ 001 /* read */
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#define FNC_WCHR 004 /* write char */
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#define FNC_WRIT 005 /* write */
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#define FNC_WSSM 006 /* write mem */
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#define FNC_POS 010 /* position */
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#define FNC_FMT 011 /* format */
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#define FNC_CTL 012 /* control */
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#define FNC_INIT 013 /* init */
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#define FNC_GSTA 017 /* get status */
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#define CMD_MBZ 0000140
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#define GET_FNC(x) (((x) >> CMD_V_FNC) & CMD_M_FNC)
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#define GET_MOD(x) (((x) >> CMD_V_MODE) & CMD_M_MODE)
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/* Function test flags */
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#define FLG_MO 001 /* motion */
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#define FLG_WR 002 /* write */
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#define FLG_AD 004 /* addr mem */
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/* Message packet offsets */
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#define MSG_PLNT 8 /* packet length */
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#define msghdr tsmsgp[0] /* header */
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#define msglnt tsmsgp[1] /* length */
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#define msgrfc tsmsgp[2] /* residual frame */
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#define msgxs0 tsmsgp[3] /* ext status 0 */
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#define msgxs1 tsmsgp[4] /* ext status 1 */
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#define msgxs2 tsmsgp[5] /* ext status 2 */
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#define msgxs3 tsmsgp[6] /* ext status 3 */
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#define msgxs4 tsmsgp[7] /* ext status 4 */
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/* Message packet header */
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#define MSG_ACK 0100000 /* acknowledge */
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#define MSG_MATN 0000000 /* attention */
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#define MSG_MILL 0000400 /* illegal */
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#define MSG_MNEF 0001000 /* non exec fnc */
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#define MSG_CEND 0000020 /* end */
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#define MSG_CFAIL 0000021 /* fail */
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#define MSG_CERR 0000022 /* error */
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#define MSG_CATN 0000023 /* attention */
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/* Extended status register 0 */
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#define XS0_TMK 0100000 /* tape mark */
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#define XS0_RLS 0040000 /* rec lnt short */
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#define XS0_LET 0020000 /* log end tape */
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#define XS0_RLL 0010000 /* rec lnt long */
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#define XS0_WLE 0004000 /* write lock err */
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#define XS0_NEF 0002000 /* non exec fnc */
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#define XS0_ILC 0001000 /* illegal cmd */
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#define XS0_ILA 0000400 /* illegal addr */
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#define XS0_MOT 0000200 /* tape has moved */
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#define XS0_ONL 0000100 /* online */
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#define XS0_IE 0000040 /* int enb */
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#define XS0_VCK 0000020 /* volume check */
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#define XS0_PET 0000010 /* 1600 bpi */
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#define XS0_WLK 0000004 /* write lock */
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#define XS0_BOT 0000002 /* BOT */
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#define XS0_EOT 0000001 /* EOT */
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#define XS0_ALLCLR 0177600 /* clear at start */
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/* Extended status register 1 */
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#define XS1_UCOR 0000002 /* uncorrectable */
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/* Extended status register 2 */
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#define XS2_XTF 0000200 /* ext features */
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/* Extended status register 3 */
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#define XS3_OPI 0000100 /* op incomplete */
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#define XS3_REV 0000040 /* reverse */
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#define XS3_RIB 0000001 /* reverse to BOT */
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/* Extended status register 4 */
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#define XS4_HDS 0100000 /* high density */
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/* Write characteristics packet offsets */
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#define WCH_PLNT 5 /* packet length */
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#define wchadl tswchp[0] /* address low */
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#define wchadh tswchp[1] /* address high */
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#define wchlnt tswchp[2] /* length */
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#define wchopt tswchp[3] /* options */
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#define wchxopt tswchp[4] /* ext options */
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/* Write characteristics options */
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#define WCH_ESS 0000200 /* stop dbl tmk */
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#define WCH_ENB 0000100 /* BOT = tmk */
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#define WCH_EAI 0000040 /* enb attn int */
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#define WCH_ERI 0000020 /* enb mrls int */
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/* Write characteristics extended options */
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#define WCHX_HDS 0000040 /* high density */
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#define MAX(a,b) (((a) >= (b))? (a): (b))
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extern int32 int_req[IPL_HLVL];
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extern int32 int_vec[IPL_HLVL][32];
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extern UNIT cpu_unit;
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extern int32 cpu_log;
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extern FILE *sim_log;
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uint8 *tsxb = NULL; /* xfer buffer */
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int32 tssr = 0; /* status register */
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int32 tsba = 0; /* mem addr */
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int32 tsdbx = 0; /* data buf ext */
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int32 tscmdp[CMD_PLNT] = { 0 }; /* command packet */
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int32 tsmsgp[MSG_PLNT] = { 0 }; /* message packet */
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int32 tswchp[WCH_PLNT] = { 0 }; /* wr char packet */
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int32 ts_ownc = 0; /* tape owns cmd */
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int32 ts_ownm = 0; /* tape owns msg */
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int32 ts_qatn = 0; /* queued attn */
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int32 ts_bcmd = 0; /* boot cmd */
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int32 ts_time = 10; /* record latency */
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DEVICE ts_dev;
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t_stat ts_rd (int32 *data, int32 PA, int32 access);
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t_stat ts_wr (int32 data, int32 PA, int32 access);
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t_stat ts_svc (UNIT *uptr);
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t_stat ts_reset (DEVICE *dptr);
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t_stat ts_attach (UNIT *uptr, char *cptr);
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t_stat ts_detach (UNIT *uptr);
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t_stat ts_boot (int32 unitno, DEVICE *dptr);
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int32 ts_updtssr (int32 t);
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int32 ts_updxs0 (int32 t);
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void ts_cmpendcmd (int32 s0, int32 s1);
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void ts_endcmd (int32 ssf, int32 xs0f, int32 msg);
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/* TS data structures
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ts_dev TS device descriptor
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ts_unit TS unit list
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ts_reg TS register list
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ts_mod TS modifier list
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*/
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DIB ts_dib = { IOBA_TS, IOLN_TS, &ts_rd, &ts_wr,
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1, IVCL (TS), VEC_TS, { NULL } };
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UNIT ts_unit = { UDATA (&ts_svc, UNIT_ATTABLE + UNIT_DISABLE, 0) };
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REG ts_reg[] = {
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{ GRDATA (TSSR, tssr, TS_RDX, 16, 0) },
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{ GRDATA (TSBA, tsba, TS_RDX, 22, 0) },
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{ GRDATA (TSDBX, tsdbx, TS_RDX, 8, 0) },
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{ GRDATA (CHDR, cmdhdr, TS_RDX, 16, 0) },
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{ GRDATA (CADL, cmdadl, TS_RDX, 16, 0) },
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{ GRDATA (CADH, cmdadh, TS_RDX, 16, 0) },
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{ GRDATA (CLNT, cmdlnt, TS_RDX, 16, 0) },
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{ GRDATA (MHDR, msghdr, TS_RDX, 16, 0) },
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{ GRDATA (MRFC, msgrfc, TS_RDX, 16, 0) },
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{ GRDATA (MXS0, msgxs0, TS_RDX, 16, 0) },
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{ GRDATA (MXS1, msgxs1, TS_RDX, 16, 0) },
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{ GRDATA (MXS2, msgxs2, TS_RDX, 16, 0) },
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{ GRDATA (MXS3, msgxs3, TS_RDX, 16, 0) },
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{ GRDATA (MSX4, msgxs4, TS_RDX, 16, 0) },
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{ GRDATA (WADL, wchadl, TS_RDX, 16, 0) },
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{ GRDATA (WADH, wchadh, TS_RDX, 16, 0) },
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{ GRDATA (WLNT, wchlnt, TS_RDX, 16, 0) },
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{ GRDATA (WOPT, wchopt, TS_RDX, 16, 0) },
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{ GRDATA (WXOPT, wchxopt, TS_RDX, 16, 0) },
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{ FLDATA (INT, IREQ (TS), INT_V_TS) },
|
||
{ FLDATA (ATTN, ts_qatn, 0) },
|
||
{ FLDATA (BOOT, ts_bcmd, 0) },
|
||
{ FLDATA (OWNC, ts_ownc, 0) },
|
||
{ FLDATA (OWNM, ts_ownm, 0) },
|
||
{ DRDATA (TIME, ts_time, 24), PV_LEFT + REG_NZ },
|
||
{ DRDATA (POS, ts_unit.pos, 32), PV_LEFT + REG_RO },
|
||
{ GRDATA (DEVADDR, ts_dib.ba, TS_RDX, 32, 0), REG_HRO },
|
||
{ GRDATA (DEVVEC, ts_dib.vec, TS_RDX, 16, 0), REG_HRO },
|
||
{ NULL } };
|
||
|
||
MTAB ts_mod[] = {
|
||
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
|
||
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
|
||
{ MTAB_XTD|MTAB_VDV, 004, "ADDRESS", "ADDRESS",
|
||
&set_addr, &show_addr, NULL },
|
||
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
|
||
&set_vec, &show_vec, NULL },
|
||
{ 0 } };
|
||
|
||
DEVICE ts_dev = {
|
||
"TS", &ts_unit, ts_reg, ts_mod,
|
||
1, 10, 31, 1, TS_RDX, 8,
|
||
NULL, NULL, &ts_reset,
|
||
&ts_boot, &ts_attach, &ts_detach,
|
||
&ts_dib, DEV_DISABLE | TS_DIS | DEV_UBUS | DEV_QBUS };
|
||
|
||
/* I/O dispatch routine, I/O addresses 17772520 - 17772522
|
||
|
||
17772520 TSBA read/write
|
||
17772522 TSSR read/write
|
||
*/
|
||
|
||
t_stat ts_rd (int32 *data, int32 PA, int32 access)
|
||
{
|
||
switch ((PA >> 1) & 01) { /* decode PA<1> */
|
||
case 0: /* TSBA */
|
||
*data = tsba & DMASK; /* low 16b of ba */
|
||
break;
|
||
case 1: /* TSSR */
|
||
*data = tssr = ts_updtssr (tssr); /* update tssr */
|
||
break; }
|
||
return SCPE_OK;
|
||
}
|
||
|
||
t_stat ts_wr (int32 data, int32 PA, int32 access)
|
||
{
|
||
int32 i;
|
||
t_addr pa;
|
||
|
||
switch ((PA >> 1) & 01) { /* decode PA<1> */
|
||
case 0: /* TSDB */
|
||
if ((tssr & TSSR_SSR) == 0) { /* ready? */
|
||
tssr = tssr | TSSR_RMR; /* no, refuse */
|
||
break; }
|
||
tsba = ((tsdbx & TSDBX_M_XA) << 18) | /* form pkt addr */
|
||
((data & 03) << 16) | (data & 0177774);
|
||
tsdbx = 0; /* clr tsdbx */
|
||
tssr = ts_updtssr (tssr & TSSR_NBA); /* clr ssr, err */
|
||
msgxs0 = ts_updxs0 (msgxs0 & ~XS0_ALLCLR); /* clr, upd xs0 */
|
||
msgrfc = msgxs1 = msgxs2 = msgxs3 = msgxs4 = 0; /* clr status */
|
||
CLR_INT (TS); /* clr int req */
|
||
for (i = 0; i < CMD_PLNT; i++) { /* get cmd pkt */
|
||
if (Map_Addr (tsba, &pa) && ADDR_IS_MEM (pa))
|
||
tscmdp[i] = ReadW (pa);
|
||
else { ts_endcmd (TSSR_NXM + TC5, 0, MSG_ACK|MSG_MNEF|MSG_CFAIL);
|
||
return SCPE_OK; }
|
||
tsba = tsba + 2; } /* incr tsba */
|
||
ts_ownc = ts_ownm = 1; /* tape owns all */
|
||
sim_activate (&ts_unit, ts_time); /* activate */
|
||
break;
|
||
case 1: /* TSSR */
|
||
if (PA & 1) { /* TSDBX */
|
||
if (UNIBUS) return SCPE_OK; /* not in TS11 */
|
||
if (tssr & TSSR_SSR) { /* ready? */
|
||
tsdbx = data; /* save */
|
||
if (data & TSDBX_BOOT) {
|
||
ts_bcmd = 1;
|
||
sim_activate (&ts_unit, ts_time); } }
|
||
else tssr = tssr | TSSR_RMR; } /* no, err */
|
||
else if (access == WRITE) ts_reset (&ts_dev); /* reset */
|
||
break; }
|
||
return SCPE_OK;
|
||
}
|
||
|
||
/* Tape motion routines */
|
||
|
||
#define XTC(x,t) (((unsigned) (x) << 16) | (t))
|
||
#define GET_X(x) (((x) >> 16) & 0177777)
|
||
#define GET_T(x) ((x) & 0177777)
|
||
|
||
int32 ts_rdlntf (UNIT *uptr, t_mtrlnt *tbc)
|
||
{
|
||
fseek (uptr->fileref, uptr->pos, SEEK_SET); /* set pos */
|
||
fxread (tbc, sizeof (t_mtrlnt), 1, uptr->fileref); /* read rec lnt */
|
||
if (ferror (uptr->fileref)) { /* error? */
|
||
msgxs1 = msgxs1 | XS1_UCOR; /* uncorrectable */
|
||
return (XTC (XS0_RLS, TC6)); } /* pos lost */
|
||
if (feof (uptr->fileref) || (*tbc == MTR_EOM)) { /* end of medium? */
|
||
msgxs3 = msgxs3 | XS3_OPI; /* incomplete */
|
||
return (XTC (XS0_RLS, TC6)); } /* pos lost */
|
||
return 0;
|
||
}
|
||
|
||
int32 ts_spacef (UNIT *uptr, int32 fc, t_bool upd)
|
||
{
|
||
int32 st;
|
||
t_mtrlnt tbc;
|
||
|
||
do { fc = (fc - 1) & DMASK; /* decr wc */
|
||
if (upd) msgrfc = fc;
|
||
if (st = ts_rdlntf (uptr, &tbc)) return st; /* read rec lnt */
|
||
uptr->pos = uptr->pos + sizeof (t_mtrlnt); /* update pos */
|
||
msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
|
||
if (tbc == MTR_TMK) /* tape mark? */
|
||
return (XTC (XS0_TMK | XS0_RLS, TC2));
|
||
uptr->pos = uptr->pos + ((MTRL (tbc) + 1) & ~1) + sizeof (t_mtrlnt);
|
||
}
|
||
while (fc != 0);
|
||
return 0;
|
||
}
|
||
|
||
int32 ts_skipf (UNIT *uptr, int32 fc)
|
||
{
|
||
int32 tc;
|
||
t_mtrlnt prvp;
|
||
t_bool tmkprv = FALSE;
|
||
|
||
msgrfc = fc;
|
||
if ((uptr->pos == 0) && (wchopt & WCH_ENB)) tmkprv = TRUE;
|
||
do { prvp = uptr->pos; /* save cur pos */
|
||
tc = ts_spacef (uptr, 0, FALSE); /* space fwd */
|
||
if (GET_X (tc) & XS0_TMK) { /* tape mark? */
|
||
msgrfc = (msgrfc - 1) & DMASK; /* decr count */
|
||
if (tmkprv && (wchopt & WCH_ESS) &&
|
||
(uptr->pos - prvp == sizeof (t_mtrlnt)))
|
||
return (XTC ((msgrfc? XS0_RLS: 0) |
|
||
XS0_TMK | XS0_LET, TC2));
|
||
tmkprv = TRUE; }
|
||
else { if (tc) return tc; /* other err? */
|
||
tmkprv = FALSE; } }
|
||
while (msgrfc != 0);
|
||
return 0;
|
||
}
|
||
|
||
int32 ts_rdlntr (UNIT *uptr, t_mtrlnt *tbc)
|
||
{
|
||
msgxs3 = msgxs3 | XS3_REV; /* set rev op */
|
||
if (uptr->pos < sizeof (t_mtrlnt)) { /* BOT? */
|
||
msgxs3 = msgxs3 | XS3_RIB; /* set status */
|
||
return (XTC (XS0_BOT | XS0_RLS, TC2)); } /* tape alert */
|
||
fseek (uptr->fileref, uptr->pos - sizeof (t_mtrlnt), SEEK_SET);
|
||
fxread (tbc, sizeof (t_mtrlnt), 1, uptr->fileref);
|
||
if (ferror (uptr->fileref)) { /* error? */
|
||
msgxs1 = msgxs1 | XS1_UCOR; /* uncorrectable */
|
||
return (XTC (XS0_RLS, TC6)); } /* pos lost */
|
||
if (feof (uptr->fileref)) { /* end of file? */
|
||
msgxs3 = msgxs3 | XS3_OPI; /* incomplete */
|
||
return (XTC (XS0_RLS, TC6)); } /* pos lost */
|
||
if (*tbc == MTR_EOM) { /* eom? */
|
||
msgxs3 = msgxs3 | XS3_OPI; /* incomplete */
|
||
uptr->pos = uptr->pos - sizeof (t_mtrlnt); /* spc over eom */
|
||
return (XTC (XS0_RLS, TC6)); } /* pos lost */
|
||
return 0;
|
||
}
|
||
|
||
int32 ts_spacer (UNIT *uptr, int32 fc, t_bool upd)
|
||
{
|
||
int32 st;
|
||
t_mtrlnt tbc;
|
||
|
||
if (upd) msgrfc = fc;
|
||
do { fc = (fc - 1) & DMASK; /* decr wc */
|
||
if (upd) msgrfc = fc;
|
||
if (st = ts_rdlntr (uptr, &tbc)) return st; /* read rec lnt */
|
||
uptr->pos = uptr->pos - sizeof (t_mtrlnt); /* update pos */
|
||
msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
|
||
if (tbc == MTR_TMK) /* tape mark? */
|
||
return (XTC (XS0_TMK | XS0_RLS, TC2));
|
||
uptr->pos = uptr->pos - ((MTRL (tbc) + 1) & ~1) - sizeof (t_mtrlnt);
|
||
}
|
||
while (fc != 0);
|
||
return 0;
|
||
}
|
||
|
||
int32 ts_skipr (UNIT *uptr, int32 fc)
|
||
{
|
||
int32 tc;
|
||
t_mtrlnt prvp;
|
||
t_bool tmkprv = FALSE;
|
||
|
||
msgrfc = fc;
|
||
do { prvp = uptr->pos; /* save cur pos */
|
||
tc = ts_spacer (uptr, 0, FALSE); /* space rev */
|
||
if (GET_X (tc) & XS0_TMK) { /* tape mark? */
|
||
msgrfc = (msgrfc - 1) & DMASK; /* decr wc */
|
||
if (tmkprv && (wchopt & WCH_ESS) &&
|
||
(prvp - uptr->pos == sizeof (t_mtrlnt)))
|
||
return (XTC ((msgrfc? XS0_RLS: 0) |
|
||
XS0_TMK | XS0_LET, TC2));
|
||
tmkprv = TRUE; }
|
||
else { if (tc) return tc; /* other err? */
|
||
tmkprv = FALSE; } }
|
||
while (msgrfc != 0);
|
||
return 0;
|
||
}
|
||
|
||
int32 ts_readf (UNIT *uptr, uint32 fc)
|
||
{
|
||
int32 st;
|
||
t_mtrlnt i, tbc, wbc;
|
||
t_addr wa, pa;
|
||
|
||
msgrfc = fc;
|
||
if (st = ts_rdlntf (uptr, &tbc)) return st; /* read rec lnt */
|
||
if (tbc == MTR_TMK) { /* tape mark? */
|
||
uptr->pos = uptr->pos + sizeof (t_mtrlnt); /* update pos */
|
||
msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
|
||
return (XTC (XS0_TMK | XS0_RLS, TC2)); }
|
||
if (fc == 0) fc = 0200000; /* byte count */
|
||
tsba = (cmdadh << 16) | cmdadl; /* buf addr */
|
||
tbc = MTRL (tbc); /* ignore err flag */
|
||
if (tbc > MT_MAXFR) { /* record too long? */
|
||
msgxs1 = msgxs1 | XS1_UCOR; /* uncorrectable */
|
||
return XTC (XS0_RLS, TC6); } /* pos lost */
|
||
wbc = (tbc > fc)? fc: tbc; /* cap buf size */
|
||
i = fxread (tsxb, sizeof (uint8), wbc, uptr->fileref); /* read record */
|
||
if (ferror (uptr->fileref)) { /* error? */
|
||
msgxs1 = msgxs1 | XS1_UCOR; /* uncorrectable */
|
||
return XTC (XS0_RLS, TC6); } /* pos lost */
|
||
for ( ; i < wbc; i++) tsxb[i] = 0; /* fill with 0's */
|
||
uptr->pos = uptr->pos + ((tbc + 1) & ~1) + (2 * sizeof (t_mtrlnt));
|
||
msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
|
||
for (i = 0; i < wbc; i++) { /* copy buffer */
|
||
wa = (cmdhdr & CMD_SWP)? tsba ^ 1: tsba; /* apply OPP */
|
||
if (Map_Addr (wa, &pa) && ADDR_IS_MEM (pa)) /* map addr, nxm? */
|
||
WriteB (pa, tsxb[i]); /* no, store */
|
||
else { tssr = ts_updtssr (tssr | TSSR_NXM); /* set error */
|
||
return (XTC (XS0_RLS, TC4)); }
|
||
tsba = tsba + 1;
|
||
msgrfc = (msgrfc - 1) & DMASK; }
|
||
if (msgrfc) return (XTC (XS0_RLS, TC2)); /* buf too big? */
|
||
if (tbc > wbc) return (XTC (XS0_RLL, TC2)); /* rec too big? */
|
||
return 0;
|
||
}
|
||
|
||
int32 ts_readr (UNIT *uptr, uint32 fc)
|
||
{
|
||
int32 st;
|
||
t_mtrlnt i, tbc, wbc;
|
||
t_addr wa, pa;
|
||
|
||
msgrfc = fc;
|
||
if (st = ts_rdlntr (uptr, &tbc)) return st; /* read rec lnt */
|
||
if (tbc == MTR_TMK) { /* tape mark? */
|
||
uptr->pos = uptr->pos - sizeof (t_mtrlnt); /* update pos */
|
||
msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
|
||
return XTC (XS0_TMK | XS0_RLS, TC2); }
|
||
if (fc == 0) fc = 0200000; /* byte count */
|
||
tsba = (cmdadh << 16) | cmdadl + fc; /* buf addr */
|
||
tbc = MTRL (tbc); /* ignore err flag */
|
||
if (tbc > MT_MAXFR) { /* record too long? */
|
||
msgxs1 = msgxs1 | XS1_UCOR; /* uncorrectable */
|
||
return XTC (XS0_RLS, TC6); } /* pos lost */
|
||
wbc = (tbc > fc)? fc: tbc; /* cap buf size */
|
||
fseek (uptr->fileref, uptr->pos - sizeof (t_mtrlnt) - wbc, SEEK_SET);
|
||
i = fxread (tsxb, sizeof (uint8), wbc, uptr->fileref);
|
||
for ( ; i < wbc; i++) tsxb[i] = 0; /* fill with 0's */
|
||
if (ferror (uptr->fileref)) { /* error? */
|
||
msgxs1 = msgxs1 | XS1_UCOR; /* uncorrectable */
|
||
return XTC (XS0_RLS, TC6); } /* pos lost */
|
||
uptr->pos = uptr->pos - ((tbc + 1) & ~1) - (2 * sizeof (t_mtrlnt));
|
||
msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
|
||
for (i = wbc; i > 0; i--) { /* copy buffer */
|
||
tsba = tsba - 1;
|
||
wa = (cmdhdr & CMD_SWP)? tsba ^ 1: tsba; /* apply OPP */
|
||
if (Map_Addr (wa, &pa) && ADDR_IS_MEM (pa)) /* map addr, nxm? */
|
||
WriteB (pa, tsxb[i - 1]); /* no, store */
|
||
else { tssr = ts_updtssr (tssr | TSSR_NXM);
|
||
return (XTC (XS0_RLS, TC4)); }
|
||
msgrfc = (msgrfc - 1) & DMASK; }
|
||
if (msgrfc) return (XTC (XS0_RLS, TC2)); /* buf too big? */
|
||
if (tbc > wbc) return (XTC (XS0_RLL, TC2)); /* rec too big? */
|
||
return 0;
|
||
}
|
||
|
||
int32 ts_write (UNIT *uptr, int32 fc)
|
||
{
|
||
int32 i, ebc;
|
||
t_addr wa, pa;
|
||
|
||
msgrfc = fc;
|
||
if (fc == 0) fc = 0200000; /* byte count */
|
||
tsba = (cmdadh << 16) | cmdadl; /* buf addr */
|
||
for (i = 0; i < fc; i++) { /* copy mem to buf */
|
||
wa = (cmdhdr & CMD_SWP)? tsba ^ 1: tsba; /* apply OPP */
|
||
if (Map_Addr (wa, &pa) && ADDR_IS_MEM (pa)) /* map addr, nxm? */
|
||
tsxb[i] = ReadB (pa); /* no, store */
|
||
else { tssr = ts_updtssr (tssr | TSSR_NXM);
|
||
return TC5; }
|
||
tsba = tsba + 1; }
|
||
ebc = (fc + 1) & ~1; /* force even */
|
||
fseek (uptr->fileref, uptr->pos, SEEK_SET); /* position */
|
||
fxwrite (&fc, sizeof (t_mtrlnt), 1, uptr->fileref);
|
||
fxwrite (tsxb, sizeof (uint8), ebc, uptr->fileref);
|
||
fxwrite (&fc, sizeof (t_mtrlnt), 1, uptr->fileref);
|
||
if (ferror (uptr->fileref)) { /* error? */
|
||
msgxs3 = msgxs3 | XS3_OPI;
|
||
return TC6; }
|
||
uptr->pos = uptr->pos + ebc + (2 * sizeof (t_mtrlnt)); /* update pos */
|
||
msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
|
||
msgrfc = 0;
|
||
return 0;
|
||
}
|
||
|
||
int32 ts_wtmk (UNIT *uptr)
|
||
{
|
||
t_mtrlnt bceof = MTR_TMK;
|
||
|
||
fseek (uptr->fileref, uptr->pos, SEEK_SET); /* set pos */
|
||
fxwrite (&bceof, sizeof (t_mtrlnt), 1, uptr->fileref);
|
||
if (ferror (uptr->fileref)) return TC6;
|
||
uptr->pos = uptr->pos + sizeof (t_mtrlnt); /* update position */
|
||
msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
|
||
return XTC (XS0_TMK, TC0);
|
||
}
|
||
|
||
/* Unit service */
|
||
|
||
t_stat ts_svc (UNIT *uptr)
|
||
{
|
||
int32 i, fnc, mod, st0, st1;
|
||
t_addr pa;
|
||
|
||
static const int32 fnc_mod[CMD_N_FNC] = { /* max mod+1 0 ill */
|
||
0, 4, 0, 0, 1, 2, 1, 0, /* 00 - 07 */
|
||
5, 3, 5, 1, 0, 0, 0, 1, /* 10 - 17 */
|
||
0, 0, 0, 0, 0, 0, 0, 0, /* 20 - 27 */
|
||
0, 0, 0, 0, 0, 0, 0, 0 }; /* 30 - 37 */
|
||
static const int32 fnc_flg[CMD_N_FNC] = {
|
||
0, FLG_MO+FLG_AD, 0, 0, 0, FLG_MO+FLG_WR+FLG_AD, FLG_AD, 0,
|
||
FLG_MO, FLG_MO+FLG_WR, FLG_MO, 0, 0, 0, 0, 0,
|
||
0, 0, 0, 0, 0, 0, 0, 0, /* 20 - 27 */
|
||
0, 0, 0, 0, 0, 0, 0, 0 }; /* 30 - 37 */
|
||
|
||
if (ts_bcmd) { /* boot? */
|
||
ts_bcmd = 0; /* clear flag */
|
||
uptr->pos = 0; /* rewind */
|
||
if (uptr->flags & UNIT_ATT) { /* attached? */
|
||
cmdlnt = cmdadh = cmdadl = 0; /* defang rd */
|
||
ts_spacef (uptr, 1, FALSE); /* space fwd */
|
||
ts_readf (uptr, 512); /* read blk */
|
||
tssr = ts_updtssr (tssr | TSSR_SSR); }
|
||
else tssr = ts_updtssr (tssr | TSSR_SSR | TC3);
|
||
if (cmdhdr & CMD_IE) SET_INT (TS);
|
||
return SCPE_OK; }
|
||
|
||
if (!(cmdhdr & CMD_ACK)) { /* no acknowledge? */
|
||
tssr = ts_updtssr (tssr | TSSR_SSR); /* set rdy, int */
|
||
if (cmdhdr & CMD_IE) SET_INT (TS);
|
||
ts_ownc = ts_ownm = 0; /* CPU owns all */
|
||
return SCPE_OK; }
|
||
fnc = GET_FNC (cmdhdr); /* get fnc+mode */
|
||
mod = GET_MOD (cmdhdr);
|
||
if (DBG_LOG (LOG_TS))
|
||
fprintf (sim_log, ">>TS: cmd=%o, mod=%o, buf=%o, lnt=%d, pos=%d\n",
|
||
fnc, mod, cmdadl, cmdlnt, ts_unit.pos);
|
||
if ((fnc != FNC_WCHR) && (tssr & TSSR_NBA)) { /* ~wr chr & nba? */
|
||
ts_endcmd (TC3, 0, 0); /* error */
|
||
return SCPE_OK; }
|
||
if (ts_qatn && (wchopt & WCH_EAI)) { /* attn pending? */
|
||
ts_endcmd (TC1, 0, MSG_MATN | MSG_CATN); /* send attn msg */
|
||
SET_INT (TS); /* set interrupt */
|
||
ts_qatn = 0; /* not pending */
|
||
return SCPE_OK; }
|
||
if (cmdhdr & CMD_CVC) /* cvc? clr vck */
|
||
msgxs0 = msgxs0 & ~XS0_VCK;
|
||
if ((cmdhdr & CMD_MBZ) || (mod >= fnc_mod[fnc])) { /* test mbz */
|
||
ts_endcmd (TC3, XS0_ILC, MSG_ACK | MSG_MILL | MSG_CFAIL);
|
||
return SCPE_OK; }
|
||
if ((fnc_flg[fnc] & FLG_MO) && /* mot+(vck|!att)? */
|
||
((msgxs0 & XS0_VCK) || !(uptr->flags & UNIT_ATT))) {
|
||
ts_endcmd (TC3, XS0_NEF, MSG_ACK | MSG_MNEF | MSG_CFAIL);
|
||
return SCPE_OK; }
|
||
if ((fnc_flg[fnc] & FLG_WR) && /* write? */
|
||
(uptr->flags & UNIT_WPRT)) { /* write lck? */
|
||
ts_endcmd (TC3, XS0_WLE | XS0_NEF, MSG_ACK | MSG_MNEF | MSG_CFAIL);
|
||
return SCPE_OK; }
|
||
if ((((fnc == FNC_READ) && (mod == 1)) || /* read rev */
|
||
((fnc == FNC_POS) && (mod & 1))) && /* space rev */
|
||
(uptr->pos == 0)) { /* BOT? */
|
||
ts_endcmd (TC3, XS0_NEF, MSG_ACK | MSG_MNEF | MSG_CFAIL);
|
||
return SCPE_OK; }
|
||
if ((fnc_flg[fnc] & FLG_AD) && (cmdadh & ADDRTEST)) { /* buf addr > 22b? */
|
||
ts_endcmd (TC3, XS0_ILA, MSG_ACK | MSG_MILL | MSG_CFAIL);
|
||
return SCPE_OK; }
|
||
|
||
st0 = st1 = 0;
|
||
switch (fnc) { /* case on func */
|
||
case FNC_INIT: /* init */
|
||
if (uptr->pos) msgxs0 = msgxs0 | XS0_MOT; /* set if tape moves */
|
||
uptr->pos = 0; /* rewind */
|
||
case FNC_WSSM: /* write mem */
|
||
case FNC_GSTA: /* get status */
|
||
ts_endcmd (TC0, 0, MSG_ACK | MSG_CEND); /* send end packet */
|
||
return SCPE_OK;
|
||
case FNC_WCHR: /* write char */
|
||
if ((cmdadh & ADDRTEST) || (cmdadl & 1) || (cmdlnt < 6)) {
|
||
ts_endcmd (TSSR_NBA | TC3, XS0_ILA, 0);
|
||
break; }
|
||
tsba = (cmdadh << 16) | cmdadl;
|
||
for (i = 0; (i < WCH_PLNT) && (i < (cmdlnt / 2)); i++) {
|
||
if (Map_Addr (tsba, &pa) && ADDR_IS_MEM (pa))
|
||
tswchp[i] = ReadW (pa);
|
||
else { ts_endcmd (TSSR_NBA | TSSR_NXM | TC5, 0, 0);
|
||
return SCPE_OK; }
|
||
tsba = tsba + 2; }
|
||
if ((wchlnt < ((MSG_PLNT - 1) * 2)) || (wchadh & 0177700) ||
|
||
(wchadl & 1)) ts_endcmd (TSSR_NBA | TC3, 0, 0);
|
||
else { msgxs2 = msgxs2 | XS2_XTF | 1;
|
||
tssr = ts_updtssr (tssr & ~TSSR_NBA);
|
||
ts_endcmd (TC0, 0, MSG_ACK | MSG_CEND); }
|
||
return SCPE_OK;
|
||
case FNC_CTL: /* control */
|
||
switch (mod) { /* case mode */
|
||
case 00: /* msg buf rls */
|
||
tssr = ts_updtssr (tssr | TSSR_SSR); /* set SSR */
|
||
if (wchopt & WCH_ERI) SET_INT (TS);
|
||
ts_ownc = 0; ts_ownm = 1; /* keep msg */
|
||
break;
|
||
case 01: /* rewind and unload */
|
||
if (uptr->pos) msgxs0 = msgxs0 | XS0_MOT; /* if tape moves */
|
||
detach_unit (uptr); /* unload */
|
||
ts_endcmd (TC0, 0, MSG_ACK | MSG_CEND);
|
||
break;
|
||
case 02: /* clean */
|
||
ts_endcmd (TC0, 0, MSG_ACK | MSG_CEND); /* nop */
|
||
break;
|
||
case 03: /* undefined */
|
||
ts_endcmd (TC3, XS0_ILC, MSG_ACK | MSG_MILL | MSG_CFAIL);
|
||
return SCPE_OK;
|
||
case 04: /* rewind */
|
||
if (uptr->pos) msgxs0 = msgxs0 | XS0_MOT; /* if tape moves */
|
||
uptr->pos = 0;
|
||
ts_endcmd (TC0, XS0_BOT, MSG_ACK | MSG_CEND);
|
||
break; }
|
||
break;
|
||
|
||
case FNC_READ: /* read */
|
||
switch (mod) { /* case mode */
|
||
case 00: /* fwd */
|
||
st0 = ts_readf (uptr, cmdlnt); /* read */
|
||
break;
|
||
case 01: /* back */
|
||
st0 = ts_readr (uptr, cmdlnt); /* read */
|
||
break;
|
||
case 02: /* reread fwd */
|
||
if (cmdhdr & CMD_OPP) { /* opposite? */
|
||
st0 = ts_readr (uptr, cmdlnt);
|
||
st1 = ts_spacef (uptr, 1, FALSE); }
|
||
else { st0 = ts_spacer (uptr, 1, FALSE);
|
||
st1 = ts_readf (uptr, cmdlnt); }
|
||
break;
|
||
case 03: /* reread back */
|
||
if (cmdhdr & CMD_OPP) { /* opposite */
|
||
st0 = ts_readf (uptr, cmdlnt);
|
||
st1 = ts_spacer (uptr, 1, FALSE); }
|
||
else { st0 = ts_spacef (uptr, 1, FALSE);
|
||
st1 = ts_readr (uptr, cmdlnt); }
|
||
break; }
|
||
ts_cmpendcmd (st0, st1);
|
||
break;
|
||
case FNC_WRIT: /* write */
|
||
switch (mod) { /* case mode */
|
||
case 00: /* write */
|
||
st0 = ts_write (uptr, cmdlnt);
|
||
break;
|
||
case 01: /* rewrite */
|
||
st0 = ts_spacer (uptr, 1, FALSE);
|
||
st1 = ts_write (uptr, cmdlnt);
|
||
break; }
|
||
ts_cmpendcmd (st0, st1);
|
||
break;
|
||
case FNC_FMT: /* format */
|
||
switch (mod) { /* case mode */
|
||
case 00: /* write tmk */
|
||
st0 = ts_wtmk (uptr);
|
||
break;
|
||
case 01: /* erase */
|
||
break;
|
||
case 02: /* retry tmk */
|
||
st0 = ts_spacer (uptr, 1, FALSE);
|
||
st1 = ts_wtmk (uptr);
|
||
break; }
|
||
ts_cmpendcmd (st0, st1);
|
||
break;
|
||
case FNC_POS:
|
||
switch (mod) { /* case mode */
|
||
case 00: /* space fwd */
|
||
st0 = ts_spacef (uptr, cmdadl, TRUE);
|
||
break;
|
||
case 01: /* space rev */
|
||
st0 = ts_spacer (uptr, cmdadl, TRUE);
|
||
break;
|
||
case 02: /* space ffwd */
|
||
st0 = ts_skipf (uptr, cmdadl);
|
||
break;
|
||
case 03: /* space frev */
|
||
st0 = ts_skipr (uptr, cmdadl);
|
||
break;
|
||
case 04: /* rewind */
|
||
if (uptr->pos) msgxs0 = msgxs0 | XS0_MOT; /* if tape moves */
|
||
uptr->pos = 0;
|
||
break; }
|
||
ts_cmpendcmd (st0, 0);
|
||
break; }
|
||
return SCPE_OK;
|
||
}
|
||
|
||
/* Utility routines */
|
||
|
||
int32 ts_updtssr (int32 t)
|
||
{
|
||
t = (t & ~TSSR_EMA) | ((tsba >> (16 - TSSR_V_EMA)) & TSSR_EMA);
|
||
if (ts_unit.flags & UNIT_ATT) t = t & ~TSSR_OFL;
|
||
else t = t | TSSR_OFL;
|
||
return (t & ~TSSR_MBZ);
|
||
}
|
||
|
||
int32 ts_updxs0 (int32 t)
|
||
{
|
||
t = (t & ~(XS0_ONL | XS0_WLK | XS0_BOT | XS0_IE)) | XS0_PET;
|
||
if (ts_unit.flags & UNIT_ATT) {
|
||
t = t | XS0_ONL;
|
||
if (ts_unit.flags & UNIT_WPRT) t = t | XS0_WLK;
|
||
if (ts_unit.pos == 0) t = (t | XS0_BOT) & ~XS0_EOT; }
|
||
else t = t & ~XS0_EOT;
|
||
if (cmdhdr & CMD_IE) t = t | XS0_IE;
|
||
return t;
|
||
}
|
||
|
||
void ts_cmpendcmd (int32 s0, int32 s1)
|
||
{
|
||
int32 xs0, ssr, tc;
|
||
static const int32 msg[8] = {
|
||
MSG_ACK | MSG_CEND, MSG_ACK | MSG_MATN | MSG_CATN,
|
||
MSG_ACK | MSG_CEND, MSG_ACK | MSG_CFAIL,
|
||
MSG_ACK | MSG_CERR, MSG_ACK | MSG_CERR,
|
||
MSG_ACK | MSG_CERR, MSG_ACK | MSG_CERR };
|
||
|
||
xs0 = GET_X (s0) | GET_X (s1); /* or XS0 errs */
|
||
s0 = GET_T (s0); /* get SSR errs */
|
||
s1 = GET_T (s1);
|
||
ssr = (s0 | s1) & ~TSSR_TC; /* or SSR errs */
|
||
tc = MAX (GET_TC (s0), GET_TC (s1)); /* max term code */
|
||
ts_endcmd (ssr | (tc << TSSR_V_TC), xs0, msg[tc]); /* end cmd */
|
||
return;
|
||
}
|
||
|
||
void ts_endcmd (int32 tc, int32 xs0, int32 msg)
|
||
{
|
||
int32 i;
|
||
t_addr pa;
|
||
|
||
msgxs0 = ts_updxs0 (msgxs0 | xs0); /* update XS0 */
|
||
if (wchxopt & WCHX_HDS) msgxs4 = msgxs4 | XS4_HDS; /* update XS4 */
|
||
if (msg && !(tssr & TSSR_NBA)) { /* send end pkt */
|
||
msghdr = msg;
|
||
msglnt = wchlnt - 4; /* exclude hdr, bc */
|
||
tsba = (wchadh << 16) | wchadl;
|
||
for (i = 0; (i < MSG_PLNT) && (i < (wchlnt / 2)); i++) {
|
||
if (Map_Addr (tsba, &pa) && ADDR_IS_MEM (pa))
|
||
WriteW (pa, tsmsgp[i]);
|
||
else { tssr = tssr | TSSR_NXM;
|
||
tc = (tc & ~TSSR_TC) | TC4;
|
||
break; }
|
||
tsba = tsba + 2; } }
|
||
tssr = ts_updtssr (tssr | tc | TSSR_SSR | (tc? TSSR_SC: 0));
|
||
if (cmdhdr & CMD_IE) SET_INT (TS);
|
||
ts_ownm = 0; ts_ownc = 0;
|
||
if (DBG_LOG (LOG_TS))
|
||
fprintf (sim_log, ">>TS: sta=%o, tc=%o, rfc=%d, pos=%d\n",
|
||
msgxs0, GET_TC (tssr), msgrfc, ts_unit.pos);
|
||
return;
|
||
}
|
||
|
||
/* Device reset */
|
||
|
||
t_stat ts_reset (DEVICE *dptr)
|
||
{
|
||
int32 i;
|
||
|
||
ts_unit.pos = 0;
|
||
tsba = tsdbx = 0;
|
||
ts_ownc = ts_ownm = 0;
|
||
ts_bcmd = 0;
|
||
ts_qatn = 0;
|
||
tssr = ts_updtssr (TSSR_NBA | TSSR_SSR);
|
||
for (i = 0; i < CMD_PLNT; i++) tscmdp[i] = 0;
|
||
for (i = 0; i < WCH_PLNT; i++) tswchp[i] = 0;
|
||
for (i = 0; i < MSG_PLNT; i++) tsmsgp[i] = 0;
|
||
msgxs0 = ts_updxs0 (XS0_VCK);
|
||
CLR_INT (TS);
|
||
if (tsxb == NULL) tsxb = calloc (MT_MAXFR, sizeof (unsigned int8));
|
||
if (tsxb == NULL) return SCPE_MEM;
|
||
return SCPE_OK;
|
||
}
|
||
|
||
/* Attach */
|
||
|
||
t_stat ts_attach (UNIT *uptr, char *cptr)
|
||
{
|
||
t_stat r;
|
||
|
||
r = attach_unit (uptr, cptr); /* attach unit */
|
||
if (r != SCPE_OK) return r; /* error? */
|
||
tssr = tssr & ~TSSR_OFL; /* clr offline */
|
||
if ((tssr & TSSR_NBA) || !(wchopt & WCH_EAI)) return r; /* attn msg? */
|
||
if (ts_ownm) { /* own msg buf? */
|
||
ts_endcmd (TC1, 0, MSG_MATN | MSG_CATN); /* send attn */
|
||
SET_INT (TS); /* set interrupt */
|
||
ts_qatn = 0; } /* don't queue */
|
||
else ts_qatn = 1; /* else queue */
|
||
return r;
|
||
}
|
||
|
||
/* Detach routine */
|
||
|
||
t_stat ts_detach (UNIT* uptr)
|
||
{
|
||
t_stat r;
|
||
|
||
r = detach_unit (uptr); /* detach unit */
|
||
if (r != SCPE_OK) return r; /* error? */
|
||
tssr = tssr | TSSR_OFL; /* set offline */
|
||
if ((tssr & TSSR_NBA) || !(wchopt & WCH_EAI)) return r; /* attn msg? */
|
||
if (ts_ownm) { /* own msg buf? */
|
||
ts_endcmd (TC1, 0, MSG_MATN | MSG_CATN); /* send attn */
|
||
SET_INT (TS); /* set interrupt */
|
||
ts_qatn = 0; } /* don't queue */
|
||
else ts_qatn = 1; /* else queue */
|
||
return r;
|
||
}
|
||
|
||
/* Boot */
|
||
|
||
#if defined (VM_PDP11)
|
||
#define BOOT_START 01000
|
||
#define BOOT_CSR0 (BOOT_START + 006)
|
||
#define BOOT_CSR1 (BOOT_START + 012)
|
||
#define BOOT_LEN (sizeof (boot_rom) / sizeof (int16))
|
||
|
||
static const uint16 boot_rom[] = {
|
||
0012706, 0001000, /* mov #boot_start, sp */
|
||
0012700, 0172520, /* mov #tsba, r0 */
|
||
0012701, 0172522, /* mov #tssr, r1 */
|
||
0005011, /* clr (r1) ; init, rew */
|
||
0105711, /* tstb (r1) ; wait */
|
||
0100376, /* bpl .-2 */
|
||
0012710, 0001070, /* mov #pkt1, (r0) ; set char */
|
||
0105711, /* tstb (r1) ; wait */
|
||
0100376, /* bpl .-2 */
|
||
0012710, 0001110, /* mov #pkt2, (r0) ; read, skip */
|
||
0105711, /* tstb (r1) ; wait */
|
||
0100376, /* bpl .-2 */
|
||
0012710, 0001110, /* mov #pkt2, (r0) ; read */
|
||
0105711, /* tstb (r1) ; wait */
|
||
0100376, /* bpl .-2 */
|
||
0005711, /* tst (r1) ; err? */
|
||
0100421, /* bmi hlt */
|
||
0005000, /* clr r0 */
|
||
0012704, 0001066+020, /* mov #sgnt+20, r4 */
|
||
0005007, /* clr r7 */
|
||
0046523, /* sgnt: "SM" */
|
||
0140004, /* pkt1: 140004, wcpk, 0, 8. */
|
||
0001100,
|
||
0000000,
|
||
0000010,
|
||
0001122, /* wcpk: msg, 0, 14., 0 */
|
||
0000000,
|
||
0000016,
|
||
0000000,
|
||
0140001, /* pkt2: 140001, 0, 0, 512. */
|
||
0000000,
|
||
0000000,
|
||
0001000,
|
||
0000000 /* hlt: halt */
|
||
/* msg: .blk 4 */
|
||
};
|
||
|
||
t_stat ts_boot (int32 unitno, DEVICE *dptr)
|
||
{
|
||
int32 i;
|
||
extern int32 saved_PC;
|
||
|
||
ts_unit.pos = 0;
|
||
for (i = 0; i < BOOT_LEN; i++)
|
||
M[(BOOT_START >> 1) + i] = boot_rom[i];
|
||
M[BOOT_CSR0 >> 1] = ts_dib.ba & DMASK;
|
||
M[BOOT_CSR1 >> 1] = (ts_dib.ba & DMASK) + 02;
|
||
saved_PC = BOOT_START;
|
||
return SCPE_OK;
|
||
}
|
||
#else
|
||
|
||
t_stat ts_boot (int32 unitno, DEVICE *dptr)
|
||
{
|
||
return SCPE_NOFNC;
|
||
}
|
||
#endif
|