2c2dd5ea33
WARNING: V2.10 has reorganized and renamed some of the definition files for the PDP-10, PDP-11, and VAX. Be sure to delete all previous source files before you unpack the Zip archive, or unpack it into a new directory structure. WARNING: V2.10 has a new, more comprehensive save file format. Restoring save files from previous releases will cause 'invalid register' errors and loss of CPU option flags, device enable/ disable flags, unit online/offline flags, and unit writelock flags. WARNING: If you are using Visual Studio .NET through the IDE, be sure to turn off the /Wp64 flag in the project settings, or dozens of spurious errors will be generated. WARNING: Compiling Ethernet support under Windows requires extra steps; see the Ethernet readme file. Ethernet support is currently available only for Windows, Linux, NetBSD, and OpenBSD. 1. New Features 1.1 SCP and Libraries - The VT emulation package has been replaced by the capability to remote the console to a Telnet session. Telnet clients typically have more complete and robust VT100 emulation. - Simulated devices may now have statically allocated buffers, in addition to dynamically allocated buffers or disk-based data stores. - The DO command now takes substitutable arguments (max 9). In command files, %n represents substitutable argument n. - The initial command line is now interpreted as the command name and substitutable arguments for a DO command. This is backward compatible to prior versions. - The initial command line parses switches. -Q is interpreted as quiet mode; informational messages are suppressed. - The HELP command now takes an optional argument. HELP <cmd> types help on the specified command. - Hooks have been added for implementing GUI-based consoles, as well as simulator-specific command extensions. A few internal data structures and definitions have changed. - Two new routines (tmxr_open_master, tmxr_close_master) have been added to sim_tmxr.c. The calling sequence for sim_accept_conn has been changed in sim_sock.c. - The calling sequence for the VM boot routine has been modified to add an additional parameter. - SAVE now saves, and GET now restores, controller and unit flags. - Library sim_ether.c has been added for Ethernet support. 1.2 VAX - Non-volatile RAM (NVR) can behave either like a memory or like a disk-based peripheral. If unattached, it behaves like memory and is saved and restored by SAVE and RESTORE, respectively. If attached, its contents are loaded from disk by ATTACH and written back to disk at DETACH and EXIT. - SHOW <device> VECTOR displays the device's interrupt vector. A few devices allow the vector to be changed with SET <device> VECTOR=nnn. - SHOW CPU IOSPACE displays the I/O space address map. - The TK50 (TMSCP tape) has been added. - The DEQNA/DELQA (Qbus Ethernet controllers) have been added. - Autoconfiguration support has been added. - The paper tape reader has been removed from vax_stddev.c and now references a common implementation file, dec_pt.h. - Examine and deposit switches now work on all devices, not just the CPU. - Device address conflicts are not detected until simulation starts. 1.3 PDP-11 - SHOW <device> VECTOR displays the device's interrupt vector. Most devices allow the vector to be changed with SET <device> VECTOR=nnn. - SHOW CPU IOSPACE displays the I/O space address map. - The TK50 (TMSCP tape), RK611/RK06/RK07 (cartridge disk), RX211 (double density floppy), and KW11P programmable clock have been added. - The DEQNA/DELQA (Qbus Ethernet controllers) have been added. - Autoconfiguration support has been added. - The paper tape reader has been removed from pdp11_stddev.c and now references a common implementation file, dec_pt.h. - Device bootstraps now use the actual CSR specified by the SET ADDRESS command, rather than just the default CSR. Note that PDP-11 operating systems may NOT support booting with non-standard addresses. - Specifying more than 256KB of memory, or changing the bus configuration, causes all peripherals that are not compatible with the current bus configuration to be disabled. - Device address conflicts are not detected until simulation starts. 1.4 PDP-10 - SHOW <device> VECTOR displays the device's interrupt vector. A few devices allow the vector to be changed with SET <device> VECTOR=nnn. - SHOW CPU IOSPACE displays the I/O space address map. - The RX211 (double density floppy) has been added; it is off by default. - The paper tape now references a common implementation file, dec_pt.h. - Device address conflicts are not detected until simulation starts. 1.5 PDP-1 - DECtape (then known as MicroTape) support has been added. - The line printer and DECtape can be disabled and enabled. 1.6 PDP-8 - The RX28 (double density floppy) has been added as an option to the existing RX8E controller. - SHOW <device> DEVNO displays the device's device number. Most devices allow the device number to be changed with SET <device> DEVNO=nnn. - Device number conflicts are not detected until simulation starts. 1.7 IBM 1620 - The IBM 1620 simulator has been released. 1.8 AltairZ80 - A hard drive has been added for increased storage. - Several bugs have been fixed. 1.9 HP 2100 - The 12845A has been added and made the default line printer (LPT). The 12653A has been renamed LPS and is off by default. It also supports the diagnostic functions needed to run the DCPC and DMS diagnostics. - The 12557A/13210A disk defaults to the 13210A (7900/7901). - The 12559A magtape is off by default. - New CPU options (EAU/NOEAU) enable/disable the extended arithmetic instructions for the 2116. These instructions are standard on the 2100 and 21MX. - New CPU options (MPR/NOMPR) enable/disable memory protect for the 2100 and 21MX. - New CPU options (DMS/NODMS) enable/disable the dynamic mapping instructions for the 21MX. - The 12539 timebase generator autocalibrates. 1.10 Simulated Magtapes - Simulated magtapes recognize end of file and the marker 0xFFFFFFFF as end of medium. Only the TMSCP tape simulator can generate an end of medium marker. - The error handling in simulated magtapes was overhauled to be consistent through all simulators. 1.11 Simulated DECtapes - Added support for RT11 image file format (256 x 16b) to DECtapes. 2. Release Notes 2.1 Bugs Fixed - TS11/TSV05 was not simulating the XS0_MOT bit, causing failures under VMS. In addition, two of the CTL options were coded interchanged. - IBM 1401 tape was not setting a word mark under group mark for load mode reads. This caused the diagnostics to crash. - SCP bugs in ssh_break and set_logon were fixed (found by Dave Hittner). - Numerous bugs in the HP 2100 extended arithmetic, floating point, 21MX, DMS, and IOP instructions were fixed. Bugs were also fixed in the memory protect and DMS functions. The moving head disks (DP, DQ) were revised to simulate the hardware more accurately. Missing functions in DQ (address skip, read address) were added. 2.2 HP 2100 Debugging - The HP 2100 CPU nows runs all of the CPU diagnostics. - The peripherals run most of the peripheral diagnostics. There is still a problem in overlapped seek operation on the disks. See the file hp2100_diag.txt for details. 3. In Progress These simulators are not finished and are available in a separate Zip archive distribution. - Interdata 16b/32b: coded, partially tested. See the file id_diag.txt for details. - SDS 940: coded, partially tested.
865 lines
29 KiB
C
865 lines
29 KiB
C
/* pdp18b_sys.c: 18b PDP's simulator interface
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Copyright (c) 1993-2002, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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05-Oct-02 RMS Added variable device number support
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25-Jul-02 RMS Added PDP-4 DECtape support
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10-Feb-02 RMS Added PDP-7 DECtape IOT's
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03-Feb-02 RMS Fixed typo (found by Robert Alan Byer)
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17-Sep-01 RMS Removed multiconsole support
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27-May-01 RMS Added second Teletype support
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18-May-01 RMS Added PDP-9,-15 API IOT's
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12-May-01 RMS Fixed bug in RIM loaders
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14-Mar-01 RMS Added extension detection of RIM format tapes
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21-Jan-01 RMS Added DECtape support
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30-Nov-00 RMS Added PDP-9,-15 RIM/BIN loader format
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30-Oct-00 RMS Added support for examine to file
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27-Oct-98 RMS V2.4 load interface
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20-Oct-97 RMS Fixed endian dependence in RIM loader
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(found by Michael Somos)
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*/
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#include "pdp18b_defs.h"
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#include <ctype.h>
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extern DEVICE cpu_dev;
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extern DEVICE ptr_dev, ptp_dev;
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extern DEVICE tti_dev, tto_dev;
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extern UNIT tti_unit, tto_unit;
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extern DEVICE clk_dev;
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extern DEVICE lpt_dev;
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extern DEVICE dt_dev;
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#if defined (DRM)
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extern DEVICE drm_dev;
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#endif
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#if defined (RF)
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extern DEVICE rf_dev;
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#endif
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#if defined (RP)
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extern DEVICE rp_dev;
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#endif
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#if defined (MTA)
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extern DEVICE mt_dev;
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#endif
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#if defined (TTY1)
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extern DEVICE tti1_dev, tto1_dev;
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extern UNIT tti1_unit, tto1_unit;
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#endif
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extern UNIT cpu_unit;
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extern REG cpu_reg[];
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extern int32 M[];
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extern int32 memm;
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extern int32 saved_PC;
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/* SCP data structures and interface routines
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sim_name simulator name string
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sim_PC pointer to saved PC register descriptor
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sim_emax number of words for examine
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sim_devices array of pointers to simulated devices
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sim_stop_messages array of pointers to stop messages
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sim_load binary loader
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*/
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#if defined (PDP4)
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char sim_name[] = "PDP-4";
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#elif defined (PDP7)
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char sim_name[] = "PDP-7";
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#elif defined (PDP9)
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char sim_name[] = "PDP-9";
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#elif defined (PDP15)
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char sim_name[] = "PDP-15";
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#endif
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REG *sim_PC = &cpu_reg[0];
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int32 sim_emax = 3;
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DEVICE *sim_devices[] = { &cpu_dev,
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&ptr_dev, &ptp_dev,
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&tti_dev, &tto_dev,
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&clk_dev, &lpt_dev,
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#if defined (DRM)
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&drm_dev,
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#endif
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#if defined (RF)
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&rf_dev,
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#endif
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#if defined (RP)
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&rp_dev,
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#endif
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&dt_dev,
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#if defined (MTA)
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&mt_dev,
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#endif
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#if defined (TTY1)
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&tti1_dev, &tto1_dev,
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#endif
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NULL };
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const char *sim_stop_messages[] = {
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"Unknown error",
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"Undefined instruction",
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"HALT instruction",
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"Breakpoint",
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"Nested XCT's",
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"Invalid API interrupt",
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"Non-standard device number" };
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/* Binary loader */
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int32 getword (FILE *fileref, int32 *hi)
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{
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int32 word, bits, st, ch;
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word = st = bits = 0;
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do { if ((ch = getc (fileref)) == EOF) return -1;
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if (ch & 0200) {
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word = (word << 6) | (ch & 077);
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bits = (bits << 1) | ((ch >> 6) & 1);
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st++; } }
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while (st < 3);
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if (hi != NULL) *hi = bits;
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return word;
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}
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#if defined (PDP4) || defined (PDP7)
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/* PDP-4/PDP-7: RIM format only
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Tape format
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dac addr
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data
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:
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dac addr
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data
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jmp addr or hlt
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*/
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t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
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{
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int32 origin, val;
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if ((*cptr != 0) || (flag != 0)) return SCPE_ARG;
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for (;;) {
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if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
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if ((val & 0760000) == 0040000) { /* DAC? */
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origin = val & 017777;
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if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
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if (MEM_ADDR_OK (origin)) M[origin++] = val; }
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else if ((val & 0760000) == OP_JMP) { /* JMP? */
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saved_PC = ((origin - 1) & 060000) | (val & 017777);
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return SCPE_OK; }
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else if (val == OP_HLT) return SCPE_OK; /* HLT? */
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else return SCPE_FMT; } /* error */
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return SCPE_FMT; /* error */
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}
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#else
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/* PDP-9/PDP-15: RIM format and BIN format
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RIM format (read in address specified externally)
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data
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:
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data
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word to execute (bit 1 of last character set)
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BIN format (starts after RIM bootstrap)
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block/ origin (>= 0)
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count
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checksum
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data
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:
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data
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block/
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:
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endblock/ origin (< 0)
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*/
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t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
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{
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extern int32 sim_switches;
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int32 i, bits, origin, count, cksum, val;
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t_stat r;
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char gbuf[CBUFSIZE];
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extern t_bool match_ext (char *fnm, char *ext);
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/* RIM loader */
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if ((sim_switches & SWMASK ('R')) || /* RIM format? */
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(match_ext (fnam, "RIM") && !(sim_switches & SWMASK ('B')))) {
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if (*cptr != 0) { /* more input? */
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cptr = get_glyph (cptr, gbuf, 0); /* get origin */
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origin = get_uint (gbuf, 8, ADDRMASK, &r);
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if (r != SCPE_OK) return r;
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if (*cptr != 0) return SCPE_ARG; } /* no more */
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else origin = 0200; /* default 200 */
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for (;;) { /* word loop */
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if ((val = getword (fileref, &bits)) < 0) return SCPE_FMT;
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if (bits & 1) { /* end of tape? */
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if ((val & 0760000) == OP_JMP) saved_PC =
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((origin - 1) & 060000) | (val & 017777);
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else if (val != OP_HLT) return SCPE_FMT;
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break; }
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else if (MEM_ADDR_OK (origin)) M[origin++] = val; }
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return SCPE_OK; }
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/* Binary loader */
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if (*cptr != 0) return SCPE_ARG; /* no arguments */
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do { val = getc (fileref); } /* find end RIM */
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while (((val & 0100) == 0) && (val != EOF));
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if (val == EOF) rewind (fileref); /* no RIM? rewind */
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for (;;) { /* block loop */
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if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
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if (val & SIGN) {
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if (val != DMASK) saved_PC = val & 077777;
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break; }
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cksum = origin = val; /* save origin */
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if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
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cksum = cksum + val; /* add to cksum */
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count = (-val) & DMASK; /* save count */
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if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
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cksum = cksum + val; /* add to cksum */
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for (i = 0; i < count; i++) {
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if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
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cksum = cksum + val;
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if (MEM_ADDR_OK (origin)) M[origin++] = val; }
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if ((cksum & DMASK) != 0) return SCPE_CSUM; }
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return SCPE_OK;
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}
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#endif
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/* Symbol tables */
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#define I_V_FL 18 /* inst class */
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#define I_M_FL 017 /* class mask */
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#define I_V_DC 22 /* default count */
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#define I_V_NPN 0 /* no operand */
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#define I_V_NPI 1 /* no operand IOT */
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#define I_V_IOT 2 /* IOT */
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#define I_V_MRF 3 /* memory reference */
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#define I_V_OPR 4 /* OPR */
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#define I_V_LAW 5 /* LAW */
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#define I_V_XR 6 /* index */
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#define I_V_XR9 7 /* index literal */
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#define I_V_EST 8 /* EAE setup */
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#define I_V_ESH 9 /* EAE shift */
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#define I_V_EMD 10 /* EAE mul-div */
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#define I_NPN (I_V_NPN << I_V_FL) /* no operand */
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#define I_NPI (I_V_NPI << I_V_FL) /* no operand IOT */
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#define I_IOT (I_V_IOT << I_V_FL) /* IOT */
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#define I_MRF (I_V_MRF << I_V_FL) /* memory reference */
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#define I_OPR (I_V_OPR << I_V_FL) /* OPR */
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#define I_LAW (I_V_LAW << I_V_FL) /* LAW */
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#define I_XR (I_V_XR << I_V_FL) /* index */
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#define I_XR9 (I_V_XR9 << I_V_FL) /* index literal */
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#define I_EST (I_V_EST << I_V_FL) /* EAE setup */
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#define I_ESH (I_V_ESH << I_V_FL) /* EAE shift */
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#define I_EMD (I_V_EMD << I_V_FL) /* EAE mul-div */
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#define MD(x) ((I_EMD) + ((x) << I_V_DC))
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static const int32 masks[] = {
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0777777, 0777767, 0740000, 0760000,
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0763730, 0760000, 0777000, 0777000,
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0740700, 0760700, 0777700 };
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static const char *opcode[] = {
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"CAL", "DAC", "JMS", "DZM", /* mem refs */
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"LAC", "XOR", "ADD", "TAD",
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"XCT", "ISZ", "AND", "SAD",
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"JMP",
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#if defined (PDP9) || defined (PDP15) /* mem ref ind */
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"CAL*", "DAC*", "JMS*", "DZM*", /* normal */
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"LAC*", "XOR*", "ADD*", "TAD*",
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"XCT*", "ISZ*", "AND*", "SAD*",
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"JMP*",
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#else
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"CAL I", "DAC I", "JMS I", "DZM I", /* decode only */
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"LAC I", "XOR I", "ADD I", "TAD I",
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"XCT I", "ISZ I", "AND I", "SAD I",
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"JMP I",
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#endif
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"LAW", /* LAW */
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"LACQ", "LACS", "ABS", "GSM", "LMQ", /* EAE */
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"MUL", "MULS", "DIV", "DIVS",
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"IDIV", "IDIVS", "FRDIV", "FRDIVS",
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"NORM", "NORMS",
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"MUY", "LLK MUY", "DVI", "LLK DVI",
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"NMI", "NMIS", "LRS", "LRSS",
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"LLS", "LLSS", "ALS", "ALSS",
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"EAE-setup", "EAE", /* setup, general */
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"CLSF", "IOF", "ION", "CLOF", "CLON", /* standard IO devs */
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"RSF", "RRB", "RCF", "RSA", "RSB",
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"PSF", "PCF", "PSA", "PSB", "PLS",
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"KSF", "KRB", "KCF", "IORS", "IOOS",
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"TSF", "TCF", "TPC", "TLS",
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#if defined (TYPE62) /* PDP-4 LPT */
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"LPSF", "LPCF", "LPLD", "LPSE",
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"LSSF", "LSCF", "LSPR",
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#elif defined (TYPE647) /* PDP-7, PDP-9 LPT */
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"LPSF", "LPCB", "LPCD", "LPCD", "LPCD",
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"LPL2", "LPLD", "LPL1",
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"LPEF", "LPCF", "LPCF", "LPCF", "LPCF",
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"LPPB", "LPLS", "LPPS",
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#elif defined (LP15) /* PDP-15 LPT */
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"LPSF", "LPPM", "LPP1", "LPDI",
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"LPRS", "LPOS", "LPEI", "LPCD", "LPCF",
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#endif
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#if defined (DRM) /* drum */
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"DRLR", "DRLW", "DRSS", "DRCS",
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"DRSF", "DRSN", "DRCF",
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"DRLCRD", "DRLCWR", "DRLBLK", "DRCONT",
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"DRSF", "DRSOK", "DRCF",
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#endif
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#if defined (RF) /* RF09 */
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"DSSF", "DSCC", "DSCF",
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"DRBR", "DRAL", "DSFX", "DRAH",
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"DLBR", "DLAL", "DSCN", "DLAH",
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"DLOK", "DSCD", "DSRS",
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"DGHS", "DGSS",
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#endif
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#if defined (RP)
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"DPSF", "DPSA", "DPSJ", "DPSE",
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"DPRSA", "DPOSA", "DPRSB", "DPOSB",
|
||
"DPRM", "DPOM",
|
||
"DPLA", "DPCS", "DPCA", "DPWC",
|
||
"DPLM", "DPEM", "DPSN",
|
||
"DPRU", "DPOU", "DPRA", "DPOA",
|
||
"DPRC", "DPOC", "DPRW", "DPOW",
|
||
"DPCF", "DPLZ", "DPCN", "DPLO", "DPLF",
|
||
#endif
|
||
#if defined (MTA) /* TC59 */
|
||
"MTTR", "MTCR", "MTSF", "MTRC", "MTAF",
|
||
"MTRS", "MTGO", "MTCM", "MTLC",
|
||
#endif
|
||
#if defined (TYPE550) /* Type 550 */
|
||
"MMDF", "MMEF", "MMRD", "MMWR",
|
||
"MMBF", "MMRS", "MMLC", "MMSE",
|
||
#elif defined (TC02) /* TC02/TC15 */
|
||
"DTCA", "DTRA", "DTXA", "DTLA",
|
||
"DTEF", "DTRB", "DTDF",
|
||
#endif
|
||
#if defined (TTY1)
|
||
"KSF1", "KRB1",
|
||
"TSF1", "TCF1", "TLS1", "TCF1!TLS1",
|
||
#endif
|
||
#if defined (PDP7)
|
||
"ITON", "TTS", "SKP7", "CAF",
|
||
"SEM", "EEM", "EMIR", "LEM",
|
||
#endif
|
||
#if defined (PDP9)
|
||
"SKP7", "SEM", "EEM", "LEM",
|
||
"LPDI", "LPEI",
|
||
#endif
|
||
#if defined (PDP15)
|
||
"SPCO", "SKP15", "RES",
|
||
"SBA", "DBA", "EBA",
|
||
"AAS", "PAX", "PAL", "AAC",
|
||
"PXA", "AXS", "PXL", "PLA",
|
||
"PLX", "CLAC","CLX", "CLLR", "AXR",
|
||
#endif
|
||
#if defined (PDP9) || defined (PDP15)
|
||
"MPSK", "MPSNE", "MPCV", "MPEU",
|
||
"MPLD", "MPCNE", "PFSF",
|
||
"TTS", "CAF", "DBK", "DBR",
|
||
"SPI", "RPL", "ISA",
|
||
#endif
|
||
"IOT", /* general */
|
||
|
||
"NOP", "STL", "RCL", "RCR",
|
||
"CLC", "LAS", "GLK",
|
||
"OPR", "SMA", "SZA", "SZA SMA",
|
||
"SNL", "SNL SMA", "SNL SZA", "SNL SZA SMA",
|
||
"SKP", "SPA", "SNA", "SNA SPA",
|
||
"SZL", "SZL SPA", "SZL SNA", "SZL SZA SPA",
|
||
"RAL", "SMA RAL", "SZA RAL", "SZA SMA RAL",
|
||
"SNL RAL", "SNL SMA RAL", "SNL SZA RAL", "SNL SZA SMA RAL",
|
||
"SKP RAL", "SPA RAL", "SNA RAL", "SNA SPA RAL",
|
||
"SZL RAL", "SZL SPA RAL", "SZL SNA RAL", "SZL SZA SPA RAL",
|
||
"RAR", "SMA RAR", "SZA RAR", "SZA SMA RAR",
|
||
"SNL RAR", "SNL SMA RAR", "SNL SZA RAR", "SNL SZA SMA RAR",
|
||
"SKP RAR", "SPA RAR", "SNA RAR", "SNA SPA RAR",
|
||
"SZL RAR", "SZL SPA RAR", "SZL SNA RAR", "SZL SZA SPA RAR",
|
||
#if defined (PDP15)
|
||
"IAC", "SMA IAC", "SZA IAC", "SZA SMA IAC",
|
||
"SNL IAC", "SNL SMA IAC", "SNL SZA IAC", "SNL SZA SMA IAC",
|
||
"SKP IAC", "SPA IAC", "SNA IAC", "SNA SPA IAC",
|
||
"SZL IAC", "SZL SPA IAC", "SZL SNA IAC", "SZL SZA SPA IAC",
|
||
#else
|
||
"RAL RAR", "SMA RAL RAR", "SZA RAL RAR", "SZA SMA RAL RAR",
|
||
"SNL RAL RAR", "SNL SMA RAL RAR", "SNL SZA RAL RAR", "SNL SZA SMA RAL RAR",
|
||
"SKP RAL RAR", "SPA RAL RAR", "SNA RAL RAR", "SNA SPA RAL RAR",
|
||
"SZL RAL RAR", "SZL SPA RAL RAR", "SZL SNA RAL RAR", "SZL SZA SPA RAL RAR",
|
||
#endif
|
||
"RTWO", "SMA RTWO", "SZA RTWO", "SZA SMA RTWO",
|
||
"SNL RTWO", "SNL SMA RTWO", "SNL SZA RTWO", "SNL SZA SMA RTWO",
|
||
"SKP RTWO", "SPA RTWO", "SNA RTWO", "SNA SPA RTWO",
|
||
"SZL RTWO", "SZL SPA RTWO", "SZL SNA RTWO", "SZL SZA SPA RTWO",
|
||
"RTL", "SMA RTL", "SZA RTL", "SZA SMA RTL",
|
||
"SNL RTL", "SNL SMA RTL", "SNL SZA RTL", "SNL SZA SMA RTL",
|
||
"SKP RTL", "SPA RTL", "SNA RTL", "SNA SPA RTL",
|
||
"SZL RTL", "SZL SPA RTL", "SZL SNA RTL", "SZL SZA SPA RTL",
|
||
"RTR", "SMA RTR", "SZA RTR", "SZA SMA RTR",
|
||
"SNL RTR", "SNL SMA RTR", "SNL SZA RTR", "SNL SZA SMA RTR",
|
||
"SKP RTR", "SPA RTR", "SNA RTR", "SNA SPA RTR",
|
||
"SZL RTR", "SZL SPA RTR", "SZL SNA RTR", "SZL SZA SPA RTR",
|
||
#if defined (PDP15)
|
||
"BSW", "SMA BSW", "SZA BSW", "SZA SMA BSW",
|
||
"SNL BSW", "SNL SMA BSW", "SNL SZA BSW", "SNL SZA SMA BSW",
|
||
"SKP BSW", "SPA BSW", "SNA BSW", "SNA SPA BSW",
|
||
"SZL BSW", "SZL SPA BSW", "SZL SNA BSW", "SZL SZA SPA BSW",
|
||
#else
|
||
"RTL RTR", "SMA RTL RTR", "SZA RTL RTR", "SZA SMA RTL RTR",
|
||
"SNL RTL RTR", "SNL SMA RTL RTR", "SNL SZA RTL RTR", "SNL SZA SMA RTL RTR",
|
||
"SKP RTL RTR", "SPA RTL RTR", "SNA RTL RTR", "SNA SPA RTL RTR",
|
||
"SZL RTL RTR", "SZL SPA RTL RTR", "SZL SNA RTL RTR", "SZL SZA SPA RTL RTR",
|
||
#endif
|
||
|
||
"LLK", "CLQ", "LSN", "OACQ", "ECLA", /* encode only masks */
|
||
"CMQ", "OMQ", "OSC",
|
||
"CLA", "CLL", "CML", "CMA",
|
||
"OAS", "HLT",
|
||
NULL };
|
||
|
||
static const int32 opc_val[] = {
|
||
0000000+I_MRF, 0040000+I_MRF, 0100000+I_MRF, 0140000+I_MRF,
|
||
0200000+I_MRF, 0240000+I_MRF, 0300000+I_MRF, 0340000+I_MRF,
|
||
0400000+I_MRF, 0440000+I_MRF, 0500000+I_MRF, 0540000+I_MRF,
|
||
0600000+I_MRF,
|
||
0020000+I_MRF, 0060000+I_MRF, 0120000+I_MRF, 0160000+I_MRF,
|
||
0220000+I_MRF, 0260000+I_MRF, 0320000+I_MRF, 0360000+I_MRF,
|
||
0420000+I_MRF, 0460000+I_MRF, 0520000+I_MRF, 0560000+I_MRF,
|
||
0620000+I_MRF,
|
||
|
||
0760000+I_LAW,
|
||
|
||
0641002+I_NPN, 0641001+I_NPN, 0644000+I_NPN, 0664000+I_NPN, 0652000+I_NPN,
|
||
0653100+MD(022), 0657100+MD(022), 0640300+MD(023), 0644300+MD(023),
|
||
0653300+MD(023), 0657300+MD(023), 0650300+MD(023), 0654300+MD(023),
|
||
0640400+MD(044), 0660400+MD(044),
|
||
0640100+I_ESH, 0660100+I_ESH, 0640300+I_ESH, 0660300+I_ESH,
|
||
0640400+I_ESH, 0660400+I_ESH, 0640500+I_ESH, 0660500+I_ESH,
|
||
0640600+I_ESH, 0660600+I_ESH, 0640700+I_ESH, 0660700+I_ESH,
|
||
0640000+I_EST, 0640000+I_IOT,
|
||
|
||
0700001+I_NPI, 0700002+I_NPI, 0700042+I_NPI, 0700004+I_NPI, 0700044+I_NPI,
|
||
0700101+I_NPI, 0700112+I_NPN, 0700102+I_NPI, 0700104+I_NPI, 0700144+I_NPI,
|
||
0700201+I_NPI, 0700202+I_NPI, 0700204+I_NPI, 0700244+I_NPI, 0700206+I_NPI,
|
||
0700301+I_NPI, 0700312+I_NPN, 0700302+I_NPI, 0700314+I_NPN, 0700304+I_NPI,
|
||
0700401+I_NPI, 0700402+I_NPI, 0700404+I_NPI, 0700406+I_NPI,
|
||
#if defined (TYPE62)
|
||
0706501+I_NPI, 0706502+I_NPI, 0706542+I_NPI, 0706506+I_NPI,
|
||
0706601+I_NPI, 0706602+I_NPI, 0706606+I_NPI,
|
||
#elif defined (TYPE647)
|
||
0706501+I_NPI, 0706502+I_NPI, 0706522+I_NPI, 0706542+I_NPI, 0706562+I_NPI,
|
||
0706526+I_NPI, 0706546+I_NPI, 0706566+I_NPI,
|
||
0706601+I_NPI, 0706602+I_NPI, 0706622+I_NPI, 0706642+I_NPI, 0706662+I_NPI,
|
||
0706606+I_NPI, 0706626+I_NPI, 0706646+I_NPI,
|
||
#elif defined (LP15)
|
||
0706501+I_NPI, 0706521+I_NPI, 0706541+I_NPI, 0706561+I_NPI,
|
||
0706552+I_NPN, 0706542+I_NPI, 0706544+I_NPI, 0706621+I_NPI, 0706641+I_NPI,
|
||
#endif
|
||
#if defined (DRM)
|
||
0706006+I_NPI, 0706046+I_NPI, 0706106+I_NPI, 0706204+I_NPI,
|
||
0706101+I_NPI, 0706201+I_NPI, 0706102+I_NPI,
|
||
0706006+I_NPI, 0706046+I_NPI, 0706106+I_NPI, 0706204+I_NPI,
|
||
0706101+I_NPI, 0706201+I_NPI, 0706102+I_NPI,
|
||
#endif
|
||
#if defined (RF)
|
||
0707001+I_NPI, 0707021+I_NPI, 0707041+I_NPI,
|
||
0707002+I_NPI, 0707022+I_NPI, 0707042+I_NPI, 0707062+I_NPI,
|
||
0707004+I_NPI, 0707024+I_NPI, 0707044+I_NPI, 0707064+I_NPI,
|
||
0707202+I_NPI, 0707242+I_NPI, 0707262+I_NPI,
|
||
0707204+I_NPI, 0707224+I_NPI,
|
||
#endif
|
||
#if defined (RP)
|
||
0706301+I_NPI, 0706321+I_NPI, 0706341+I_NPI, 0706361+I_NPI,
|
||
0706312+I_NPN, 0706302+I_NPI, 0706332+I_NPN, 0706322+I_NPI,
|
||
0706342+I_NPN, 0706352+I_NPI,
|
||
0706304+I_NPI, 0706324+I_NPI, 0706344+I_NPI, 0706364+I_NPI,
|
||
0706411+I_NPN, 0706401+I_NPI, 0706421+I_NPI,
|
||
0706412+I_NPN, 0706402+I_NPI, 0706432+I_NPN, 0706422+I_NPI,
|
||
0706452+I_NPN, 0706442+I_NPI, 0706472+I_NPN, 0706462+I_NPI,
|
||
0706404+I_NPI, 0706424+I_NPI, 0706454+I_NPN, 0706444+I_NPI, 0706464+I_NPI,
|
||
#endif
|
||
#if defined (MTA)
|
||
0707301+I_NPI, 0707321+I_NPI, 0707341+I_NPI, 0707312+I_NPN, 0707322+I_NPI,
|
||
0707352+I_NPN, 0707304+I_NPI, 0707324+I_NPI, 0707326+I_NPI,
|
||
#endif
|
||
#if defined (TYPE550) /* Type 550 */
|
||
0707501+I_NPI, 0707541+I_NPI, 0707512+I_NPN, 0707504+I_NPI,
|
||
0707601+I_NPI, 0707612+I_NPN, 0707604+I_NPI, 0707644+I_NPI,
|
||
#elif defined (TC02) /* TC02/TC15 */
|
||
0707541+I_NPI, 0707552+I_NPN, 0707544+I_NPI, 0707545+I_NPI,
|
||
0707561+I_NPI, 0707572+I_NPN, 0707601+I_NPI,
|
||
#endif
|
||
#if defined (TTY1)
|
||
0704101+I_NPI, 0704112+I_NPN,
|
||
0704001+I_NPI, 0704002+I_NPI, 0704004+I_NPI, 0704006+I_NPI,
|
||
#endif
|
||
#if defined (PDP7)
|
||
0703201+I_NPI, 0703301+I_NPI, 0703341+I_NPI, 0703302+I_NPI,
|
||
0707701+I_NPI, 0707702+I_NPI, 0707742+I_NPI, 0707704+I_NPI,
|
||
#endif
|
||
#if defined (PDP9)
|
||
0703341+I_NPI, 0707701+I_NPI, 0707702+I_NPI, 0707704+I_NPI,
|
||
0706504+I_NPI, 0706604+I_NPI,
|
||
#endif
|
||
#if defined (PDP15)
|
||
0703341+I_NPI, 0707741+I_NPI, 0707742+I_NPI,
|
||
0707761+I_NPI, 0707762+I_NPI, 0707764+I_NPI,
|
||
0720000+I_XR9, 0721000+I_XR, 0722000+I_XR, 0723000+I_XR9,
|
||
0724000+I_XR, 0725000+I_XR9, 0726000+I_XR, 0730000+I_XR,
|
||
0731000+I_XR, 0734000+I_XR, 0735000+I_XR, 0736000+I_XR, 0737000+I_XR9,
|
||
#endif
|
||
#if defined (PDP9) || defined (PDP15)
|
||
0701701+I_NPI, 0701741+I_NPI, 0701702+I_NPI, 0701742+I_NPI,
|
||
0701704+I_NPI, 0701744+I_NPI, 0703201+I_NPI,
|
||
0703301+I_NPI, 0703302+I_NPI, 0703304+I_NPI, 0703344+I_NPI,
|
||
0705501+I_NPI, 0705512+I_NPN, 0705504+I_NPI,
|
||
#endif
|
||
0700000+I_IOT,
|
||
|
||
0740000+I_NPN, 0744002+I_NPN, 0744010+I_NPN, 0744020+I_NPN,
|
||
0750001+I_NPN, 0750004+I_NPN, 0750010+I_NPN,
|
||
0740000+I_OPR, 0740100+I_OPR, 0740200+I_OPR, 0740300+I_OPR,
|
||
0740400+I_OPR, 0740500+I_OPR, 0740600+I_OPR, 0740700+I_OPR,
|
||
0741000+I_OPR, 0741100+I_OPR, 0741200+I_OPR, 0741300+I_OPR,
|
||
0741400+I_OPR, 0741500+I_OPR, 0741600+I_OPR, 0741700+I_OPR,
|
||
0740010+I_OPR, 0740110+I_OPR, 0740210+I_OPR, 0740310+I_OPR,
|
||
0740410+I_OPR, 0740510+I_OPR, 0740610+I_OPR, 0740710+I_OPR,
|
||
0741010+I_OPR, 0741110+I_OPR, 0741210+I_OPR, 0741310+I_OPR,
|
||
0741410+I_OPR, 0741510+I_OPR, 0741610+I_OPR, 0741710+I_OPR,
|
||
0740020+I_OPR, 0740120+I_OPR, 0740220+I_OPR, 0740320+I_OPR,
|
||
0740420+I_OPR, 0740520+I_OPR, 0740620+I_OPR, 0740720+I_OPR,
|
||
0741020+I_OPR, 0741120+I_OPR, 0741220+I_OPR, 0741320+I_OPR,
|
||
0741420+I_OPR, 0741520+I_OPR, 0741620+I_OPR, 0741720+I_OPR,
|
||
0740030+I_OPR, 0740130+I_OPR, 0740230+I_OPR, 0740330+I_OPR,
|
||
0740430+I_OPR, 0740530+I_OPR, 0740630+I_OPR, 0740730+I_OPR,
|
||
0741030+I_OPR, 0741130+I_OPR, 0741230+I_OPR, 0741330+I_OPR,
|
||
0741430+I_OPR, 0741530+I_OPR, 0741630+I_OPR, 0741730+I_OPR,
|
||
0742000+I_OPR, 0742100+I_OPR, 0742200+I_OPR, 0742300+I_OPR,
|
||
0742400+I_OPR, 0742500+I_OPR, 0742600+I_OPR, 0742700+I_OPR,
|
||
0743000+I_OPR, 0743100+I_OPR, 0743200+I_OPR, 0743300+I_OPR,
|
||
0743400+I_OPR, 0743500+I_OPR, 0743600+I_OPR, 0743700+I_OPR,
|
||
0742010+I_OPR, 0742110+I_OPR, 0742210+I_OPR, 0742310+I_OPR,
|
||
0742410+I_OPR, 0742510+I_OPR, 0742610+I_OPR, 0742710+I_OPR,
|
||
0743010+I_OPR, 0743110+I_OPR, 0743210+I_OPR, 0743310+I_OPR,
|
||
0743410+I_OPR, 0743510+I_OPR, 0743610+I_OPR, 0743710+I_OPR,
|
||
0742020+I_OPR, 0742120+I_OPR, 0742220+I_OPR, 0742320+I_OPR,
|
||
0742420+I_OPR, 0742520+I_OPR, 0742620+I_OPR, 0742720+I_OPR,
|
||
0743020+I_OPR, 0743120+I_OPR, 0743220+I_OPR, 0743320+I_OPR,
|
||
0743420+I_OPR, 0743520+I_OPR, 0743620+I_OPR, 0743720+I_OPR,
|
||
0742030+I_OPR, 0742130+I_OPR, 0742230+I_OPR, 0742330+I_OPR,
|
||
0742430+I_OPR, 0742530+I_OPR, 0742630+I_OPR, 0742730+I_OPR,
|
||
0743030+I_OPR, 0743130+I_OPR, 0743230+I_OPR, 0743330+I_OPR,
|
||
0743430+I_OPR, 0743530+I_OPR, 0743630+I_OPR, 0743730+I_OPR,
|
||
|
||
0660000+I_EST, 0650000+I_EST, 0644000+I_EST, 0642000+I_EST, 0641000+I_EST,
|
||
0640004+I_EST, 0640002+I_EST, 0640001+I_EST,
|
||
0750000+I_OPR, 0744000+I_OPR, 0740002+I_OPR, 0740001+I_OPR,
|
||
0740004+I_OPR, 0740040+I_OPR,
|
||
-1 };
|
||
|
||
/* Operate or EAE decode
|
||
|
||
Inputs:
|
||
*of = output stream
|
||
inst = mask bits
|
||
class = instruction class code
|
||
sp = space needed?
|
||
Outputs:
|
||
status = space needed?
|
||
*/
|
||
|
||
int32 fprint_opr (FILE *of, int32 inst, int32 class, int32 sp)
|
||
{
|
||
int32 i, j;
|
||
|
||
for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
|
||
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
|
||
if ((j == class) && (opc_val[i] & inst)) { /* same class? */
|
||
inst = inst & ~opc_val[i]; /* mask bit set? */
|
||
fprintf (of, (sp? " %s": "%s"), opcode[i]);
|
||
sp = 1; } }
|
||
return sp;
|
||
}
|
||
|
||
/* Symbolic decode
|
||
|
||
Inputs:
|
||
*of = output stream
|
||
addr = current PC
|
||
*val = pointer to values
|
||
*uptr = pointer to unit
|
||
sw = switches
|
||
Outputs:
|
||
return = status code
|
||
*/
|
||
|
||
#define FMTASC(x) (((x) < 040)? "<%03o>": "%c", (x))
|
||
#define SIXTOASC(x) (((x) >= 040)? (x): ((x) + 0100))
|
||
|
||
t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
|
||
UNIT *uptr, int32 sw)
|
||
{
|
||
int32 cflag, i, j, k, sp, inst, disp, ma;
|
||
|
||
inst = val[0];
|
||
cflag = (uptr == NULL) || (uptr == &cpu_unit);
|
||
if (sw & SWMASK ('A')) { /* ASCII? */
|
||
if (inst > 0377) return SCPE_ARG;
|
||
fprintf (of, "%c", FMTASC (inst & 0177));
|
||
return SCPE_OK; }
|
||
if (sw & SWMASK ('C')) { /* character? */
|
||
fprintf (of, "%c", SIXTOASC ((inst >> 12) & 077));
|
||
fprintf (of, "%c", SIXTOASC ((inst >> 6) & 077));
|
||
fprintf (of, "%c", SIXTOASC (inst & 077));
|
||
return SCPE_OK; }
|
||
#if defined (PDP15)
|
||
if (sw & SWMASK ('P')) { /* packed ASCII? */
|
||
i = val[1];
|
||
fprintf (of, "%c", FMTASC ((inst >> 11) & 0177));
|
||
fprintf (of, "%c", FMTASC ((inst >> 4) & 0177));
|
||
fprintf (of, "%c", FMTASC (((inst << 3) | (i >> 15)) & 0177));
|
||
fprintf (of, "%c", FMTASC ((i >> 8) & 0177));
|
||
fprintf (of, "%c", FMTASC ((i >> 1) & 0177));
|
||
return -1; }
|
||
#endif
|
||
if (!(sw & SWMASK ('M'))) return SCPE_ARG;
|
||
|
||
/* Instruction decode */
|
||
|
||
for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
|
||
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
|
||
if ((opc_val[i] & 0777777) == (inst & masks[j])) { /* match? */
|
||
|
||
switch (j) { /* case on class */
|
||
case I_V_NPN: /* no operands */
|
||
case I_V_XR: /* index no opers */
|
||
fprintf (of, "%s", opcode[i]); /* opcode */
|
||
break;
|
||
case I_V_NPI: /* IOT no operand */
|
||
fprintf (of, "%s", opcode[i]); /* opcode */
|
||
if (inst & 010) fprintf (of, " +10");
|
||
break;
|
||
case I_V_IOT: /* IOT or EAE */
|
||
fprintf (of, "%s %-o", opcode[i], inst & 037777);
|
||
break;
|
||
case I_V_MRF: /* mem ref */
|
||
#if defined (PDP15)
|
||
if (memm) {
|
||
disp = inst & 017777;
|
||
ma = (addr & 0760000) | disp; }
|
||
else { disp = inst & 007777;
|
||
ma = (addr & 0770000) | disp; }
|
||
fprintf (of, "%s %-o", opcode[i],
|
||
(cflag? ma & ADDRMASK: disp));
|
||
if (!memm && (inst & 0010000)) fprintf (of, ",X");
|
||
#else
|
||
disp = inst & 017777;
|
||
ma = (addr & 0760000) | disp;
|
||
fprintf (of, "%s %-o", opcode[i],
|
||
(cflag? ma & ADDRMASK: disp));
|
||
#endif
|
||
break;
|
||
case I_V_OPR: /* operate */
|
||
if (sp = (inst & 03730)) fprintf (of, "%s", opcode[i]);
|
||
fprint_opr (of, inst & 014047, I_V_OPR, sp);
|
||
break;
|
||
case I_V_LAW: /* LAW */
|
||
fprintf (of, "%s %-o", opcode[i], inst & 017777);
|
||
break;
|
||
case I_V_XR9: /* index with lit */
|
||
disp = inst & 0777;
|
||
if (disp & 0400) fprintf (of, "%s -%-o", opcode[i], 01000 - disp);
|
||
else fprintf (of, "%s %-o", opcode[i], disp);
|
||
break;
|
||
case I_V_EST: /* EAE setup */
|
||
fprint_opr (of, inst & 037007, I_V_EST, 0);
|
||
break;
|
||
case I_V_ESH: /* EAE shift */
|
||
sp = fprint_opr (of, inst & 017000, I_V_EST, 0);
|
||
fprintf (of, (sp? " %s %-o": "%s %-o"), opcode[i], inst & 077);
|
||
break;
|
||
case I_V_EMD: /* EAE mul-div */
|
||
disp = inst & 077; /* get actual val */
|
||
k = (opc_val[i] >> I_V_DC) & 077; /* get default val */
|
||
if (disp == k) fprintf (of, "%s", opcode[i]);
|
||
else if (disp < k) fprintf (of, "%s -%-o", opcode[i], k - disp);
|
||
else fprintf (of, "%s +%-o", opcode[i], disp - k);
|
||
break; } /* end case */
|
||
return SCPE_OK; } /* end if */
|
||
} /* end for */
|
||
return SCPE_ARG;
|
||
}
|
||
|
||
/* Get 18b signed number
|
||
|
||
Inputs:
|
||
*cptr = pointer to input string
|
||
*sign = pointer to sign
|
||
*status = pointer to error status
|
||
Outputs:
|
||
val = output value
|
||
*/
|
||
|
||
t_value get_sint (char *cptr, int32 *sign, t_stat *status)
|
||
{
|
||
*sign = 0;
|
||
if (*cptr == '+') {
|
||
*sign = 1;
|
||
cptr++; }
|
||
else if (*cptr == '-') {
|
||
*sign = -1;
|
||
cptr++; }
|
||
return get_uint (cptr, 8, 0777777, status);
|
||
}
|
||
|
||
/* Symbolic input
|
||
|
||
Inputs:
|
||
*cptr = pointer to input string
|
||
addr = current PC
|
||
uptr = pointer to unit
|
||
*val = pointer to output values
|
||
sw = switches
|
||
Outputs:
|
||
status = error status
|
||
*/
|
||
|
||
t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
|
||
{
|
||
int32 cflag, d, i, j, k, sign, dmask, epcmask;
|
||
t_stat r;
|
||
char gbuf[CBUFSIZE];
|
||
|
||
cflag = (uptr == NULL) || (uptr == &cpu_unit);
|
||
while (isspace (*cptr)) cptr++;
|
||
for (i = 1; (i < 5) && (cptr[i] != 0); i++)
|
||
if (cptr[i] == 0) for (j = i + 1; j <= 5; j++) cptr[j] = 0;
|
||
if ((sw & SWMASK ('A')) || ((*cptr == '\'') && cptr++)) { /* ASCII char? */
|
||
if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */
|
||
val[0] = (t_value) cptr[0] | 0200;
|
||
return SCPE_OK; }
|
||
if ((sw & SWMASK ('C')) || ((*cptr == '"') && cptr++)) { /* sixbit string? */
|
||
if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */
|
||
val[0] = (((t_value) cptr[0] & 077) << 12) |
|
||
(((t_value) cptr[1] & 077) << 6) |
|
||
((t_value) cptr[2] & 077);
|
||
return SCPE_OK; }
|
||
#if defined (PDP15)
|
||
if ((sw & SWMASK ('P')) || ((*cptr == '#') && cptr++)) { /* packed string? */
|
||
if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */
|
||
val[0] = (((t_value) cptr[0] & 0177) << 11) |
|
||
(((t_value) cptr[1] & 0177) << 4) |
|
||
(((t_value) cptr[2] & 0170) >> 3);
|
||
val[1] = (((t_value) cptr[2] & 0007) << 15) |
|
||
(((t_value) cptr[3] & 0177) << 8) |
|
||
(((t_value) cptr[4] & 0177) << 1);
|
||
return -1; }
|
||
#endif
|
||
|
||
/* Symbolic input, continued */
|
||
|
||
cptr = get_glyph (cptr, gbuf, 0); /* get opcode */
|
||
for (i = 0; (opcode[i] != NULL) && (strcmp (opcode[i], gbuf) != 0) ; i++) ;
|
||
if (opcode[i] == NULL) return SCPE_ARG;
|
||
val[0] = opc_val[i] & DMASK; /* get value */
|
||
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
|
||
|
||
switch (j) { /* case on class */
|
||
case I_V_XR: /* index */
|
||
break;
|
||
case I_V_XR9: /* index literal */
|
||
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
||
d = get_sint (gbuf, &sign, &r);
|
||
if (r != SCPE_OK) return SCPE_ARG;
|
||
if (((sign >= 0) && (d > 0377)) || ((sign < 0) && (d > 0400)))
|
||
return SCPE_ARG;
|
||
val[0] = val[0] | ((sign >= 0)? d: (01000 - d));
|
||
break;
|
||
case I_V_LAW: /* law */
|
||
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
||
d = get_uint (gbuf, 8, 017777, &r);
|
||
if (r != SCPE_OK) return SCPE_ARG;
|
||
val[0] = val[0] | d;
|
||
break;
|
||
case I_V_MRF: /* mem ref */
|
||
#if defined (PDP15)
|
||
if (memm) dmask = 017777;
|
||
else dmask = 07777;
|
||
cptr = get_glyph (cptr, gbuf, ','); /* get glyph */
|
||
#else
|
||
dmask = 017777;
|
||
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
||
#endif
|
||
#if defined (PDP4) || defined (PDP7)
|
||
if (strcmp (gbuf, "I") == 0) { /* indirect? */
|
||
val[0] = val[0] | 020000;
|
||
cptr = get_glyph (cptr, gbuf, 0); }
|
||
#endif
|
||
epcmask = ADDRMASK & ~dmask; /* get ePC */
|
||
d = get_uint (gbuf, 8, ADDRMASK, &r); /* get addr */
|
||
if (r != SCPE_OK) return SCPE_ARG;
|
||
if (d <= dmask) val[0] = val[0] | d; /* fit in 12/13b? */
|
||
else if (cflag && (((addr ^ d) & epcmask) == 0))
|
||
val[0] = val[0] | (d & dmask); /* hi bits = ePC? */
|
||
else return SCPE_ARG;
|
||
#if defined (PDP15)
|
||
if (!memm) {
|
||
cptr = get_glyph (cptr, gbuf, 0);
|
||
if (gbuf[0] != 0) {
|
||
if (strcmp (gbuf, "X") != 0) return SCPE_ARG;
|
||
val[0] = val[0] | 010000; } }
|
||
#endif
|
||
break;
|
||
case I_V_EMD: /* or'able */
|
||
val[0] = val[0] | ((opc_val[i] >> I_V_DC) & 077); /* default shift */
|
||
case I_V_EST: case I_V_ESH:
|
||
case I_V_NPN: case I_V_NPI: case I_V_IOT: case I_V_OPR:
|
||
for (cptr = get_glyph (cptr, gbuf, 0); gbuf[0] != 0;
|
||
cptr = get_glyph (cptr, gbuf, 0)) {
|
||
for (i = 0; (opcode[i] != NULL) &&
|
||
(strcmp (opcode[i], gbuf) != 0) ; i++) ;
|
||
if (opcode[i] != NULL) {
|
||
k = opc_val[i] & DMASK;
|
||
if (((k ^ val[0]) & 0740000) != 0) return SCPE_ARG;
|
||
val[0] = val[0] | k; }
|
||
else { d = get_sint (gbuf, & sign, &r);
|
||
if (r != SCPE_OK) return SCPE_ARG;
|
||
if (sign > 0) val[0] = val[0] + d;
|
||
else if (sign < 0) val[0] = val[0] - d;
|
||
else val[0] = val[0] | d; } }
|
||
break; } /* end case */
|
||
if (*cptr != 0) return SCPE_ARG; /* junk at end? */
|
||
return SCPE_OK;
|
||
}
|