4ffd3be790
Because some key files have changed, V3.0 should be unzipped to a clean directory. 1. New Features in 3.0-0 1.1 SCP and Libraries - Added ASSIGN/DEASSIGN (logical name) commands. - Changed RESTORE to unconditionally detach files. - Added E11 and TPC format support to magtape library. - Fixed bug in SHOW CONNECTIONS. - Added USE_ADDR64 support 1.2 All magtapes - Magtapes support SIMH format, E11 format, and TPC format (read only). - SET <tape_unit> FORMAT=format sets the specified tape unit's format. - SHOW <tape_unit> FORMAT displays the specified tape unit's format. - Tape format can also be set as part of the ATTACH command, using the -F switch. 1.3 VAX - VAX can be compiled without USE_INT64. - If compiled with USE_INT64 and USE_ADDR64, RQ and TQ controllers support files > 2GB. - VAX ROM has speed control (SET ROM DELAY/NODELAY). 2. Bugs Fixed in 3.01-0 2.1 VAX - Fixed CVTfi bug: integer overflow not set if exponent out of range - Fixed EMODx bugs: o First and second operands reversed o Separated fraction received wrong exponent o Overflow calculation on separated integer incorrect o Fraction not set to zero if exponent out of range - Fixed interval timer and ROM access to pass power-up self-test even on very fast host processors (fixes from Mark Pizzolato). 2.2 1401 - Fixed mnemonic, instruction lengths, and reverse scan length check bug for MCS. - Fixed MCE bug, BS off by 1 if zero suppress. - Fixed chaining bug, D lost if return to SCP. - Fixed H branch, branch occurs after continue. - Added check for invalid 8 character MCW, LCA. - Fixed magtape load-mode end of record response. 2.3 Nova - Fixed DSK variable size interaction with restore. 2.4 PDP-1 - Fixed DT variable size interaction with restore. 2.5 PDP-11 - Fixed DT variable size interaction with restore. - Fixed bug in MMR1 update (found by Tim Stark). - Added XQ features and fixed bugs: o Corrected XQ interrupts on IE state transition (code by Tom Evans). o Added XQ interrupt clear on soft reset. o Removed XQ interrupt when setting XL or RL (multiple people). o Added SET/SHOW XQ STATS. o Added SHOW XQ FILTERS. o Added ability to split received packet into multiple buffers. o Added explicit runt and giant packet processing. 2.6 PDP-18B - Fixed DT, RF variable size interaction with restore. - Fixed MT bug in MTTR. 2.7 PDP-8 - Fixed DT, DF, RF, RX variable size interaction with restore. - Fixed MT bug in SKTR. 2.8 HP2100 - Fixed bug in DP (13210A controller only), DQ read status. - Fixed bug in DP, DQ seek complete. 2.9 GRI - Fixed bug in SC queue pointer management. 3. New Features in 3.0 vs prior releases N/A 4. Bugs Fixed in 3.0 vs prior releases N/A 5. General Notes WARNING: The RESTORE command has changed. RESTORE will now detach an attached file on a unit, if that unit did not have an attached file in the saved configuration. This is required to assure that the unit flags and the file state are consistent. WARNING: The compilation scheme for the PDP-10, PDP-11, and VAX has changed. Use one of the supplied build files, or read the documentation carefully, before compiling any of these simulators.
1145 lines
35 KiB
C
1145 lines
35 KiB
C
/* pdp8_cpu.c: PDP-8 CPU simulator
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Copyright (c) 1993-2003, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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cpu central processor
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12-Mar-03 RMS Added logical name support
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04-Oct-02 RMS Revamped device dispatching, added device number support
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06-Jan-02 RMS Added device enable/disable routines
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30-Dec-01 RMS Added old PC queue
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16-Dec-01 RMS Fixed bugs in EAE
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07-Dec-01 RMS Revised to use new breakpoint package
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30-Nov-01 RMS Added RL8A, extended SET/SHOW support
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16-Sep-01 RMS Fixed bug in reset routine, added KL8A support
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10-Aug-01 RMS Removed register from declarations
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17-Jul-01 RMS Moved function prototype
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07-Jun-01 RMS Fixed bug in JMS to non-existent memory
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25-Apr-01 RMS Added device enable/disable support
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18-Mar-01 RMS Added DF32 support
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05-Mar-01 RMS Added clock calibration support
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15-Feb-01 RMS Added DECtape support
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14-Apr-99 RMS Changed t_addr to unsigned
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The register state for the PDP-8 is:
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AC<0:11> accumulator
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MQ<0:11> multiplier-quotient
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L link flag
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PC<0:11> program counter
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IF<0:2> instruction field
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IB<0:2> instruction buffer
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DF<0:2> data field
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UF user flag
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UB user buffer
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SF<0:6> interrupt save field
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The PDP-8 has three instruction formats: memory reference, I/O transfer,
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and operate. The memory reference format is:
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0 1 2 3 4 5 6 7 8 9 10 11
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+--+--+--+--+--+--+--+--+--+--+--+--+
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| op |in|zr| page offset | memory reference
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+--+--+--+--+--+--+--+--+--+--+--+--+
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<0:2> mnemonic action
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000 AND AC = AC & M[MA]
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001 TAD L'AC = AC + M[MA]
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010 DCA M[MA] = AC, AC = 0
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011 ISZ M[MA] = M[MA] + 1, skip if M[MA] == 0
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100 JMS M[MA] = PC, PC = MA + 1
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101 JMP PC = MA
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<3:4> mode action
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00 page zero MA = IF'0'IR<5:11>
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01 current page MA = IF'PC<0:4>'IR<5:11>
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10 indirect page zero MA = xF'M[IF'0'IR<5:11>]
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11 indirect current page MA = xF'M[IF'PC<0:4>'IR<5:11>]
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where x is D for AND, TAD, ISZ, DCA, and I for JMS, JMP.
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Memory reference instructions can access an address space of 32K words.
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The address space is divided into eight 4K word fields; each field is
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divided into thirty-two 128 word pages. An instruction can directly
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address, via its 7b offset, locations 0-127 on page zero or on the current
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page. All 32k words can be accessed via indirect addressing and the
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instruction and data field registers. If an indirect address is in
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locations 0010-0017 of any field, the indirect address is incremented
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and rewritten to memory before use.
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*/
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/* The I/O transfer format is as follows:
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0 1 2 3 4 5 6 7 8 9 10 11
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+--+--+--+--+--+--+--+--+--+--+--+--+
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| op | device | pulse | I/O transfer
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+--+--+--+--+--+--+--+--+--+--+--+--+
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The IO transfer instruction sends the the specified pulse to the
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specified I/O device. The I/O device may take data from the AC,
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return data to the AC, initiate or cancel operations, or skip on
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status.
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The operate format is as follows:
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+--+--+--+--+--+--+--+--+--+--+--+--+
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| 1| 1| 1| 0| | | | | | | | | operate group 1
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+--+--+--+--+--+--+--+--+--+--+--+--+
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| | | | | | | |
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| | | | | | | +--- increment AC 3
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| | | | | | +--- rotate 1 or 2 4
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| | | | | +--- rotate left 4
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| | | | +--- rotate right 4
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| | | +--- complement L 2
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| | +--- complement AC 2
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| +--- clear L 1
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+-- clear AC 1
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+--+--+--+--+--+--+--+--+--+--+--+--+
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| 1| 1| 1| 1| | | | | | | | 0| operate group 2
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+--+--+--+--+--+--+--+--+--+--+--+--+
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| | | | | | |
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| | | | | | +--- halt 3
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| | | | | +--- or switch register 3
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| | | | +--- reverse skip sense 1
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| | | +--- skip on L != 0 1
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| | +--- skip on AC == 0 1
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| +--- skip on AC < 0 1
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+-- clear AC 2
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+--+--+--+--+--+--+--+--+--+--+--+--+
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| 1| 1| 1| 1| | | | | | | | 1| operate group 3
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+--+--+--+--+--+--+--+--+--+--+--+--+
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| | | | \______/
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| | | | |
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| | +--|-----+--- EAE command 3
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| | +--- AC -> MQ, 0 -> AC 2
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| +--- MQ v AC --> AC 2
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+-- clear AC 1
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The operate instruction can be microprogrammed to perform operations
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on the AC, MQ, and link.
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*/
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/* This routine is the instruction decode routine for the PDP-8.
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It is called from the simulator control program to execute
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instructions in simulated memory, starting at the simulated PC.
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It runs until 'reason' is set non-zero.
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General notes:
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1. Reasons to stop. The simulator can be stopped by:
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HALT instruction
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breakpoint encountered
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unimplemented instruction and stop_inst flag set
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I/O error in I/O simulator
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2. Interrupts. Interrupts are maintained by three parallel variables:
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dev_done device done flags
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int_enable interrupt enable flags
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int_req interrupt requests
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In addition, int_req contains the interrupt enable flag, the
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CIF not pending flag, and the ION not pending flag. If all
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three of these flags are set, and at least one interrupt request
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is set, then an interrupt occurs.
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3. Non-existent memory. On the PDP-8, reads to non-existent memory
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return zero, and writes are ignored. In the simulator, the
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largest possible memory is instantiated and initialized to zero.
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Thus, only writes outside the current field (indirect writes) need
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be checked against actual memory size.
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3. Adding I/O devices. These modules must be modified:
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pdp8_defs.h add device number and interrupt definitions
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pdp8_sys.c add sim_devices table entry
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*/
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#include "pdp8_defs.h"
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#define PCQ_SIZE 64 /* must be 2**n */
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#define PCQ_MASK (PCQ_SIZE - 1)
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#define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = PC
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#define UNIT_V_NOEAE (UNIT_V_UF) /* EAE absent */
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#define UNIT_NOEAE (1 << UNIT_V_NOEAE)
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#define UNIT_V_MSIZE (UNIT_V_UF+1) /* dummy mask */
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#define UNIT_MSIZE (1 << UNIT_V_MSIZE)
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uint16 M[MAXMEMSIZE] = { 0 }; /* main memory */
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int32 saved_LAC = 0; /* saved L'AC */
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int32 saved_MQ = 0; /* saved MQ */
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int32 saved_PC = 0; /* saved IF'PC */
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int32 saved_DF = 0; /* saved Data Field */
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int32 IB = 0; /* Instruction Buffer */
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int32 SF = 0; /* Save Field */
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int32 emode = 0; /* EAE mode */
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int32 gtf = 0; /* EAE gtf flag */
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int32 SC = 0; /* EAE shift count */
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int32 UB = 0; /* User mode Buffer */
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int32 UF = 0; /* User mode Flag */
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int32 OSR = 0; /* Switch Register */
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int16 pcq[PCQ_SIZE] = { 0 }; /* PC queue */
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int32 pcq_p = 0; /* PC queue ptr */
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REG *pcq_r = NULL; /* PC queue reg ptr */
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int32 dev_done = 0; /* dev done flags */
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int32 int_enable = INT_INIT_ENABLE; /* intr enables */
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int32 int_req = 0; /* intr requests */
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int32 stop_inst = 0; /* trap on ill inst */
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int32 (*dev_tab[DEV_MAX])(int32 IR, int32 dat); /* device dispatch */
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extern int32 sim_interval;
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extern int32 sim_int_char;
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extern int32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
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extern DEVICE *sim_devices[];
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extern FILE *sim_log;
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extern UNIT clk_unit, ttix_unit;
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t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
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t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
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t_stat cpu_reset (DEVICE *dptr);
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t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_bool build_dev_tab (void);
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/* CPU data structures
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cpu_dev CPU device descriptor
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cpu_unit CPU unit descriptor
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cpu_reg CPU register list
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cpu_mod CPU modifier list
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*/
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UNIT cpu_unit = { UDATA (NULL, UNIT_FIX + UNIT_BINK, MAXMEMSIZE) };
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REG cpu_reg[] = {
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{ ORDATA (PC, saved_PC, 15) },
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{ ORDATA (AC, saved_LAC, 12) },
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{ FLDATA (L, saved_LAC, 12) },
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{ ORDATA (MQ, saved_MQ, 12) },
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{ ORDATA (SR, OSR, 12) },
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{ GRDATA (IF, saved_PC, 8, 3, 12) },
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{ GRDATA (DF, saved_DF, 8, 3, 12) },
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{ GRDATA (IB, IB, 8, 3, 12) },
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{ ORDATA (SF, SF, 7) },
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{ FLDATA (UB, UB, 0) },
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{ FLDATA (UF, UF, 0) },
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{ ORDATA (SC, SC, 5) },
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{ FLDATA (GTF, gtf, 0) },
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{ FLDATA (EMODE, emode, 0) },
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{ FLDATA (ION, int_req, INT_V_ION) },
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{ FLDATA (ION_DELAY, int_req, INT_V_NO_ION_PENDING) },
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{ FLDATA (CIF_DELAY, int_req, INT_V_NO_CIF_PENDING) },
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{ FLDATA (PWR_INT, int_req, INT_V_PWR) },
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{ FLDATA (UF_INT, int_req, INT_V_UF) },
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{ ORDATA (INT, int_req, INT_V_ION+1), REG_RO },
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{ ORDATA (DONE, dev_done, INT_V_DIRECT), REG_RO },
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{ ORDATA (ENABLE, int_enable, INT_V_DIRECT), REG_RO },
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{ BRDATA (PCQ, pcq, 8, 15, PCQ_SIZE), REG_RO+REG_CIRC },
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{ ORDATA (PCQP, pcq_p, 6), REG_HRO },
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{ FLDATA (STOP_INST, stop_inst, 0) },
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{ ORDATA (WRU, sim_int_char, 8) },
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{ NULL } };
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MTAB cpu_mod[] = {
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{ UNIT_NOEAE, UNIT_NOEAE, "no EAE", "NOEAE", NULL },
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{ UNIT_NOEAE, 0, "EAE", "EAE", NULL },
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{ UNIT_MSIZE, 4096, NULL, "4K", &cpu_set_size },
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{ UNIT_MSIZE, 8192, NULL, "8K", &cpu_set_size },
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{ UNIT_MSIZE, 12288, NULL, "12K", &cpu_set_size },
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{ UNIT_MSIZE, 16384, NULL, "16K", &cpu_set_size },
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{ UNIT_MSIZE, 20480, NULL, "20K", &cpu_set_size },
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{ UNIT_MSIZE, 24576, NULL, "24K", &cpu_set_size },
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{ UNIT_MSIZE, 28672, NULL, "28K", &cpu_set_size },
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{ UNIT_MSIZE, 32768, NULL, "32K", &cpu_set_size },
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{ 0 } };
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DEVICE cpu_dev = {
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"CPU", &cpu_unit, cpu_reg, cpu_mod,
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1, 8, 15, 1, 8, 12,
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&cpu_ex, &cpu_dep, &cpu_reset,
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NULL, NULL, NULL,
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NULL, 0 };
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t_stat sim_instr (void)
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{
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int32 IR, MB, IF, DF, LAC, MQ;
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uint32 PC, MA;
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int32 device, pulse, temp, iot_data;
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t_stat reason;
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/* Restore register state */
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if (build_dev_tab ()) return SCPE_STOP; /* build dev_tab */
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PC = saved_PC & 007777; /* load local copies */
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IF = saved_PC & 070000;
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DF = saved_DF & 070000;
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LAC = saved_LAC & 017777;
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MQ = saved_MQ & 07777;
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int_req = INT_UPDATE;
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reason = 0;
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sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init clk calib */
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sim_rtcn_init (ttix_unit.wait, TMR_TTX); /* init ttx calib */
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/* Main instruction fetch/decode loop */
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while (reason == 0) { /* loop until halted */
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if (sim_interval <= 0) { /* check clock queue */
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if (reason = sim_process_event ()) break; }
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if (int_req > INT_PENDING) { /* interrupt? */
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int_req = int_req & ~INT_ION; /* interrupts off */
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SF = (UF << 6) | (IF >> 9) | (DF >> 12); /* form save field */
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IF = IB = DF = UF = UB = 0; /* clear mem ext */
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PCQ_ENTRY; /* save old PC */
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M[0] = PC; /* save PC in 0 */
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PC = 1; } /* fetch next from 1 */
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MA = IF | PC; /* form PC */
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if (sim_brk_summ && sim_brk_test (MA, SWMASK ('E'))) { /* breakpoint? */
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reason = STOP_IBKPT; /* stop simulation */
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break; }
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IR = M[MA]; /* fetch instruction */
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PC = (PC + 1) & 07777; /* increment PC */
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int_req = int_req | INT_NO_ION_PENDING; /* clear ION delay */
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sim_interval = sim_interval - 1;
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/* Instruction decoding.
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The opcode (IR<0:2>), indirect flag (IR<3>), and page flag (IR<4>)
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are decoded together. This produces 32 decode points, four per
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major opcode. For IOT, the extra decode points are not useful;
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for OPR, only the group flag (IR<3>) is used.
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The following macros define the address calculations for data and
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jump calculations. Data calculations return a full 15b extended
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address, jump calculations a 12b field-relative address.
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Autoindex calculations always occur within the same field as the
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instruction fetch. The field must exist; otherwise, the instruction
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fetched would be 0000, and indirect addressing could not occur.
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Note that MA contains IF'PC.
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*/
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#define ZERO_PAGE MA = IF | (IR & 0177)
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#define CURR_PAGE MA = (MA & 077600) | (IR & 0177)
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#define INDIRECT if ((MA & 07770) != 00010) MA = DF | M[MA]; \
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else MA = DF | (M[MA] = (M[MA] + 1) & 07777)
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#define ZERO_PAGE_J MA = IR & 0177
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#define CURR_PAGE_J MA = (MA & 007600) | (IR & 0177)
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#define INDIRECT_J if ((MA & 07770) != 00010) MA = M[MA]; \
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else MA = (M[MA] = (M[MA] + 1) & 07777)
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#define CHANGE_FIELD IF = IB; UF = UB; \
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int_req = int_req | INT_NO_CIF_PENDING
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switch ((IR >> 7) & 037) { /* decode IR<0:4> */
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/* Opcode 0, AND */
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case 000: /* AND, dir, zero */
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ZERO_PAGE;
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LAC = LAC & (M[MA] | 010000);
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break;
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case 001: /* AND, dir, curr */
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CURR_PAGE;
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LAC = LAC & (M[MA] | 010000);
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break;
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case 002: /* AND, indir, zero */
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ZERO_PAGE;
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INDIRECT;
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LAC = LAC & (M[MA] | 010000);
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break;
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case 003: /* AND, indir, curr */
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CURR_PAGE;
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INDIRECT;
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LAC = LAC & (M[MA] | 010000);
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break;
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/* Opcode 1, TAD */
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case 004: /* TAD, dir, zero */
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ZERO_PAGE;
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LAC = (LAC + M[MA]) & 017777;
|
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break;
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case 005: /* TAD, dir, curr */
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||
CURR_PAGE;
|
||
LAC = (LAC + M[MA]) & 017777;
|
||
break;
|
||
case 006: /* TAD, indir, zero */
|
||
ZERO_PAGE;
|
||
INDIRECT;
|
||
LAC = (LAC + M[MA]) & 017777;
|
||
break;
|
||
case 007: /* TAD, indir, curr */
|
||
CURR_PAGE;
|
||
INDIRECT;
|
||
LAC = (LAC + M[MA]) & 017777;
|
||
break;
|
||
|
||
/* Opcode 2, ISZ */
|
||
|
||
case 010: /* ISZ, dir, zero */
|
||
ZERO_PAGE;
|
||
M[MA] = MB = (M[MA] + 1) & 07777; /* field must exist */
|
||
if (MB == 0) PC = (PC + 1) & 07777;
|
||
break;
|
||
case 011: /* ISZ, dir, curr */
|
||
CURR_PAGE;
|
||
M[MA] = MB = (M[MA] + 1) & 07777; /* field must exist */
|
||
if (MB == 0) PC = (PC + 1) & 07777;
|
||
break;
|
||
case 012: /* ISZ, indir, zero */
|
||
ZERO_PAGE;
|
||
INDIRECT;
|
||
MB = (M[MA] + 1) & 07777;
|
||
if (MEM_ADDR_OK (MA)) M[MA] = MB;
|
||
if (MB == 0) PC = (PC + 1) & 07777;
|
||
break;
|
||
case 013: /* ISZ, indir, curr */
|
||
CURR_PAGE;
|
||
INDIRECT;
|
||
MB = (M[MA] + 1) & 07777;
|
||
if (MEM_ADDR_OK (MA)) M[MA] = MB;
|
||
if (MB == 0) PC = (PC + 1) & 07777;
|
||
break;
|
||
|
||
/* Opcode 3, DCA */
|
||
|
||
case 014: /* DCA, dir, zero */
|
||
ZERO_PAGE;
|
||
M[MA] = LAC & 07777;
|
||
LAC = LAC & 010000;
|
||
break;
|
||
case 015: /* DCA, dir, curr */
|
||
CURR_PAGE;
|
||
M[MA] = LAC & 07777;
|
||
LAC = LAC & 010000;
|
||
break;
|
||
case 016: /* DCA, indir, zero */
|
||
ZERO_PAGE;
|
||
INDIRECT;
|
||
if (MEM_ADDR_OK (MA)) M[MA] = LAC & 07777;
|
||
LAC = LAC & 010000;
|
||
break;
|
||
case 017: /* DCA, indir, curr */
|
||
CURR_PAGE;
|
||
INDIRECT;
|
||
if (MEM_ADDR_OK (MA)) M[MA] = LAC & 07777;
|
||
LAC = LAC & 010000;
|
||
break;
|
||
|
||
/* Opcode 4, JMS */
|
||
|
||
case 020: /* JMS, dir, zero */
|
||
ZERO_PAGE_J;
|
||
CHANGE_FIELD;
|
||
MA = IF | MA;
|
||
PCQ_ENTRY;
|
||
if (MEM_ADDR_OK (MA)) M[MA] = PC;
|
||
PC = (MA + 1) & 07777;
|
||
break;
|
||
case 021: /* JMS, dir, curr */
|
||
CURR_PAGE_J;
|
||
CHANGE_FIELD;
|
||
MA = IF | MA;
|
||
PCQ_ENTRY;
|
||
if (MEM_ADDR_OK (MA)) M[MA] = PC;
|
||
PC = (MA + 1) & 07777;
|
||
break;
|
||
case 022: /* JMS, indir, zero */
|
||
ZERO_PAGE;
|
||
INDIRECT_J;
|
||
CHANGE_FIELD;
|
||
MA = IF | MA;
|
||
PCQ_ENTRY;
|
||
if (MEM_ADDR_OK (MA)) M[MA] = PC;
|
||
PC = (MA + 1) & 07777;
|
||
break;
|
||
case 023: /* JMS, indir, curr */
|
||
CURR_PAGE;
|
||
INDIRECT_J;
|
||
CHANGE_FIELD;
|
||
MA = IF | MA;
|
||
PCQ_ENTRY;
|
||
if (MEM_ADDR_OK (MA)) M[MA] = PC;
|
||
PC = (MA + 1) & 07777;
|
||
break;
|
||
|
||
/* Opcode 5, JMP */
|
||
|
||
case 024: /* JMP, dir, zero */
|
||
ZERO_PAGE_J;
|
||
CHANGE_FIELD;
|
||
PCQ_ENTRY;
|
||
PC = MA;
|
||
break;
|
||
case 025: /* JMP, dir, curr */
|
||
CURR_PAGE_J;
|
||
CHANGE_FIELD;
|
||
PCQ_ENTRY;
|
||
PC = MA;
|
||
break;
|
||
case 026: /* JMP, indir, zero */
|
||
ZERO_PAGE;
|
||
INDIRECT_J;
|
||
CHANGE_FIELD;
|
||
PCQ_ENTRY;
|
||
PC = MA;
|
||
break;
|
||
case 027: /* JMP, indir, curr */
|
||
CURR_PAGE;
|
||
INDIRECT_J;
|
||
CHANGE_FIELD;
|
||
PCQ_ENTRY;
|
||
PC = MA;
|
||
break;
|
||
|
||
/* Opcode 7, OPR group 1 */
|
||
|
||
case 034:case 035: /* OPR, group 1 */
|
||
switch ((IR >> 4) & 017) { /* decode IR<4:7> */
|
||
case 0: /* nop */
|
||
break;
|
||
case 1: /* CML */
|
||
LAC = LAC ^ 010000;
|
||
break;
|
||
case 2: /* CMA */
|
||
LAC = LAC ^ 07777;
|
||
break;
|
||
case 3: /* CMA CML */
|
||
LAC = LAC ^ 017777;
|
||
break;
|
||
case 4: /* CLL */
|
||
LAC = LAC & 07777;
|
||
break;
|
||
case 5: /* CLL CML = STL */
|
||
LAC = LAC | 010000;
|
||
break;
|
||
case 6: /* CLL CMA */
|
||
LAC = (LAC ^ 07777) & 07777;
|
||
break;
|
||
case 7: /* CLL CMA CML */
|
||
LAC = (LAC ^ 07777) | 010000;
|
||
break;
|
||
case 010: /* CLA */
|
||
LAC = LAC & 010000;
|
||
break;
|
||
case 011: /* CLA CML */
|
||
LAC = (LAC & 010000) ^ 010000;
|
||
break;
|
||
case 012: /* CLA CMA = STA */
|
||
LAC = LAC | 07777;
|
||
break;
|
||
case 013: /* CLA CMA CML */
|
||
LAC = (LAC | 07777) ^ 010000;
|
||
break;
|
||
case 014: /* CLA CLL */
|
||
LAC = 0;
|
||
break;
|
||
case 015: /* CLA CLL CML */
|
||
LAC = 010000;
|
||
break;
|
||
case 016: /* CLA CLL CMA */
|
||
LAC = 07777;
|
||
break;
|
||
case 017: /* CLA CLL CMA CML */
|
||
LAC = 017777;
|
||
break; } /* end switch opers */
|
||
|
||
/* OPR group 1, continued */
|
||
|
||
if (IR & 01) LAC = (LAC + 1) & 017777; /* IAC */
|
||
switch ((IR >> 1) & 07) { /* decode IR<8:10> */
|
||
case 0: /* nop */
|
||
break;
|
||
case 1: /* BSW */
|
||
LAC = (LAC & 010000) | ((LAC >> 6) & 077) | ((LAC & 077) << 6);
|
||
break;
|
||
case 2: /* RAL */
|
||
LAC = ((LAC << 1) | (LAC >> 12)) & 017777;
|
||
break;
|
||
case 3: /* RTL */
|
||
LAC = ((LAC << 2) | (LAC >> 11)) & 017777;
|
||
break;
|
||
case 4: /* RAR */
|
||
LAC = ((LAC >> 1) | (LAC << 12)) & 017777;
|
||
break;
|
||
case 5: /* RTR */
|
||
LAC = ((LAC >> 2) | (LAC << 11)) & 017777;
|
||
break;
|
||
case 6: /* RAL RAR - undef */
|
||
LAC = LAC & (IR | 010000); /* uses AND path */
|
||
break;
|
||
case 7: /* RTL RTR - undef */
|
||
LAC = (LAC & 010000) | (MA & 07600) | (IR & 0177);
|
||
break; } /* uses address path */
|
||
break; /* end group 1 */
|
||
|
||
/* OPR group 2 */
|
||
|
||
case 036:case 037: /* OPR, groups 2, 3 */
|
||
if ((IR & 01) == 0) { /* group 2 */
|
||
switch ((IR >> 3) & 017) { /* decode IR<6:8> */
|
||
case 0: /* nop */
|
||
break;
|
||
case 1: /* SKP */
|
||
PC = (PC + 1) & 07777;
|
||
break;
|
||
case 2: /* SNL */
|
||
if (LAC >= 010000) PC = (PC + 1) & 07777;
|
||
break;
|
||
case 3: /* SZL */
|
||
if (LAC < 010000) PC = (PC + 1) & 07777;
|
||
break;
|
||
case 4: /* SZA */
|
||
if ((LAC & 07777) == 0) PC = (PC + 1) & 07777;
|
||
break;
|
||
case 5: /* SNA */
|
||
if ((LAC & 07777) != 0) PC = (PC + 1) & 07777;
|
||
break;
|
||
case 6: /* SZA | SNL */
|
||
if ((LAC == 0) || (LAC >= 010000))
|
||
PC = (PC + 1) & 07777;
|
||
break;
|
||
case 7: /* SNA & SZL */
|
||
if ((LAC != 0) && (LAC < 010000)) PC = (PC + 1) & 07777;
|
||
break;
|
||
case 010: /* SMA */
|
||
if ((LAC & 04000) != 0) PC = (PC + 1) & 07777;
|
||
break;
|
||
case 011: /* SPA */
|
||
if ((LAC & 04000) == 0) PC = (PC + 1) & 07777;
|
||
break;
|
||
case 012: /* SMA | SNL */
|
||
if (LAC >= 04000) PC = (PC + 1) & 07777;
|
||
break;
|
||
case 013: /* SPA & SZL */
|
||
if (LAC < 04000) PC = (PC + 1) & 07777;
|
||
break;
|
||
case 014: /* SMA | SZA */
|
||
if (((LAC & 04000) != 0) || ((LAC & 07777) == 0))
|
||
PC = (PC + 1) & 07777;
|
||
break;
|
||
case 015: /* SPA & SNA */
|
||
if (((LAC & 04000) == 0) && ((LAC & 07777) != 0))
|
||
PC = (PC + 1) & 07777;
|
||
break;
|
||
case 016: /* SMA | SZA | SNL */
|
||
if ((LAC >= 04000) || (LAC == 0)) PC = (PC + 1) & 07777;
|
||
break;
|
||
case 017: /* SPA & SNA & SZL */
|
||
if ((LAC < 04000) && (LAC != 0)) PC = (PC + 1) & 07777;
|
||
break; } /* end switch skips */
|
||
if (IR & 0200) LAC = LAC & 010000; /* CLA */
|
||
if ((IR & 06) && UF) int_req = int_req | INT_UF;
|
||
else {
|
||
if (IR & 04) LAC = LAC | OSR; /* OSR */
|
||
if (IR & 02) reason = STOP_HALT; } /* HLT */
|
||
break; } /* end group 2 */
|
||
|
||
/* OPR group 3 standard
|
||
|
||
MQA!MQL exchanges AC and MQ, as follows:
|
||
|
||
temp = MQ;
|
||
MQ = LAC & 07777;
|
||
LAC = LAC & 010000 | temp;
|
||
*/
|
||
|
||
temp = MQ; /* group 3 */
|
||
if (IR & 0200) LAC = LAC & 010000; /* CLA */
|
||
if (IR & 0020) { /* MQL */
|
||
MQ = LAC & 07777;
|
||
LAC = LAC & 010000; }
|
||
if (IR & 0100) LAC = LAC | temp; /* MQA */
|
||
if ((IR & 0056) && (cpu_unit.flags & UNIT_NOEAE)) {
|
||
reason = stop_inst; /* EAE not present */
|
||
break; }
|
||
|
||
/* OPR group 3 EAE
|
||
|
||
The EAE operates in two modes:
|
||
|
||
Mode A, PDP-8/I compatible
|
||
Mode B, extended capability
|
||
|
||
Mode B provides eight additional subfunctions; in addition, some
|
||
of the Mode A functions operate differently in Mode B.
|
||
|
||
The mode switch instructions are decoded explicitly and cannot be
|
||
microprogrammed with other EAE functions (SWAB performs an MQL as
|
||
part of standard group 3 decoding). If mode switching is decoded,
|
||
all other EAE timing is suppressed.
|
||
*/
|
||
|
||
if (IR == 07431) { /* SWAB */
|
||
emode = 1; /* set mode flag */
|
||
break; }
|
||
if (IR == 07447) { /* SWBA */
|
||
emode = gtf = 0; /* clear mode, gtf */
|
||
break; }
|
||
|
||
/* If not switching modes, the EAE operation is determined by the mode
|
||
and IR<6,8:10>:
|
||
|
||
<6:10> mode A mode B comments
|
||
|
||
0x000 NOP NOP
|
||
0x001 SCL ACS
|
||
0x010 MUY MUY if mode B, next = address
|
||
0x011 DVI DVI if mode B, next = address
|
||
0x100 NMI NMI if mode B, clear AC if
|
||
result = 4000'0000
|
||
0x101 SHL SHL if mode A, extra shift
|
||
0x110 ASR ASR if mode A, extra shift
|
||
0x111 LSR LSR if mode A, extra shift
|
||
1x000 SCA SCA
|
||
1x001 SCA + SCL DAD
|
||
1x010 SCA + MUY DST
|
||
1x011 SCA + DVI SWBA NOP if not detected earlier
|
||
1x100 SCA + NMI DPSZ
|
||
1x101 SCA + SHL DPIC must be combined with MQA!MQL
|
||
1x110 SCA + ASR DCM must be combined with MQA!MQL
|
||
1x111 SCA + LSR SAM
|
||
|
||
EAE instructions which fetch memory operands use the CPU's DEFER
|
||
state to read the first word; if the address operand is in locations
|
||
x0010 - x0017, it is autoincremented.
|
||
*/
|
||
|
||
/* EAE continued */
|
||
|
||
if (emode == 0) gtf = 0; /* mode A? clr gtf */
|
||
switch ((IR >> 1) & 027) { /* decode IR<6,8:10> */
|
||
case 020: /* mode A, B: SCA */
|
||
LAC = LAC | SC;
|
||
break;
|
||
case 000: /* mode A, B: NOP */
|
||
break;
|
||
case 021: /* mode B: DAD */
|
||
if (emode) {
|
||
MA = IF | PC;
|
||
INDIRECT; /* defer state */
|
||
MQ = MQ + M[MA];
|
||
MA = DF | ((MA + 1) & 07777);
|
||
LAC = (LAC & 07777) + M[MA] + (MQ >> 12);
|
||
MQ = MQ & 07777;
|
||
PC = (PC + 1) & 07777;
|
||
break; }
|
||
LAC = LAC | SC; /* mode A: SCA then */
|
||
case 001: /* mode B: ACS */
|
||
if (emode) {
|
||
SC = LAC & 037;
|
||
LAC = LAC & 010000; }
|
||
else { /* mode A: SCL */
|
||
SC = (~M[IF | PC]) & 037;
|
||
PC = (PC + 1) & 07777; }
|
||
break;
|
||
case 022: /* mode B: DST */
|
||
if (emode) {
|
||
MA = IF | PC;
|
||
INDIRECT; /* defer state */
|
||
if (MEM_ADDR_OK (MA)) M[MA] = MQ & 07777;
|
||
MA = DF | ((MA + 1) & 07777);
|
||
if (MEM_ADDR_OK (MA)) M[MA] = LAC & 07777;
|
||
PC = (PC + 1) & 07777;
|
||
break; }
|
||
LAC = LAC | SC; /* mode A: SCA then */
|
||
case 002: /* MUY */
|
||
MA = IF | PC;
|
||
if (emode) { INDIRECT; } /* mode B: defer */
|
||
temp = (MQ * M[MA]) + (LAC & 07777);
|
||
LAC = (temp >> 12) & 07777;
|
||
MQ = temp & 07777;
|
||
PC = (PC + 1) & 07777;
|
||
SC = 014; /* 12 shifts */
|
||
break;
|
||
|
||
/* EAE continued */
|
||
|
||
case 023: /* mode B: SWBA */
|
||
if (emode) break;
|
||
LAC = LAC | SC; /* mode A: SCA then */
|
||
case 003: /* DVI */
|
||
MA = IF | PC;
|
||
if (emode) { INDIRECT; } /* mode B: defer */
|
||
if ((LAC & 07777) >= M[MA]) { /* overflow? */
|
||
LAC = LAC | 010000; /* set link */
|
||
MQ = ((MQ << 1) + 1) & 07777; /* rotate MQ */
|
||
SC = 01; } /* 1 shift */
|
||
else {
|
||
temp = ((LAC & 07777) << 12) | MQ;
|
||
MQ = temp / M[MA];
|
||
LAC = temp % M[MA];
|
||
SC = 015; } /* 13 shifts */
|
||
PC = (PC + 1) & 07777;
|
||
break;
|
||
case 024: /* mode B: DPSZ */
|
||
if (emode) {
|
||
if (((LAC | MQ) & 07777) == 0) PC = (PC + 1) & 07777;
|
||
break; }
|
||
LAC = LAC | SC; /* mode A: SCA then */
|
||
case 004: /* NMI */
|
||
temp = (LAC << 12) | MQ; /* preserve link */
|
||
for (SC = 0; ((temp & 017777777) != 0) &&
|
||
(temp & 040000000) == ((temp << 1) & 040000000); SC++)
|
||
temp = temp << 1;
|
||
LAC = (temp >> 12) & 017777;
|
||
MQ = temp & 07777;
|
||
if (emode && ((LAC & 07777) == 04000) && (MQ == 0))
|
||
LAC = LAC & 010000; /* clr if 4000'0000 */
|
||
break;
|
||
case 025: /* mode B: DPIC */
|
||
if (emode) {
|
||
temp = (LAC + 1) & 07777; /* SWP already done! */
|
||
LAC = MQ + (temp == 0);
|
||
MQ = temp;
|
||
break; }
|
||
LAC = LAC | SC; /* mode A: SCA then */
|
||
case 5: /* SHL */
|
||
SC = (M[IF | PC] & 037) + (emode ^ 1); /* shift+1 if mode A */
|
||
if (SC > 25) temp = 0; /* >25? result = 0 */
|
||
else temp = ((LAC << 12) | MQ) << SC; /* <=25? shift LAC:MQ */
|
||
LAC = (temp >> 12) & 017777;
|
||
MQ = temp & 07777;
|
||
PC = (PC + 1) & 07777;
|
||
SC = emode? 037: 0; /* SC = 0 if mode A */
|
||
break;
|
||
|
||
/* EAE continued */
|
||
|
||
case 026: /* mode B: DCM */
|
||
if (emode) {
|
||
temp = (-LAC) & 07777; /* SWP already done! */
|
||
LAC = (MQ ^ 07777) + (temp == 0);
|
||
MQ = temp;
|
||
break; }
|
||
LAC = LAC | SC; /* mode A: SCA then */
|
||
case 6: /* ASR */
|
||
SC = (M[IF | PC] & 037) + (emode ^ 1); /* shift+1 if mode A */
|
||
temp = ((LAC & 07777) << 12) | MQ; /* sext from AC0 */
|
||
if (LAC & 04000) temp = temp | ~037777777;
|
||
if (emode && (SC != 0)) gtf = (temp >> (SC - 1)) & 1;
|
||
if (SC > 25) temp = (LAC & 04000)? -1: 0;
|
||
else temp = temp >> SC;
|
||
LAC = (temp >> 12) & 017777;
|
||
MQ = temp & 07777;
|
||
PC = (PC + 1) & 07777;
|
||
SC = emode? 037: 0; /* SC = 0 if mode A */
|
||
break;
|
||
case 027: /* mode B: SAM */
|
||
if (emode) {
|
||
temp = LAC & 07777;
|
||
LAC = MQ + (temp ^ 07777) + 1; /* L'AC = MQ - AC */
|
||
gtf = (temp <= MQ) ^ ((temp ^ MQ) >> 11);
|
||
break; }
|
||
LAC = LAC | SC; /* mode A: SCA then */
|
||
case 7: /* LSR */
|
||
SC = (M[IF | PC] & 037) + (emode ^ 1); /* shift+1 if mode A */
|
||
temp = ((LAC & 07777) << 12) | MQ; /* clear link */
|
||
if (emode && (SC != 0)) gtf = (temp >> (SC - 1)) & 1;
|
||
if (SC > 24) temp = 0; /* >24? result = 0 */
|
||
else temp = temp >> SC; /* <=24? shift AC:MQ */
|
||
LAC = (temp >> 12) & 07777;
|
||
MQ = temp & 07777;
|
||
PC = (PC + 1) & 07777;
|
||
SC = emode? 037: 0; /* SC = 0 if mode A */
|
||
break; } /* end switch */
|
||
break; /* end case 7 */
|
||
|
||
/* Opcode 6, IOT */
|
||
|
||
case 030:case 031:case 032:case 033: /* IOT */
|
||
if (UF) { /* privileged? */
|
||
int_req = int_req | INT_UF;
|
||
break; }
|
||
device = (IR >> 3) & 077; /* device = IR<3:8> */
|
||
pulse = IR & 07; /* pulse = IR<9:11> */
|
||
iot_data = LAC & 07777; /* AC unchanged */
|
||
switch (device) { /* decode IR<3:8> */
|
||
case 0: /* CPU control */
|
||
switch (pulse) { /* decode IR<9:11> */
|
||
case 0: /* SKON */
|
||
if (int_req & INT_ION) PC = (PC + 1) & 07777;
|
||
int_req = int_req & ~INT_ION;
|
||
break;
|
||
case 1: /* ION */
|
||
int_req = (int_req | INT_ION) & ~INT_NO_ION_PENDING;
|
||
break;
|
||
case 2: /* IOF */
|
||
int_req = int_req & ~INT_ION;
|
||
break;
|
||
case 3: /* SRQ */
|
||
if (int_req & INT_ALL) PC = (PC + 1) & 07777;
|
||
break;
|
||
case 4: /* GTF */
|
||
LAC = (LAC & 010000) |
|
||
((LAC & 010000) >> 1) | (gtf << 10) |
|
||
(((int_req & INT_ALL) != 0) << 9) |
|
||
(((int_req & INT_ION) != 0) << 7) | SF;
|
||
break;
|
||
case 5: /* RTF */
|
||
gtf = ((LAC & 02000) >> 10);
|
||
UB = (LAC & 0100) >> 6;
|
||
IB = (LAC & 0070) << 9;
|
||
DF = (LAC & 0007) << 12;
|
||
LAC = ((LAC & 04000) << 1) | iot_data;
|
||
int_req = (int_req | INT_ION) & ~INT_NO_CIF_PENDING;
|
||
break;
|
||
case 6: /* SGT */
|
||
if (gtf) PC = (PC + 1) & 07777;
|
||
break;
|
||
case 7: /* CAF */
|
||
gtf = 0;
|
||
emode = 0;
|
||
int_req = int_req & INT_NO_CIF_PENDING;
|
||
dev_done = 0;
|
||
int_enable = INT_INIT_ENABLE;
|
||
LAC = 0;
|
||
break; } /* end switch pulse */
|
||
break; /* end case 0 */
|
||
|
||
/* IOT, continued: memory extension */
|
||
|
||
case 020:case 021:case 022:case 023:
|
||
case 024:case 025:case 026:case 027: /* memory extension */
|
||
switch (pulse) { /* decode IR<9:11> */
|
||
case 1: /* CDF */
|
||
DF = (IR & 0070) << 9;
|
||
break;
|
||
case 2: /* CIF */
|
||
IB = (IR & 0070) << 9;
|
||
int_req = int_req & ~INT_NO_CIF_PENDING;
|
||
break;
|
||
case 3: /* CDF CIF */
|
||
DF = IB = (IR & 0070) << 9;
|
||
int_req = int_req & ~INT_NO_CIF_PENDING;
|
||
break;
|
||
case 4:
|
||
switch (device & 07) { /* decode IR<6:8> */
|
||
case 0: /* CINT */
|
||
int_req = int_req & ~INT_UF;
|
||
break;
|
||
case 1: /* RDF */
|
||
LAC = LAC | (DF >> 9);
|
||
break;
|
||
case 2: /* RIF */
|
||
LAC = LAC | (IF >> 9);
|
||
break;
|
||
case 3: /* RIB */
|
||
LAC = LAC | SF;
|
||
break;
|
||
case 4: /* RMF */
|
||
UB = (SF & 0100) >> 6;
|
||
IB = (SF & 0070) << 9;
|
||
DF = (SF & 0007) << 12;
|
||
int_req = int_req & ~INT_NO_CIF_PENDING;
|
||
break;
|
||
case 5: /* SINT */
|
||
if (int_req & INT_UF) PC = (PC + 1) & 07777;
|
||
break;
|
||
case 6: /* CUF */
|
||
UB = 0;
|
||
int_req = int_req & ~INT_NO_CIF_PENDING;
|
||
break;
|
||
case 7: /* SUF */
|
||
UB = 1;
|
||
int_req = int_req & ~INT_NO_CIF_PENDING;
|
||
break; } /* end switch device */
|
||
break;
|
||
default:
|
||
reason = stop_inst;
|
||
break; } /* end switch pulse */
|
||
break; /* end case 20-27 */
|
||
|
||
/* IOT, continued: other special cases */
|
||
|
||
case 010: /* power fail */
|
||
switch (pulse) { /* decode IR<9:11> */
|
||
case 1: /* SBE */
|
||
break;
|
||
case 2: /* SPL */
|
||
if (int_req & INT_PWR) PC = (PC + 1) & 07777;
|
||
break;
|
||
case 3: /* CAL */
|
||
int_req = int_req & ~INT_PWR;
|
||
break;
|
||
default:
|
||
reason = stop_inst;
|
||
break; } /* end switch pulse */
|
||
break; /* end case 10 */
|
||
default: /* I/O device */
|
||
if (dev_tab[device]) { /* dev present? */
|
||
iot_data = dev_tab[device] (IR, iot_data);
|
||
LAC = (LAC & 010000) | (iot_data & 07777);
|
||
if (iot_data & IOT_SKP) PC = (PC + 1) & 07777;
|
||
if (iot_data >= IOT_REASON)
|
||
reason = iot_data >> IOT_V_REASON; }
|
||
else reason = stop_inst; /* stop on flag */
|
||
break; } /* end switch device */
|
||
break; /* end case IOT */
|
||
} /* end switch opcode */
|
||
} /* end while */
|
||
|
||
/* Simulation halted */
|
||
|
||
saved_PC = IF | (PC & 07777); /* save copies */
|
||
saved_DF = DF & 070000;
|
||
saved_LAC = LAC & 017777;
|
||
saved_MQ = MQ & 07777;
|
||
pcq_r->qptr = pcq_p; /* update pc q ptr */
|
||
return reason;
|
||
} /* end sim_instr */
|
||
|
||
/* Reset routine */
|
||
|
||
t_stat cpu_reset (DEVICE *dptr)
|
||
{
|
||
int_req = (int_req & ~INT_ION) | INT_NO_CIF_PENDING;
|
||
saved_DF = IB = saved_PC & 070000;
|
||
UF = UB = gtf = emode = 0;
|
||
pcq_r = find_reg ("PCQ", NULL, dptr);
|
||
if (pcq_r) pcq_r->qptr = 0;
|
||
else return SCPE_IERR;
|
||
sim_brk_types = sim_brk_dflt = SWMASK ('E');
|
||
return SCPE_OK;
|
||
}
|
||
|
||
/* Memory examine */
|
||
|
||
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw)
|
||
{
|
||
if (addr >= MEMSIZE) return SCPE_NXM;
|
||
if (vptr != NULL) *vptr = M[addr] & 07777;
|
||
return SCPE_OK;
|
||
}
|
||
|
||
/* Memory deposit */
|
||
|
||
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw)
|
||
{
|
||
if (addr >= MEMSIZE) return SCPE_NXM;
|
||
M[addr] = val & 07777;
|
||
return SCPE_OK;
|
||
}
|
||
|
||
/* Memory size change */
|
||
|
||
t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
|
||
{
|
||
int32 mc = 0;
|
||
uint32 i;
|
||
|
||
if ((val <= 0) || (val > MAXMEMSIZE) || ((val & 07777) != 0))
|
||
return SCPE_ARG;
|
||
for (i = val; i < MEMSIZE; i++) mc = mc | M[i];
|
||
if ((mc != 0) && (!get_yn ("Really truncate memory [N]?", FALSE)))
|
||
return SCPE_OK;
|
||
MEMSIZE = val;
|
||
for (i = MEMSIZE; i < MAXMEMSIZE; i++) M[i] = 0;
|
||
return SCPE_OK;
|
||
}
|
||
|
||
/* Change device number for a device */
|
||
|
||
t_stat set_dev (UNIT *uptr, int32 val, char *cptr, void *desc)
|
||
{
|
||
DEVICE *dptr;
|
||
DIB *dibp;
|
||
uint32 newdev;
|
||
t_stat r;
|
||
|
||
if (cptr == NULL) return SCPE_ARG;
|
||
if (uptr == NULL) return SCPE_IERR;
|
||
dptr = find_dev_from_unit (uptr);
|
||
if (dptr == NULL) return SCPE_IERR;
|
||
dibp = (DIB *) dptr->ctxt;
|
||
if (dibp == NULL) return SCPE_IERR;
|
||
newdev = get_uint (cptr, 8, DEV_MAX - 1, &r); /* get new */
|
||
if ((r != SCPE_OK) || (newdev == dibp->dev)) return r;
|
||
dibp->dev = newdev; /* store */
|
||
return SCPE_OK;
|
||
}
|
||
|
||
/* Show device number for a device */
|
||
|
||
t_stat show_dev (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||
{
|
||
DEVICE *dptr;
|
||
DIB *dibp;
|
||
|
||
if (uptr == NULL) return SCPE_IERR;
|
||
dptr = find_dev_from_unit (uptr);
|
||
if (dptr == NULL) return SCPE_IERR;
|
||
dibp = (DIB *) dptr->ctxt;
|
||
if (dibp == NULL) return SCPE_IERR;
|
||
fprintf (st, "devno=%02o", dibp->dev);
|
||
if (dibp->num > 1) fprintf (st, "-%2o", dibp->dev + dibp->num - 1);
|
||
return SCPE_OK;
|
||
}
|
||
|
||
/* CPU device handler - should never get here! */
|
||
|
||
int32 bad_dev (int32 IR, int32 AC)
|
||
{
|
||
return (SCPE_IERR << IOT_V_REASON) | AC; /* broken! */
|
||
}
|
||
|
||
/* Build device dispatch table */
|
||
|
||
t_bool build_dev_tab (void)
|
||
{
|
||
DEVICE *dptr;
|
||
DIB *dibp;
|
||
uint32 i, j;
|
||
static const uint8 std_dev[] =
|
||
{ 000, 010, 020, 021, 022, 023, 024, 025, 026, 027 };
|
||
|
||
for (i = 0; i < DEV_MAX; i++) dev_tab[i] = NULL; /* clr table */
|
||
for (i = 0; i < ((uint32) sizeof (std_dev)); i++) /* std entries */
|
||
dev_tab[std_dev[i]] = &bad_dev;
|
||
for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* add devices */
|
||
dibp = (DIB *) dptr->ctxt; /* get DIB */
|
||
if (dibp && !(dptr->flags & DEV_DIS)) { /* enabled? */
|
||
for (j = 0; j < dibp->num; j++) { /* loop thru disp */
|
||
if (dibp->dsp[j]) { /* any dispatch? */
|
||
if (dev_tab[dibp->dev + j]) { /* already filled? */
|
||
printf ("%s device number conflict at %02o\n",
|
||
sim_dname (dptr), dibp->dev + j);
|
||
if (sim_log) fprintf (sim_log,
|
||
"%s device number conflict at %02o\n",
|
||
sim_dname (dptr), dibp->dev + j);
|
||
return TRUE; }
|
||
dev_tab[dibp->dev + j] = dibp->dsp[j]; /* fill */
|
||
} /* end if dsp */
|
||
} /* end for j */
|
||
} /* end if enb */
|
||
} /* end for i */
|
||
return FALSE;
|
||
}
|