224 lines
6.8 KiB
C
224 lines
6.8 KiB
C
/* iRAM8.c: Intel RAM simulator for 8-bit SBCs
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Copyright (c) 2011, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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MODIFICATIONS:
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?? ??? 11 - Original file.
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NOTES:
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These functions support a simulated RAM devices on an iSBC-80/XX SBCs.
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These functions also support bit 2 of 8255 number 1, port B, to enable/
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disable the onboard RAM.
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*/
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#include "system_defs.h"
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#define BASE_ADDR u3
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#define iRAM_NAME "Intel RAM Chip"
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/* function prototypes */
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t_stat RAM_cfg(uint16 base, uint16 size, uint8 dummy);
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t_stat RAM_clr(void);
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t_stat RAM_reset (DEVICE *dptr);
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t_stat RAM_set_size(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat RAM_set_base(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat RAM_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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uint8 RAM_get_mbyte(uint16 addr);
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void RAM_put_mbyte(uint16 addr, uint8 val);
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/* external function prototypes */
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/* external globals */
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// globals
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static const char* iRAM_desc(DEVICE *dptr) {
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return iRAM_NAME;
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}
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/* SIMH RAM Standard I/O Data Structures */
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UNIT RAM_unit = { UDATA (NULL, UNIT_BINK, 0) };
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MTAB RAM_mod[] = {
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{ MTAB_XTD | MTAB_VDV, 0, NULL, "BASE", &RAM_set_base,
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NULL, NULL, "Sets the base address for RAM"},
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{ MTAB_XTD | MTAB_VDV, 0, NULL, "SIZE", &RAM_set_size,
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NULL, NULL, "Sets the size for RAM"},
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{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, RAM_show_param, NULL,
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"show configured parameters for RAM" },
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{ 0 }
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};
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DEBTAB RAM_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "XACK", DEBUG_xack },
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{ NULL }
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};
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DEVICE RAM_dev = {
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"RAM", //name
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&RAM_unit, //units
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NULL, //registers
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RAM_mod, //modifiers
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1, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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RAM_reset, //reset
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NULL, //boot
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NULL, //attach
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NULL, //detach
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NULL, //ctxt
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DEV_DEBUG+DEV_DISABLE+DEV_DIS, //flags
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0, //dctrl
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RAM_debug, //debflags
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NULL, //msize
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NULL, //lname
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NULL, //help routine
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NULL, //attach help routine
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NULL, //help context
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&iRAM_desc //device description
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};
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/* RAM functions */
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// RAM configuration
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t_stat RAM_cfg(uint16 base, uint16 size, uint8 dummy)
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{
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RAM_unit.capac = size; /* set RAM size */
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RAM_unit.u3 = base; /* set RAM base */
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RAM_unit.filebuf = (uint8 *)calloc(size, sizeof(uint8));
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if (RAM_unit.filebuf == NULL) {
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sim_printf (" RAM: Calloc error\n");
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return SCPE_MEM;
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}
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sim_printf(" RAM: 0%04XH bytes at base address 0%04XH\n",
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size, base);
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return SCPE_OK;
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}
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t_stat RAM_clr(void)
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{
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RAM_unit.capac = 0;
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RAM_unit.u3 = 0;
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free(RAM_unit.filebuf);
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return SCPE_OK;
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}
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/* RAM reset */
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t_stat RAM_reset (DEVICE *dptr)
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{
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return SCPE_OK;
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}
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// set size parameter
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t_stat RAM_set_size(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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uint32 size, result, i;
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if (cptr == NULL)
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return SCPE_ARG;
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result = sscanf(cptr, "%i%n", &size, &i);
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if ((result == 1) && (cptr[i] == 'K') && ((cptr[i + 1] == 0) ||
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((cptr[i + 1] == 'B') && (cptr[i + 2] == 0)))) {
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if (size & 0xff8f) {
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sim_printf("RAM: Size error\n");
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return SCPE_ARG;
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} else {
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RAM_unit.capac = (size * 1024) - 1;
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sim_printf("RAM: Size=%04XH\n", RAM_unit.capac);
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return SCPE_OK;
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}
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}
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return SCPE_ARG;
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}
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// set base address parameter
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t_stat RAM_set_base(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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uint32 size, result, i;
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if (cptr == NULL)
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return SCPE_ARG;
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result = sscanf(cptr, "%i%n", &size, &i);
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if ((result == 1) && (cptr[i] == 'K') && ((cptr[i + 1] == 0) ||
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((cptr[i + 1] == 'B') && (cptr[i + 2] == 0)))) {
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if (size & 0xff8f) {
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sim_printf("RAM: Base error\n");
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return SCPE_ARG;
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} else {
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RAM_unit.BASE_ADDR = size * 1024;
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sim_printf("RAM: Base=%04XH\n", RAM_unit.BASE_ADDR);
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return SCPE_OK;
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}
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}
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return SCPE_ARG;
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}
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// show configuration parameters
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t_stat RAM_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
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{
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if (uptr == NULL)
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return SCPE_ARG;
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fprintf(st, "%s at Base Address 0%04XH (%dD) for 0%04XH (%dD) Bytes ",
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((RAM_dev.flags & DEV_DIS) == 0) ? "Enabled" : "Disabled",
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RAM_unit.u3, RAM_unit.u3, RAM_unit.capac, RAM_unit.capac);
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return SCPE_OK;
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}
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/* get a byte from memory */
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uint8 RAM_get_mbyte(uint16 addr)
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{
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uint8 val;
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val = *((uint8 *)RAM_unit.filebuf + (addr - RAM_unit.u3));
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return (val & BYTEMASK);
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}
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/* put a byte into memory */
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void RAM_put_mbyte(uint16 addr, uint8 val)
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{
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*((uint8 *)RAM_unit.filebuf + (addr - RAM_unit.u3)) = val & BYTEMASK;
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return;
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}
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/* end of iRAM8.c */
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