7a5432d9e2
sim> mem df00 DF00 C3 5C E2 C3 58 E2 7F 00 43 6F 70 79 72 69 67 68 .\..X...Copyrigh DF10 74 20 31 39 37 39 20 28 63 29 20 62 79 20 44 69 t 1979 (c) by Di DF20 67 69 74 61 6C 20 52 65 73 65 61 72 63 68 20 20 gital Research DF30 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 ............ DF40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ DF50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ DF60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ....s...ub...m.. DF70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ..I..tT...e..... DF80 00 00 00 00 00 00 00 00 08 DF 00 00 5F 0E 02 C3 d....4...l.._0.r DF90 05 00 C5 CD 8C DF C1 C9 3E 0D CD 92 DF 3E 0A C3 .d..M...>....>.. DFA0 92 DF 3E 20 C3 92 DF C5 CD 98 DF E1 7E B7 C8 23 ..> ..a.....~..# DFB0 E5 CD 8C DF E1 C3 AC DF 0E 0D C3 05 00 5F 0E 0E ...r........._.. DFC0 C3 05 00 CD 05 00 32 EE E6 3C C9 0E 0F C3 C3 DF ...K..2..<..'.s. DFD0 AF 32 ED E6 11 CD E6 C3 CB DF 0E 10 C3 C3 DF 0E .2...a...p.P.... DFE0 11 C3 C3 DF 0E 12 C3 C3 DF 11 CD E6 C3 DF DF 0E ...r...0..v..... DFF0 13 C3 05 00 CD 05 00 B7 C9 0E 14 C3 F4 DF 11 CD .....a.l........ sim> reg C0Z1M0E1I1 A=02 B=007F D=DF06 H=EA0E S=EA37 P=FA6B ANI 01h sim> set on sim> on error reg sim> s Step expired, PC: 0FA6D (JZ 0FA69h) C0Z1M0E1I1 A=00 B=007F D=DF06 H=EA0E S=EA37 P=FA6D JZ 0FA69h sim> s Step expired, PC: 0FA69 (IN 10h) C0Z1M0E1I1 A=00 B=007F D=DF06 H=EA0E S=EA37 P=FA69 IN 10h sim> s Step expired, PC: 0FA6B (ANI 01h) C0Z1M0E1I1 A=02 B=007F D=DF06 H=EA0E S=EA37 P=FA6B ANI 01h
103 lines
6 KiB
C
103 lines
6 KiB
C
/* altairz80_defs.h: MITS Altair simulator definitions
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Copyright (c) 2002-2014, Peter Schorn
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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PETER SCHORN BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Peter Schorn shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Peter Schorn.
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Based on work by Charles E Owen (c) 1997
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*/
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#ifndef ALTAIRZ80_DEFS_H_
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#define ALTAIRZ80_DEFS_H_ 0
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#include "sim_defs.h" /* simulator definitions */
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#define MAXBANKSIZE 65536 /* maximum memory size, a power of 2 */
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#define MAXBANKSIZELOG2 16 /* log2 of MAXBANKSIZE */
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#define MAXBANKS 16 /* max number of memory banks, a power of 2 */
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#define MAXBANKSLOG2 4 /* log2 of MAXBANKS */
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#define MAXMEMORY (MAXBANKS * MAXBANKSIZE) /* maximum, total memory size */
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#define ADDRMASK (MAXBANKSIZE - 1) /* address mask */
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#define ADDRMASKEXTENDED (MAXMEMORY - 1) /* extended address mask */
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#define BANKMASK (MAXBANKS - 1) /* bank mask */
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#define MEMORYSIZE (cpu_unit.capac) /* actual memory size */
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#define MEMORYMASK (cpu_unit.capac - 1) /* actual memory size mask */
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#define KB 1024 /* kilo byte */
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#define KBLOG2 10 /* log2 of KB */
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#define ALTAIR_ROM_LOW 0xff00 /* start address of regular Altair ROM */
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#define RESOURCE_TYPE_MEMORY 1
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#define RESOURCE_TYPE_IO 2
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#define MAX_INT_VECTORS 32 /* maximum number of interrupt vectors */
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#define NUM_OF_DSK 16 /* NUM_OF_DSK must be power of two */
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#define LDA_INSTRUCTION 0x3e /* op-code for LD A,<8-bit value> instruction */
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#define UNIT_NO_OFFSET_1 0x37 /* LD A,<unitno> */
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#define UNIT_NO_OFFSET_2 0xb4 /* LD a,80h | <unitno> */
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#define CPU_INDEX_8080 4 /* index of default PC register */
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typedef enum {
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CHIP_TYPE_8080 = 0,
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CHIP_TYPE_Z80,
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CHIP_TYPE_8086,
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CHIP_TYPE_M68K, /* must come after 8080, Z80 and 8086 */
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NUM_CHIP_TYPE, /* must be last */
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} ChipType;
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/* simulator stop codes */
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#define STOP_HALT 0 /* HALT */
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#define STOP_IBKPT 1 /* breakpoint (program counter) */
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#define STOP_MEM 2 /* breakpoint (memory access) */
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#define STOP_INSTR 3 /* breakpoint (instruction access) */
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#define STOP_OPCODE 4 /* invalid operation encountered (8080, Z80, 8086) */
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#define UNIT_CPU_V_OPSTOP (UNIT_V_UF+0) /* stop on invalid operation */
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#define UNIT_CPU_OPSTOP (1 << UNIT_CPU_V_OPSTOP)
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#define UNIT_CPU_V_BANKED (UNIT_V_UF+1) /* banked memory is used */
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#define UNIT_CPU_BANKED (1 << UNIT_CPU_V_BANKED)
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#define UNIT_CPU_V_ALTAIRROM (UNIT_V_UF+2) /* ALTAIR ROM exists */
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#define UNIT_CPU_ALTAIRROM (1 << UNIT_CPU_V_ALTAIRROM)
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#define UNIT_CPU_V_VERBOSE (UNIT_V_UF+3) /* warn if ROM is written to */
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#define UNIT_CPU_VERBOSE (1 << UNIT_CPU_V_VERBOSE)
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#define UNIT_CPU_V_MMU (UNIT_V_UF+4) /* use MMU and slower CPU */
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#define UNIT_CPU_MMU (1 << UNIT_CPU_V_MMU)
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#define UNIT_CPU_V_STOPONHALT (UNIT_V_UF+5) /* stop simulation on HALT */
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#define UNIT_CPU_STOPONHALT (1 << UNIT_CPU_V_STOPONHALT)
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#define UNIT_CPU_V_SWITCHER (UNIT_V_UF+6) /* switcher 8086 <--> 8080/Z80 enabled */
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#define UNIT_CPU_SWITCHER (1 << UNIT_CPU_V_SWITCHER)
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#define ADDRESS_FORMAT "[0x%08x]"
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#if (defined (__MWERKS__) && defined (macintosh)) || defined(__DECC)
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#define __FUNCTION__ __FILE__
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#endif
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typedef struct {
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uint32 mem_base; /* Memory Base Address */
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uint32 mem_size; /* Memory Address space requirement */
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uint32 io_base; /* I/O Base Address */
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uint32 io_size; /* I/O Address Space requirement */
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} PNP_INFO;
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extern ChipType chiptype;
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#endif
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