53d02f7fa7
1. New Features 1.1 3.7-0 1.1.1 SCP - Added SET THROTTLE and SET NOTHROTTLE commands to regulate simulator execution rate and host resource utilization. - Added idle support (based on work by Mark Pizzolato). - Added -e to control error processing in nested DO commands (from Dave Bryan). 1.1.2 HP2100 - Added Double Integer instructions, 1000-F CPU, and Floating Point Processor (from Dave Bryan). - Added 2114 and 2115 CPUs, 12607B and 12578A DMA controllers, and 21xx binary loader protection (from Dave Bryan). 1.1.3 Interdata - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state. 1.1.4 PDP-11 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (WAIT instruction executed). - Added TA11/TU60 cassette support. 1.1.5 PDP-8 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (keyboard poll loop or jump-to-self). - Added TA8E/TU60 cassette support. 1.1.6 PDP-1 - Added support for 16-channel sequence break system. - Added support for PDP-1D extended features and timesharing clock. - Added support for Type 630 data communications subsystem. 1.1.6 PDP-4/7/9/15 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (keyboard poll loop or jump-to-self). 1.1.7 VAX, VAX780 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (more than 200 cycles at IPL's 0, 1, or 3 in kernel mode). 1.1.8 PDP-10 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (operating system dependent). - Added CD20 (CD11) support. 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h.
206 lines
8.9 KiB
C
206 lines
8.9 KiB
C
/* hp2100_cpu.h: HP 2100 CPU definitions
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Copyright (c) 2005-2006, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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16-Dec-06 JDB Added UNIT_2115 and UNIT_2114
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16-Oct-06 JDB Moved ReadF to hp2100_cpu1.c
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26-Sep-06 JDB Added CPU externs for microcode simulators
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16-Aug-06 JDB Added UNIT_EMA for future RTE-4 EMA microcode
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Added UNIT_VMA for future RTE-6 VMA and OS microcode
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Added UNIT_1000_F for future F-Series support
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09-Aug-06 JDB Added UNIT_DBI for double integer microcode
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21-Jan-05 JDB Reorganized CPU option flags
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14-Jan-05 RMS Cloned from hp2100_cpu.c
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CPU models are broken down into family, type, and series to facilitate option
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validation. Bit 3 encodes the family, bit 2 encodes the type, and bits 1:0
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encode the series within the type.
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*/
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#ifndef _HP2100_CPU_H_
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#define _HP2100_CPU_H_ 0
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/* CPU model definition flags */
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#define CPU_V_SERIES 0
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#define CPU_V_TYPE 2
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#define CPU_V_FAMILY 3
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#define FAMILY_21XX (0 << CPU_V_FAMILY)
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#define FAMILY_1000 (1 << CPU_V_FAMILY)
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#define TYPE_211X (0 << CPU_V_TYPE) /* 2114, 2115, 2116 */
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#define TYPE_2100 (1 << CPU_V_TYPE) /* 2100A, 2100S */
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#define TYPE_1000MEF (0 << CPU_V_TYPE) /* 1000-M, 1000-E, 1000-F */
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#define TYPE_1000AL (1 << CPU_V_TYPE) /* 1000-L, A600, A700, A900, A990 */
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#define SERIES_16 (0 << CPU_V_SERIES) /* 211X */
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#define SERIES_15 (1 << CPU_V_SERIES) /* 211X */
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#define SERIES_14 (2 << CPU_V_SERIES) /* 211X */
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#define SERIES_00 (0 << CPU_V_SERIES) /* 2100 */
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#define SERIES_M (0 << CPU_V_SERIES) /* 1000 */
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#define SERIES_E (1 << CPU_V_SERIES) /* 1000 */
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#define SERIES_F (2 << CPU_V_SERIES) /* 1000 */
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/* CPU unit flags */
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#define UNIT_M_CPU 017 /* CPU model mask [3:0] */
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#define UNIT_M_TYPE 014 /* CPU type mask [3:2] */
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#define UNIT_M_FAMILY 010 /* CPU family mask [3:3] */
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#define UNIT_V_CPU (UNIT_V_UF + 0) /* CPU model bits 0-3 */
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#define UNIT_V_EAU (UNIT_V_UF + 4) /* EAU installed */
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#define UNIT_V_FP (UNIT_V_UF + 5) /* FP installed */
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#define UNIT_V_IOP (UNIT_V_UF + 6) /* IOP installed */
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#define UNIT_V_DMS (UNIT_V_UF + 7) /* DMS installed */
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#define UNIT_V_FFP (UNIT_V_UF + 8) /* FFP installed */
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#define UNIT_V_DBI (UNIT_V_UF + 9) /* DBI installed */
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#define UNIT_V_EMA (UNIT_V_UF + 10) /* RTE-4 EMA installed */
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#define UNIT_V_VMAOS (UNIT_V_UF + 11) /* RTE-6 VMA/OS installed */
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/* Future microcode expansion; reuse flags bottom-up if needed */
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#define UNIT_V_VIS (UNIT_V_UF + 12) /* VIS installed */
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#define UNIT_V_DS (UNIT_V_UF + 13) /* DS installed */
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#define UNIT_V_SIGNAL (UNIT_V_UF + 14) /* SIGNAL/1000 installed */
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/* Unit models */
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#define UNIT_MODEL_MASK (UNIT_M_CPU << UNIT_V_CPU)
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#define UNIT_2116 ((FAMILY_21XX | TYPE_211X | SERIES_16) << UNIT_V_CPU)
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#define UNIT_2115 ((FAMILY_21XX | TYPE_211X | SERIES_15) << UNIT_V_CPU)
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#define UNIT_2114 ((FAMILY_21XX | TYPE_211X | SERIES_14) << UNIT_V_CPU)
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#define UNIT_2100 ((FAMILY_21XX | TYPE_2100 | SERIES_00) << UNIT_V_CPU)
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#define UNIT_1000_M ((FAMILY_1000 | TYPE_1000MEF | SERIES_M) << UNIT_V_CPU)
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#define UNIT_1000_E ((FAMILY_1000 | TYPE_1000MEF | SERIES_E) << UNIT_V_CPU)
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#define UNIT_1000_F ((FAMILY_1000 | TYPE_1000MEF | SERIES_F) << UNIT_V_CPU)
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/* Unit types */
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#define UNIT_TYPE_MASK (UNIT_M_TYPE << UNIT_V_CPU)
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#define UNIT_TYPE_211X ((FAMILY_21XX | TYPE_211X) << UNIT_V_CPU)
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#define UNIT_TYPE_2100 ((FAMILY_21XX | TYPE_2100) << UNIT_V_CPU)
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#define UNIT_TYPE_1000 ((FAMILY_1000 | TYPE_1000MEF) << UNIT_V_CPU)
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/* Unit families */
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#define UNIT_FAMILY_MASK (UNIT_M_FAMILY << UNIT_V_CPU)
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#define UNIT_FAMILY_21XX (FAMILY_21XX << UNIT_V_CPU)
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#define UNIT_FAMILY_1000 (FAMILY_1000 << UNIT_V_CPU)
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/* Unit accessors */
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#define UNIT_CPU_MODEL (cpu_unit.flags & UNIT_MODEL_MASK)
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#define UNIT_CPU_TYPE (cpu_unit.flags & UNIT_TYPE_MASK)
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#define UNIT_CPU_FAMILY (cpu_unit.flags & UNIT_FAMILY_MASK)
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#define CPU_MODEL_INDEX (UNIT_CPU_MODEL >> UNIT_V_CPU)
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/* Unit features */
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#define UNIT_EAU (1 << UNIT_V_EAU)
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#define UNIT_FP (1 << UNIT_V_FP)
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#define UNIT_IOP (1 << UNIT_V_IOP)
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#define UNIT_DMS (1 << UNIT_V_DMS)
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#define UNIT_FFP (1 << UNIT_V_FFP)
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#define UNIT_DBI (1 << UNIT_V_DBI)
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#define UNIT_EMA (1 << UNIT_V_EMA)
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#define UNIT_VMAOS (1 << UNIT_V_VMAOS)
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#define UNIT_VIS (1 << UNIT_V_VIS)
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#define UNIT_DS (1 << UNIT_V_DS)
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#define UNIT_SIGNAL (1 << UNIT_V_SIGNAL)
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#define UNIT_EMA_VMA (UNIT_EMA | UNIT_VMAOS)
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#define UNIT_OPTS (UNIT_EAU | UNIT_FP | UNIT_IOP | \
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UNIT_DMS | UNIT_FFP | UNIT_DBI | \
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UNIT_EMA | UNIT_VMAOS | \
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UNIT_VIS | UNIT_DS | UNIT_SIGNAL)
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/* "Pseudo-option" flags used only for option testing; never set into UNIT structure. */
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#define UNIT_V_PFAIL (UNIT_V_UF - 1) /* Power fail installed */
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#define UNIT_V_DMA (UNIT_V_UF - 2) /* DMA installed */
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#define UNIT_V_MP (UNIT_V_UF - 3) /* Memory protect installed */
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#define UNIT_PFAIL (1 << UNIT_V_PFAIL)
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#define UNIT_DMA (1 << UNIT_V_DMA)
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#define UNIT_MP (1 << UNIT_V_MP)
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#define UNIT_NONE 0 /* no options */
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/* PC queue. */
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#define PCQ_SIZE 64 /* must be 2**n */
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#define PCQ_MASK (PCQ_SIZE - 1)
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#define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = err_PC
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/* CPU registers */
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extern uint16 ABREG[2]; /* A/B regs (use AR/BR) */
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extern uint32 PC; /* P register */
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extern uint32 SR; /* S register */
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extern uint32 MR; /* M register */
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extern uint32 TR; /* T register */
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extern uint32 XR; /* X register */
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extern uint32 YR; /* Y register */
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extern uint32 E; /* E register */
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extern uint32 O; /* O register */
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/* CPU state */
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extern uint32 err_PC;
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extern uint32 dms_enb;
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extern uint32 dms_ump;
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extern uint32 dms_sr;
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extern uint32 dms_vr;
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extern uint32 mp_fence;
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extern uint32 iop_sp;
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extern uint32 ion_defer;
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extern uint16 pcq[PCQ_SIZE];
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extern uint32 pcq_p;
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extern uint32 stop_inst;
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extern UNIT cpu_unit;
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/* CPU functions */
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t_stat resolve (uint32 MA, uint32 *addr, uint32 irq);
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uint8 ReadB (uint32 addr);
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uint8 ReadBA (uint32 addr);
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uint16 ReadW (uint32 addr);
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uint16 ReadWA (uint32 addr);
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void WriteB (uint32 addr, uint32 dat);
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void WriteBA (uint32 addr, uint32 dat);
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void WriteW (uint32 addr, uint32 dat);
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void WriteWA (uint32 addr, uint32 dat);
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t_stat iogrp (uint32 ir, uint32 iotrap);
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void mp_dms_jmp (uint32 va);
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uint16 dms_rmap (uint32 mapi);
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void dms_wmap (uint32 mapi, uint32 dat);
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void dms_viol (uint32 va, uint32 st);
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uint32 dms_upd_sr (void);
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#endif
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