53d02f7fa7
1. New Features 1.1 3.7-0 1.1.1 SCP - Added SET THROTTLE and SET NOTHROTTLE commands to regulate simulator execution rate and host resource utilization. - Added idle support (based on work by Mark Pizzolato). - Added -e to control error processing in nested DO commands (from Dave Bryan). 1.1.2 HP2100 - Added Double Integer instructions, 1000-F CPU, and Floating Point Processor (from Dave Bryan). - Added 2114 and 2115 CPUs, 12607B and 12578A DMA controllers, and 21xx binary loader protection (from Dave Bryan). 1.1.3 Interdata - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state. 1.1.4 PDP-11 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (WAIT instruction executed). - Added TA11/TU60 cassette support. 1.1.5 PDP-8 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (keyboard poll loop or jump-to-self). - Added TA8E/TU60 cassette support. 1.1.6 PDP-1 - Added support for 16-channel sequence break system. - Added support for PDP-1D extended features and timesharing clock. - Added support for Type 630 data communications subsystem. 1.1.6 PDP-4/7/9/15 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (keyboard poll loop or jump-to-self). 1.1.7 VAX, VAX780 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (more than 200 cycles at IPL's 0, 1, or 3 in kernel mode). 1.1.8 PDP-10 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (operating system dependent). - Added CD20 (CD11) support. 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h.
557 lines
23 KiB
C
557 lines
23 KiB
C
/* hp2100_cpu0.c: HP 1000 unimplemented instruction set stubs
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Copyright (c) 2006, J. David Bryan
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of the author shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from the author.
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CPU0 Unimplemented firmware option instructions
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01-Dec-06 JDB Removed and implemented "cpu_sis".
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26-Sep-06 JDB Created
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This file contains template simulations for the firmware options that have
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not yet been implemented. When a given firmware option is implemented, it
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should be moved out of this file and into another (or its own, depending on
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complexity).
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Primary references:
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- HP 1000 M/E/F-Series Computers Technical Reference Handbook
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(5955-0282, Mar-1980)
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- HP 1000 M/E/F-Series Computers Engineering and Reference Documentation
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(92851-90001, Mar-1981)
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- Macro/1000 Reference Manual (92059-90001, Dec-1992)
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Additional references are listed with the associated firmware
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implementations, as are the HP option model numbers pertaining to the
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applicable CPUs.
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*/
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#include "hp2100_defs.h"
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#include "hp2100_cpu.h"
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#include "hp2100_cpu1.h"
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t_stat cpu_rte_ema (uint32 IR, uint32 intrq); /* RTE-4 EMA */
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t_stat cpu_rte_vma (uint32 IR, uint32 intrq); /* RTE-6 VMA */
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t_stat cpu_rte_os (uint32 IR, uint32 intrq, uint32 iotrap); /* RTE-6 OS */
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t_stat cpu_ds (uint32 IR, uint32 intrq); /* Distributed System */
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t_stat cpu_vis (uint32 IR, uint32 intrq); /* Vector Instruction Set */
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t_stat cpu_signal (uint32 IR, uint32 intrq); /* SIGNAL/1000 Instructions */
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/* RTE-IV Extended Memory Area Instructions
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The RTE-IV operating system (HP product number 92067A) introduced the
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Extended Memory Area (EMA) instructions. EMA provided a mappable data area
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up to one megaword in size. These three instructions accelerated data
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accesses to variables stored in EMA partitions. Support was limited to
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E/F-Series machines; M-Series machines used software equivalents.
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Option implementation by CPU was as follows:
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2114 2115 2116 2100 1000-M 1000-E 1000-F
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------ ------ ------ ------ ------ ------ ------
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N/A N/A N/A N/A N/A 92067A 92067A
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The routines are mapped to instruction codes as follows:
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Instr. 1000-E/F Description
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------ -------- ----------------------------------------------
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.EMIO 105240 EMA I/O
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MMAP 105241 Map physical to logical memory
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[test] 105242 [self test]
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.EMAP 105257 Resolve array element address
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Notes:
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1. RTE-IV EMA and RTE-6 VMA instructions share the same address space, so a
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given machine can run one or the other, but not both.
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Additional references:
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- RTE-IVB Programmer's Reference Manual (92068-90004, Dec-1983).
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- RTE-IVB Technical Specifications (92068-90013, Jan-1980).
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*/
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static const OP_PAT op_ema[16] = {
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OP_A, OP_AKK, OP_N, OP_N, /* .EMIO MMAP [test] --- */
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OP_N, OP_N, OP_N, OP_N, /* --- --- --- --- */
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OP_N, OP_N, OP_N, OP_N, /* --- --- --- --- */
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OP_N, OP_N, OP_N, OP_A /* --- --- --- .EMAP */
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};
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t_stat cpu_rte_ema (uint32 IR, uint32 intrq)
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{
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t_stat reason = SCPE_OK;
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OPS op;
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uint32 entry;
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if ((cpu_unit.flags & UNIT_EMA) == 0) /* EMA option installed? */
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return stop_inst;
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entry = IR & 017; /* mask to entry point */
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if (op_ema[entry] != OP_N)
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if (reason = cpu_ops (op_ema[entry], op, intrq)) /* get instruction operands */
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return reason;
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switch (entry) { /* decode IR<3:0> */
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default: /* others undefined */
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reason = stop_inst;
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}
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return reason;
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}
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/* RTE-6/VM Virtual Memory Area Instructions
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RTE-6/VM (product number 92084A) introduced Virtual Memory Area (VMA)
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instructions -- a superset of the RTE-IV EMA instructions. Different
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microcode was supplied with the operating system that replaced the microcode
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used with RTE-IV. Microcode was limited to the E/F-Series, and the M-Series
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used software equivalents.
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Option implementation by CPU was as follows:
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2114 2115 2116 2100 1000-M 1000-E 1000-F
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------ ------ ------ ------ ------ ------ ------
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N/A N/A N/A N/A N/A 92084A 92084A
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The routines are mapped to instruction codes as follows:
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Instr. 1000-E/F Description
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------ -------- ----------------------------------------------
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.PMAP 105240 Map VMA page into map register
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$LOC 105241 Load on call
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[test] 105242 [self test]
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.SWP 105243 [Swap A and B registers]
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.STAS 105244 [STA B; LDA SP]
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.LDAS 105245 [LDA SP]
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.MYAD 105246 [NOP in microcode]
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.UMPY 105247 [Unsigned multiply and add]
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.IMAP 105250 Integer element resolve address and map
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.IMAR 105251 Integer element resolve address
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.JMAP 105252 Double integer element resolve address and map
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.JMAR 105253 Double integer element resolve address
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.LPXR 105254 Map pointer in P+1 plus offset in P+2
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.LPX 105255 Map pointer in A/B plus offset in P+1
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.LBPR 105256 Map pointer in P+1
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.LBP 105257 Map pointer in A/B registers
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Notes:
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1. The opcodes 105243-247 are undocumented and do not appear to be used in
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any HP software.
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2. The opcode list in the CE Handbook incorrectly shows 105246 as ".MYAD -
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multiply 2 signed integers." The microcode listing shows that this
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instruction was deleted, and the opcode is now a NOP.
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3. RTE-IV EMA and RTE-6 VMA instructions shared the same address space, so
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a given machine could run one or the other, but not both.
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Additional references:
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- RTE-6/VM VMA/EMA Microcode Source (92084-18828, revision 3).
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- RTE-6/VM Technical Specifications (92084-90015, Apr-1983).
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- M/E/F-Series Computer Systems CE Handbook (5950-3767, Jul-1984).
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*/
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static const OP_PAT op_vma[16] = {
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OP_N, OP_KKKAKK, OP_N, OP_N, /* .PMAP $LOC [test] .SWAP */
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OP_N, OP_N, OP_N, OP_K, /* .STAS .LDAS .MYAD .UMPY */
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OP_A, OP_A, OP_A, OP_A, /* .IMAP .IMAR .JMAP .JMAR */
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OP_FF, OP_F, OP_F, OP_N /* .LPXR .LPX .LBPR .LBP */
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};
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t_stat cpu_rte_vma (uint32 IR, uint32 intrq)
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{
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t_stat reason = SCPE_OK;
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OPS op;
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uint32 entry;
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if ((cpu_unit.flags & UNIT_VMAOS) == 0) /* VMA/OS option installed? */
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return cpu_rte_ema (IR, intrq); /* try EMA */
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entry = IR & 017; /* mask to entry point */
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if (op_vma[entry] != OP_N)
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if (reason = cpu_ops (op_vma[entry], op, intrq)) /* get instruction operands */
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return reason;
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switch (entry) { /* decode IR<3:0> */
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default: /* others undefined */
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reason = stop_inst;
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}
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return reason;
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}
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/* RTE-6/VM Operating System Instructions
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The OS instructions were added to acccelerate certain time-consuming
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operations of the RTE-6/VM operating system, HP product number 92084A.
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Microcode was available for the E- and F-Series; the M-Series used software
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equivalents.
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Option implementation by CPU was as follows:
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2114 2115 2116 2100 1000-M 1000-E 1000-F
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------ ------ ------ ------ ------ ------ ------
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N/A N/A N/A N/A N/A 92084A 92084A
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The routines are mapped to instruction codes as follows:
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Instr. 1000-E/F Description
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------ -------- ----------------------------------------------
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$LIBR 105340 Enter privileged/reentrant library routine
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$LIBX 105341 Exit privileged/reentrant library routine
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.TICK 105342 TBG tick interrupt handler
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.TNAM 105343 Find ID segment that matches name
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.STIO 105344 Configure I/O instructions
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.FNW 105345 Find word with user increment
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.IRT 105346 Interrupt return processing
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.LLS 105347 Linked list search
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.SIP 105350 Skip if interrupt pending
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.YLD 105351 .SIP completion return point
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.CPM 105352 Compare words LT/EQ/GT
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.ETEQ 105353 Set up EQT pointers in base page
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.ENTN 105354 Transfer parameter addresses (utility)
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[test] 105355 [self test]
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.ENTC 105356 Transfer parameter addresses (priv/reent)
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.DSPI 105357 Set display indicator
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Opcodes 105354-105357 are "dual use" instructions that take different
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actions, depending on whether they are executed from a trap cell during an
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interrupt. When executed from a trap cell, they have these actions:
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Instr. 1000-E/F Description
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------ -------- ----------------------------------------------
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[dma] 105354 DCPC channel interrupt processing
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[dms] 105355 DMS/MP/PE interrupt processing
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[dev] 105356 Standard device interrupt processing
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[tbg] 105357 TBG interrupt processing
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Notes:
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1. The microcode differentiates between interrupt processing and normal
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execution of the "dual use" instructions by testing the CPU flag.
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Interrupt vectoring sets the flag; a normal instruction fetch clears it.
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Under simulation, interrupt vectoring is indicated by the value of the
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"iotrap" parameter.
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2. The operand patterns for .ENTN and .ENTC normally would be coded as
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"OP_A", as each takes a single address as a parameter. However, because
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they might also be executed from a trap cell, we cannot assume that P+1
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is an address, or we might cause a DM abort when trying to access
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memory. Therefore, "OP_A" handling is done within each routine, once
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the type of use is determined.
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Additional references:
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- RTE-6/VM O/S Microcode Source (92084-18831, revision 6).
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- RTE-6/VM Technical Specifications (92084-90015, Apr-1983).
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*/
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static const OP_PAT op_os[16] = {
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OP_A, OP_A, OP_N, OP_N, /* $LIBR $LIBX .TICK .TNAM */
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OP_A, OP_K, OP_A, OP_KK, /* .STIO .FNW .IRT .LLS */
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OP_N, OP_CC, OP_KK, OP_N, /* .SIP .YLD .CPM .ETEQ */
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OP_N, OP_N, OP_N, OP_N /* .ENTN [test] .ENTC .DSPI */
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};
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t_stat cpu_rte_os (uint32 IR, uint32 intrq, uint32 iotrap)
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{
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t_stat reason = SCPE_OK;
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OPS op;
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uint32 entry;
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if ((cpu_unit.flags & UNIT_VMAOS) == 0) /* VMA/OS option installed? */
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return stop_inst;
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entry = IR & 017; /* mask to entry point */
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if (op_os[entry] != OP_N)
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if (reason = cpu_ops (op_os[entry], op, intrq)) /* get instruction operands */
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return reason;
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switch (entry) { /* decode IR<3:0> */
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default: /* others undefined */
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reason = stop_inst;
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}
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return reason;
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}
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/* Distributed System
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Distributed System firmware was provided with the HP 91740A DS/1000 product
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for use with the HP 12771A (12665A) Serial Interface and 12773A Modem
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Interface system interconnection kits. Firmware permitted high-speed
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transfers with minimum impact to the processor. The advent of the
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"intelligent" 12794A and 12825A HDLC cards, the 12793A and 12834A Bisync
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cards, and the 91750A DS-1000/IV software obviated the need for CPU firmware,
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as essentially the firmware was moved onto the I/O cards.
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Primary documentation for the DS instructions has not been located. However,
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examination of the DS/1000 sources reveals that two instruction were used by
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the DVA65 Serial Interface driver (91740-18071) and placed in the trap cells
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of the communications interfaces. Presumably they handled interrupts from
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the cards.
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Implementation of the DS instructions will also require simulation of the
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12665A Hardwired Serial Data Interface Card and the 12620A RTE Privileged
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Interrupt Fence. These are required for DS/1000.
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Option implementation by CPU was as follows:
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2114 2115 2116 2100 1000-M 1000-E 1000-F
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------ ------ ------ ------ ------ ------ ------
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N/A N/A N/A N/A 91740A 91740B 91740B
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The routines are mapped to instruction codes as follows:
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Instr. 1000-M 1000-E/F Description
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------ ------ -------- ----------------------------------------------
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105520 105300 "Open loop" (trap cell handler)
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105521 105301 "Closed loop" (trap cell handler)
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105522 105302 [unknown]
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[test] 105524 105304 [self test]
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Notes:
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1. The E/F-Series opcodes were moved from 105340-357 to 105300-317 at
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revision 1813.
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2. DS/1000 ROM data are available from Bitsavers.
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Additional references (documents unavailable):
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- HP 91740A M-Series Distributed System (DS/1000) Firmware Installation
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Manual (91740-90007).
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- HP 91740B Distributed System (DS/1000) Firmware Installation Manual
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(91740-90009).
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*/
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static const OP_PAT op_ds[16] = {
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OP_N, OP_N, OP_N, OP_N, /* --- --- --- --- */
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OP_N, OP_N, OP_N, OP_N, /* --- --- --- --- */
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OP_N, OP_N, OP_N, OP_N, /* --- --- --- --- */
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OP_N, OP_N, OP_N, OP_N /* --- --- --- --- */
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};
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t_stat cpu_ds (uint32 IR, uint32 intrq)
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{
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t_stat reason = SCPE_OK;
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OPS op;
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uint32 entry;
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if ((cpu_unit.flags & UNIT_DS) == 0) /* DS option installed? */
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return stop_inst;
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entry = IR & 017; /* mask to entry point */
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if (op_ds[entry] != OP_N)
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if (reason = cpu_ops (op_ds[entry], op, intrq)) /* get instruction operands */
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return reason;
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switch (entry) { /* decode IR<3:0> */
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default: /* others undefined */
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reason = stop_inst;
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}
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return reason;
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}
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/* Vector Instruction Set
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The VIS provides instructions that operate on one-dimensional arrays of
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floating-point values. Both single- and double-precision operations are
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supported.
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Option implementation by CPU was as follows:
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2114 2115 2116 2100 1000-M 1000-E 1000-F
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------ ------ ------ ------ ------ ------ ------
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N/A N/A N/A N/A N/A N/A 12824A
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The routines are mapped to instruction codes as follows:
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Single-Precision Double-Precision
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Instr. Opcode Subcod Instr. Opcode Subcod Description
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------ ------ ------ ------ ------ ------ -----------------------------
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VADD 101460 000000 DVADD 105460 004002 Vector add
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VSUB 101460 000020 DVSUB 105460 004022 Vector subtract
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VMPY 101460 000040 DVMPY 105460 004042 Vector multiply
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VDIV 101460 000060 DVDIV 105460 004062 Vector divide
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VSAD 101460 000400 DVSAD 105460 004402 Scalar-vector add
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VSSB 101460 000420 DVSSB 105460 004422 Scalar-vector subtract
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VSMY 101460 000440 DVSMY 105460 004442 Scalar-vector multiply
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VSDV 101460 000460 DVSDV 105460 004462 Scalar-vector divide
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VPIV 101461 0xxxxx DVPIV 105461 0xxxxx Vector pivot
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VABS 101462 0xxxxx DVABS 105462 0xxxxx Vector absolute value
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VSUM 101463 0xxxxx DVSUM 105463 0xxxxx Vector sum
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VNRM 101464 0xxxxx DVNRM 105464 0xxxxx Vector norm
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VDOT 101465 0xxxxx DVDOT 105465 0xxxxx Vector dot product
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VMAX 101466 0xxxxx DVMAX 105466 0xxxxx Vector maximum value
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VMAB 101467 0xxxxx DVMAB 105467 0xxxxx Vector maximum absolute value
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VMIN 101470 0xxxxx DVMIN 105470 0xxxxx Vector minimum value
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VMIB 101471 0xxxxx DVMIB 105471 0xxxxx Vector minimum absolute value
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VMOV 101472 0xxxxx DVMOV 105472 0xxxxx Vector move
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VSWP 101473 0xxxxx DVSWP 105473 0xxxxx Vector swap
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.ERES 101474 -- -- -- -- Resolve array element address
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.ESEG 101475 -- -- -- -- Load MSEG maps
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.VSET 101476 -- -- -- -- Vector setup
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[test] -- -- -- 105477 -- [self test]
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Instructions use IR bit 11 to select single- or double-precision format. The
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double-precision instruction names begin with "D" (e.g., DVADD vs. VADD).
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Most VIS instructions are two words in length, with a sub-opcode immediately
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following the primary opcode.
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Notes:
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1. The .VECT (101460) and .DVCT (105460) opcodes preface a single- or
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double-precision arithmetic operation that is determined by the
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sub-opcode value. The remainder of the dual-precision sub-opcode values
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are "don't care," except for requiring a zero in bit 15.
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2. The VIS uses the hardware FPP of the F-Series. FPP malfunctions are
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detected by the VIS firmware and are indicated by a memory-protect
|
|
violation and setting the overflow flag. Under simulation,
|
|
malfunctions cannot occur.
|
|
|
|
3. VIS ROM data are available from Bitsavers.
|
|
|
|
Additional references:
|
|
- 12824A Vector Instruction Set User's Manual (12824-90001, Jun-1979).
|
|
*/
|
|
|
|
static const OP_PAT op_vis[16] = {
|
|
OP_N, OP_N, OP_N, OP_N, /* --- --- --- --- */
|
|
OP_N, OP_N, OP_N, OP_N, /* --- --- --- --- */
|
|
OP_N, OP_N, OP_N, OP_N, /* --- --- --- --- */
|
|
OP_N, OP_N, OP_N, OP_N /* --- --- --- --- */
|
|
};
|
|
|
|
t_stat cpu_vis (uint32 IR, uint32 intrq)
|
|
{
|
|
t_stat reason = SCPE_OK;
|
|
OPS op;
|
|
uint32 entry;
|
|
|
|
if ((cpu_unit.flags & UNIT_VIS) == 0) /* VIS option installed? */
|
|
return stop_inst;
|
|
|
|
entry = IR & 017; /* mask to entry point */
|
|
|
|
if (op_vis[entry] != OP_N)
|
|
if (reason = cpu_ops (op_vis[entry], op, intrq)) /* get instruction operands */
|
|
return reason;
|
|
|
|
switch (entry) { /* decode IR<3:0> */
|
|
|
|
default: /* others undefined */
|
|
reason = stop_inst;
|
|
}
|
|
|
|
return reason;
|
|
}
|
|
|
|
|
|
/* SIGNAL/1000 Instructions
|
|
|
|
The SIGNAL/1000 instructions provide fast Fourier transforms and complex
|
|
arithmetic. They utilize the F-Series floating-point processor and the
|
|
Vector Instruction Set.
|
|
|
|
Option implementation by CPU was as follows:
|
|
|
|
2114 2115 2116 2100 1000-M 1000-E 1000-F
|
|
------ ------ ------ ------ ------ ------ ------
|
|
N/A N/A N/A N/A N/A N/A 92835A
|
|
|
|
The routines are mapped to instruction codes as follows:
|
|
|
|
Instr. 1000-F Description
|
|
------ ------ ----------------------------------------------
|
|
BITRV 105600 Bit reversal
|
|
BTRFY 105601 Butterfly algorithm
|
|
UNSCR 105602 Unscramble for phasor MPY
|
|
PRSCR 105603 Unscramble for phasor MPY
|
|
BITR1 105604 Swap two elements in array (alternate format)
|
|
BTRF1 105605 Butterfly algorithm (alternate format)
|
|
.CADD 105606 Complex number addition
|
|
.CSUB 105607 Complex number subtraction
|
|
.CMPY 105610 Complex number multiplication
|
|
.CDIV 105611 Complex number division
|
|
CONJG 105612 Complex conjugate
|
|
..CCM 105613 Complex complement
|
|
AIMAG 105614 Return imaginary part
|
|
CMPLX 105615 Form complex number
|
|
[nop] 105616 [no operation]
|
|
[test] 105617 [self test]
|
|
|
|
Notes:
|
|
|
|
1. SIGNAL/1000 ROM data are available from Bitsavers.
|
|
|
|
Additional references (documents unavailable):
|
|
- HP Signal/1000 User Reference and Installation Manual (92835-90002).
|
|
*/
|
|
|
|
static const OP_PAT op_signal[16] = {
|
|
OP_N, OP_N, OP_N, OP_N, /* --- --- --- --- */
|
|
OP_N, OP_N, OP_N, OP_N, /* --- --- --- --- */
|
|
OP_N, OP_N, OP_N, OP_N, /* --- --- --- --- */
|
|
OP_N, OP_N, OP_N, OP_N /* --- --- --- --- */
|
|
};
|
|
|
|
t_stat cpu_signal (uint32 IR, uint32 intrq)
|
|
{
|
|
t_stat reason = SCPE_OK;
|
|
OPS op;
|
|
uint32 entry;
|
|
|
|
if ((cpu_unit.flags & UNIT_SIGNAL) == 0) /* SIGNAL option installed? */
|
|
return stop_inst;
|
|
|
|
entry = IR & 017; /* mask to entry point */
|
|
|
|
if (op_signal[entry] != OP_N)
|
|
if (reason = cpu_ops (op_signal[entry], op, intrq)) /* get instruction operands */
|
|
return reason;
|
|
|
|
switch (entry) { /* decode IR<3:0> */
|
|
|
|
default: /* others undefined */
|
|
reason = stop_inst;
|
|
}
|
|
|
|
return reason;
|
|
}
|