53d02f7fa7
1. New Features 1.1 3.7-0 1.1.1 SCP - Added SET THROTTLE and SET NOTHROTTLE commands to regulate simulator execution rate and host resource utilization. - Added idle support (based on work by Mark Pizzolato). - Added -e to control error processing in nested DO commands (from Dave Bryan). 1.1.2 HP2100 - Added Double Integer instructions, 1000-F CPU, and Floating Point Processor (from Dave Bryan). - Added 2114 and 2115 CPUs, 12607B and 12578A DMA controllers, and 21xx binary loader protection (from Dave Bryan). 1.1.3 Interdata - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state. 1.1.4 PDP-11 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (WAIT instruction executed). - Added TA11/TU60 cassette support. 1.1.5 PDP-8 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (keyboard poll loop or jump-to-self). - Added TA8E/TU60 cassette support. 1.1.6 PDP-1 - Added support for 16-channel sequence break system. - Added support for PDP-1D extended features and timesharing clock. - Added support for Type 630 data communications subsystem. 1.1.6 PDP-4/7/9/15 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (keyboard poll loop or jump-to-self). 1.1.7 VAX, VAX780 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (more than 200 cycles at IPL's 0, 1, or 3 in kernel mode). 1.1.8 PDP-10 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (operating system dependent). - Added CD20 (CD11) support. 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h.
308 lines
17 KiB
C
308 lines
17 KiB
C
/* hp2100_defs.h: HP 2100 simulator definitions
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Copyright (c) 1993-2007, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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11-Jan-07 JDB Added 12578A DMA byte packing to DMA structure
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28-Dec-06 JDB Added CRS backplane signal as I/O pseudo-opcode
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Added DMASK32 32-bit mask value
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21-Dec-06 JDB Changed MEM_ADDR_OK for 21xx loader support
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12-Sep-06 JDB Define NOTE_IOG to recalc interrupts after instr exec
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Rename STOP_INDINT to NOTE_INDINT (not a stop condition)
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30-Dec-04 JDB Added IBL_DS_HEAD head number mask
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19-Nov-04 JDB Added STOP_OFFLINE, STOP_PWROFF stop codes
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25-Apr-04 RMS Added additional IBL definitions
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Added DMA EDT I/O pseudo-opcode
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25-Apr-03 RMS Revised for extended file support
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24-Oct-02 RMS Added indirect address interrupt
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08-Feb-02 RMS Added DMS definitions
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01-Feb-02 RMS Added terminal multiplexor support
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16-Jan-02 RMS Added additional device support
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30-Nov-01 RMS Added extended SET/SHOW support
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15-Oct-00 RMS Added dynamic device numbers
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14-Apr-99 RMS Changed t_addr to unsigned
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The author gratefully acknowledges the help of Jeff Moffat in answering
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questions about the HP2100; and of Dave Bryan in adding features and
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correcting errors throughout the simulator.
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*/
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#ifndef _HP2100_DEFS_H_
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#define _HP2100_DEFS_H_ 0
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#include "sim_defs.h" /* simulator defns */
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/* Simulator stop and notification codes */
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#define STOP_RSRV 1 /* must be 1 */
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#define STOP_IODV 2 /* must be 2 */
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#define STOP_HALT 3 /* HALT */
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#define STOP_IBKPT 4 /* breakpoint */
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#define STOP_IND 5 /* indirect loop */
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#define NOTE_INDINT 6 /* indirect intr */
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#define STOP_NOCONN 7 /* no connection */
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#define STOP_OFFLINE 8 /* device offline */
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#define STOP_PWROFF 9 /* device powered off */
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#define NOTE_IOG 10 /* I/O instr executed */
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#define ABORT_PRO 1 /* protection abort */
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/* Memory */
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#define MEMSIZE (cpu_unit.capac) /* actual memory size */
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#define MEM_ADDR_OK(x) (((uint32) (x)) < fwanxm)
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#define VA_N_SIZE 15 /* virtual addr size */
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#define VASIZE (1 << VA_N_SIZE)
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#define VAMASK 077777 /* virt addr mask */
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#define PA_N_SIZE 20 /* phys addr size */
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#define PASIZE (1 << PA_N_SIZE)
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#define PAMASK (PASIZE - 1) /* phys addr mask */
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/* Architectural constants */
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#define SIGN32 020000000000 /* 32b sign */
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#define DMASK32 037777777777 /* 32b data mask */
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#define SIGN 0100000 /* 16b sign */
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#define DMASK 0177777 /* 16b data mask */
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#define DMASK8 0377 /* 8b data mask */
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#define AR ABREG[0] /* A = reg 0 */
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#define BR ABREG[1] /* B = reg 1 */
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#define SEXT(x) ((int32) (((x) & SIGN)? ((x) | ~DMASK): ((x) & DMASK)))
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/* Memory reference instructions */
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#define I_IA 0100000 /* indirect address */
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#define I_AB 0004000 /* A/B select */
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#define I_CP 0002000 /* current page */
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#define I_DISP 0001777 /* page displacement */
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#define I_PAGENO 0076000 /* page number */
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/* Other instructions */
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#define I_NMRMASK 0172000 /* non-mrf opcode */
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#define I_SRG 0000000 /* shift */
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#define I_ASKP 0002000 /* alter/skip */
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#define I_EXTD 0100000 /* extend */
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#define I_IO 0102000 /* I/O */
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#define I_CTL 0004000 /* CTL on/off */
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#define I_HC 0001000 /* hold/clear */
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#define I_DEVMASK 0000077 /* device mask */
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#define I_GETIOOP(x) (((x) >> 6) & 07) /* I/O sub op */
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/* DMA channels */
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#define DMA_OE 020000000000 /* byte packing odd/even flag */
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#define DMA1_STC 0100000 /* DMA - issue STC */
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#define DMA1_PB 0040000 /* DMA - pack bytes */
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#define DMA1_CLC 0020000 /* DMA - issue CLC */
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#define DMA2_OI 0100000 /* DMA - output/input */
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struct DMA { /* DMA channel */
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uint32 cw1; /* device select */
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uint32 cw2; /* direction, address */
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uint32 cw3; /* word count */
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uint32 latency; /* 1st cycle delay */
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uint32 packer; /* byte-packer holding reg */
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};
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/* Memory management */
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#define VA_N_OFF 10 /* offset width */
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#define VA_M_OFF ((1 << VA_N_OFF) - 1) /* offset mask */
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#define VA_GETOFF(x) ((x) & VA_M_OFF)
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#define VA_N_PAG (VA_N_SIZE - VA_N_OFF) /* page width */
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#define VA_V_PAG (VA_N_OFF)
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#define VA_M_PAG ((1 << VA_N_PAG) - 1)
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#define VA_GETPAG(x) (((x) >> VA_V_PAG) & VA_M_PAG)
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/* Maps */
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#define MAP_NUM 4 /* num maps */
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#define MAP_LNT (1 << VA_N_PAG) /* map length */
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#define MAP_MASK ((MAP_NUM * MAP_LNT) - 1)
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#define SMAP 0 /* system map */
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#define UMAP (SMAP + MAP_LNT) /* user map */
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#define PAMAP (UMAP + MAP_LNT) /* port A map */
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#define PBMAP (PAMAP + MAP_LNT) /* port B map */
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/* DMS map entries */
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#define MAP_V_RPR 15 /* read prot */
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#define MAP_V_WPR 14 /* write prot */
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#define RD (1 << MAP_V_RPR)
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#define WR (1 << MAP_V_WPR)
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#define MAP_MBZ 0036000 /* must be zero */
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#define MAP_N_PAG (PA_N_SIZE - VA_N_OFF) /* page width */
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#define MAP_V_PAG (VA_N_OFF)
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#define MAP_M_PAG ((1 << MAP_N_PAG) - 1)
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#define MAP_GETPAG(x) (((x) & MAP_M_PAG) << MAP_V_PAG)
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/* Map status register */
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#define MST_ENBI 0100000 /* mem enb @ int */
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#define MST_UMPI 0040000 /* usr map @ int */
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#define MST_ENB 0020000 /* mem enb */
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#define MST_UMP 0010000 /* usr map */
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#define MST_PRO 0004000 /* protection */
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#define MST_FLT 0002000 /* fence comp */
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#define MST_FENCE 0001777 /* base page fence */
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/* Map violation register */
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#define MVI_V_RPR 15 /* must be same as */
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#define MVI_V_WPR 14 /* MAP_V_xPR */
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#define MVI_RPR (1 << MVI_V_RPR) /* rd viol */
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#define MVI_WPR (1 << MVI_V_WPR) /* wr viol */
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#define MVI_BPG 0020000 /* base page viol */
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#define MVI_PRV 0010000 /* priv viol */
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#define MVI_MEB 0000200 /* me bus enb @ viol */
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#define MVI_MEM 0000100 /* mem enb @ viol */
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#define MVI_UMP 0000040 /* usr map @ viol */
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#define MVI_PAG 0000037 /* pag sel */
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/* Timers */
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#define TMR_CLK 0 /* clock */
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#define TMR_MUX 1 /* multiplexor */
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/* I/O sub-opcodes */
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#define ioHLT 0 /* halt */
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#define ioFLG 1 /* set/clear flag */
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#define ioSFC 2 /* skip on flag clear */
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#define ioSFS 3 /* skip on flag set */
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#define ioMIX 4 /* merge into A/B */
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#define ioLIX 5 /* load into A/B */
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#define ioOTX 6 /* output from A/B */
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#define ioCTL 7 /* set/clear control */
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#define ioEDT 8 /* DMA: end data transfer */
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#define ioCRS 9 /* control reset ("CLC 0") */
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/* I/O devices - fixed assignments */
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#define CPU 000 /* interrupt control */
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#define OVF 001 /* overflow */
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#define DMALT0 002 /* DMA 0 alternate */
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#define DMALT1 003 /* DMA 1 alternate */
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#define PWR 004 /* power fail */
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#define PRO 005 /* parity/mem protect */
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#define DMA0 006 /* DMA channel 0 */
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#define DMA1 007 /* DMA channel 1 */
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#define VARDEV (DMA1 + 1) /* start of var assign */
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#define M_NXDEV (INT_M (CPU) | INT_M (OVF) | \
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INT_M (DMALT0) | INT_M (DMALT1))
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#define M_FXDEV (M_NXDEV | INT_M (PWR) | INT_M (PRO) | \
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INT_M (DMA0) | INT_M (DMA1))
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/* I/O devices - variable assignment defaults */
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#define PTR 010 /* 12597A-002 paper tape reader */
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#define TTY 011 /* 12531C teleprinter */
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#define PTP 012 /* 12597A-005 paper tape punch */
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#define CLK 013 /* 12539C time-base generator */
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#define LPS 014 /* 12653A line printer */
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#define LPT 015 /* 12845A line printer */
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#define MTD 020 /* 12559A data */
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#define MTC 021 /* 12559A control */
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#define DPD 022 /* 12557A data */
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#define DPC 023 /* 12557A control */
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#define DQD 024 /* 12565A data */
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#define DQC 025 /* 12565A control */
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#define DRD 026 /* 12610A data */
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#define DRC 027 /* 12610A control */
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#define MSD 030 /* 13181A data */
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#define MSC 031 /* 13181A control */
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#define IPLI 032 /* 12566B link in */
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#define IPLO 033 /* 12566B link out */
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#define DS 034 /* 13037A control */
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#define MUXL 040 /* 12920A lower data */
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#define MUXU 041 /* 12920A upper data */
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#define MUXC 042 /* 12920A control */
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/* IBL assignments */
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#define IBL_V_SEL 14 /* ROM select */
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#define IBL_M_SEL 03
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#define IBL_PTR 0000000 /* PTR */
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#define IBL_DP 0040000 /* disk: DP */
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#define IBL_DQ 0060000 /* disk: DQ */
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#define IBL_MS 0100000 /* option 0: MS */
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#define IBL_DS 0140000 /* option 1: DS */
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#define IBL_MAN 0010000 /* RPL/man boot */
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#define IBL_V_DEV 6 /* dev in <11:6> */
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#define IBL_OPT 0000070 /* options in <5:3> */
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#define IBL_DP_REM 0000001 /* DP removable */
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#define IBL_DS_HEAD 0000003 /* DS head number */
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#define IBL_LNT 64 /* boot length */
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#define IBL_MASK (IBL_LNT - 1) /* boot length mask */
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#define IBL_DPC (IBL_LNT - 2) /* DMA ctrl word */
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#define IBL_END (IBL_LNT - 1) /* last location */
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/* Dynamic device information table */
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typedef struct {
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uint32 devno; /* device number */
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uint32 cmd; /* saved command */
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uint32 ctl; /* saved control */
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uint32 flg; /* saved flag */
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uint32 fbf; /* saved flag buf */
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uint32 srq; /* saved svc req */
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int32 (*iot)(int32 op, int32 ir, int32 dat); /* I/O routine */
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} DIB;
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/* I/O macros */
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#define INT_V(x) ((x) & 037) /* device bit pos */
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#define INT_M(x) (1u << INT_V (x)) /* device bit mask */
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#define setCMD(D) dev_cmd[(D)/32] = dev_cmd[(D)/32] | INT_M ((D))
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#define clrCMD(D) dev_cmd[(D)/32] = dev_cmd[(D)/32] & ~INT_M (D)
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#define setCTL(D) dev_ctl[(D)/32] = dev_ctl[(D)/32] | INT_M ((D))
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#define clrCTL(D) dev_ctl[(D)/32] = dev_ctl[(D)/32] & ~INT_M (D)
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#define setFBF(D) dev_fbf[(D)/32] = dev_fbf[(D)/32] | INT_M (D)
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#define clrFBF(D) dev_fbf[(D)/32] = dev_fbf[(D)/32] & ~INT_M (D)
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#define setFLG(D) dev_flg[(D)/32] = dev_flg[(D)/32] | INT_M (D); \
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setFBF(D)
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#define clrFLG(D) dev_flg[(D)/32] = dev_flg[(D)/32] & ~INT_M (D); \
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clrFBF(D)
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#define setFSR(D) dev_flg[(D)/32] = dev_flg[(D)/32] | INT_M (D); \
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setFBF(D); setSRQ(D)
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#define clrFSR(D) dev_flg[(D)/32] = dev_flg[(D)/32] & ~INT_M (D); \
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clrFBF(D); clrSRQ(D)
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#define setSRQ(D) dev_srq[(D)/32] = dev_srq[(D)/32] | INT_M ((D))
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#define clrSRQ(D) dev_srq[(D)/32] = dev_srq[(D)/32] & ~INT_M (D)
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#define CMD(D) ((dev_cmd[(D)/32] >> INT_V (D)) & 1)
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#define CTL(D) ((dev_ctl[(D)/32] >> INT_V (D)) & 1)
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#define FLG(D) ((dev_flg[(D)/32] >> INT_V (D)) & 1)
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#define FBF(D) ((dev_fbf[(D)/32] >> INT_V (D)) & 1)
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#define SRQ(D) ((dev_srq[(D)/32] >> INT_V (D)) & 1)
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#define IOT_V_REASON 16
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#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* stop on error */
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/* Function prototypes */
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t_stat ibl_copy (const uint16 pboot[IBL_LNT], int32 dev);
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t_stat hp_setdev (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat hp_showdev (FILE *st, UNIT *uptr, int32 val, void *desc);
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void hp_enbdis_pair (DEVICE *ccp, DEVICE *dcp);
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#endif
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