53d02f7fa7
1. New Features 1.1 3.7-0 1.1.1 SCP - Added SET THROTTLE and SET NOTHROTTLE commands to regulate simulator execution rate and host resource utilization. - Added idle support (based on work by Mark Pizzolato). - Added -e to control error processing in nested DO commands (from Dave Bryan). 1.1.2 HP2100 - Added Double Integer instructions, 1000-F CPU, and Floating Point Processor (from Dave Bryan). - Added 2114 and 2115 CPUs, 12607B and 12578A DMA controllers, and 21xx binary loader protection (from Dave Bryan). 1.1.3 Interdata - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state. 1.1.4 PDP-11 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (WAIT instruction executed). - Added TA11/TU60 cassette support. 1.1.5 PDP-8 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (keyboard poll loop or jump-to-self). - Added TA8E/TU60 cassette support. 1.1.6 PDP-1 - Added support for 16-channel sequence break system. - Added support for PDP-1D extended features and timesharing clock. - Added support for Type 630 data communications subsystem. 1.1.6 PDP-4/7/9/15 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (keyboard poll loop or jump-to-self). 1.1.7 VAX, VAX780 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (more than 200 cycles at IPL's 0, 1, or 3 in kernel mode). 1.1.8 PDP-10 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (operating system dependent). - Added CD20 (CD11) support. 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h.
527 lines
21 KiB
C
527 lines
21 KiB
C
/* hp2100_ipl.c: HP 2000 interprocessor link simulator
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Copyright (c) 2002-2006, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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ipli, iplo 12566B interprocessor link pair
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28-Dec-06 JDB Added ioCRS state to I/O decoders (action unverified)
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16-Aug-05 RMS Fixed C++ declaration and cast problems
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07-Oct-04 JDB Fixed enable/disable from either device
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26-Apr-04 RMS Fixed SFS x,C and SFC x,C
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Implemented DMA SRQ (follows FLG)
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21-Dec-03 RMS Adjusted ipl_ptime for TSB (from Mike Gemeny)
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09-May-03 RMS Added network device flag
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31-Jan-03 RMS Links are full duplex (found by Mike Gemeny)
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*/
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#include "hp2100_defs.h"
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#include "sim_sock.h"
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#include "sim_tmxr.h"
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#define UNIT_V_DIAG (UNIT_V_UF + 0) /* diagnostic mode */
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#define UNIT_V_ACTV (UNIT_V_UF + 1) /* making connection */
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#define UNIT_V_ESTB (UNIT_V_UF + 2) /* connection established */
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#define UNIT_V_HOLD (UNIT_V_UF + 3) /* character holding */
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#define UNIT_DIAG (1 << UNIT_V_DIAG)
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#define UNIT_ACTV (1 << UNIT_V_ACTV)
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#define UNIT_ESTB (1 << UNIT_V_ESTB)
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#define UNIT_HOLD (1 << UNIT_V_HOLD)
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#define IBUF buf /* input buffer */
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#define OBUF wait /* output buffer */
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#define DSOCKET u3 /* data socket */
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#define LSOCKET u4 /* listening socket */
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extern uint32 PC;
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extern uint32 dev_cmd[2], dev_ctl[2], dev_flg[2], dev_fbf[2], dev_srq[2];
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extern FILE *sim_log;
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int32 ipl_ptime = 31; /* polling interval */
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int32 ipl_stopioe = 0; /* stop on error */
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int32 ipl_hold[2] = { 0 }; /* holding character */
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DEVICE ipli_dev, iplo_dev;
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int32 ipliio (int32 inst, int32 IR, int32 dat);
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int32 iploio (int32 inst, int32 IR, int32 dat);
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int32 iplio (UNIT *uptr, int32 inst, int32 IR, int32 dat);
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t_stat ipl_svc (UNIT *uptr);
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t_stat ipl_reset (DEVICE *dptr);
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t_stat ipl_attach (UNIT *uptr, char *cptr);
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t_stat ipl_detach (UNIT *uptr);
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t_stat ipl_boot (int32 unitno, DEVICE *dptr);
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t_stat ipl_dscln (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat ipl_setdiag (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_bool ipl_check_conn (UNIT *uptr);
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/* IPLI data structures
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ipli_dev IPLI device descriptor
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ipli_unit IPLI unit descriptor
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ipli_reg IPLI register list
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*/
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DIB ipl_dib[] = {
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{ IPLI, 0, 0, 0, 0, 0, &ipliio },
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{ IPLO, 0, 0, 0, 0, 0, &iploio }
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};
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#define ipli_dib ipl_dib[0]
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#define iplo_dib ipl_dib[1]
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UNIT ipl_unit[] = {
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{ UDATA (&ipl_svc, UNIT_ATTABLE, 0) },
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{ UDATA (&ipl_svc, UNIT_ATTABLE, 0) }
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};
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#define ipli_unit ipl_unit[0]
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#define iplo_unit ipl_unit[1]
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REG ipli_reg[] = {
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{ ORDATA (IBUF, ipli_unit.IBUF, 16) },
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{ ORDATA (OBUF, ipli_unit.OBUF, 16) },
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{ FLDATA (CMD, ipli_dib.cmd, 0) },
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{ FLDATA (CTL, ipli_dib.ctl, 0) },
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{ FLDATA (FLG, ipli_dib.flg, 0) },
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{ FLDATA (FBF, ipli_dib.fbf, 0) },
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{ FLDATA (SRQ, ipli_dib.srq, 0) },
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{ ORDATA (HOLD, ipl_hold[0], 8) },
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{ DRDATA (TIME, ipl_ptime, 24), PV_LEFT },
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{ FLDATA (STOP_IOE, ipl_stopioe, 0) },
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{ ORDATA (DEVNO, ipli_dib.devno, 6), REG_HRO },
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{ NULL }
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};
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MTAB ipl_mod[] = {
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{ UNIT_DIAG, UNIT_DIAG, "diagnostic mode", "DIAG", &ipl_setdiag },
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{ UNIT_DIAG, 0, "link mode", "LINK", &ipl_setdiag },
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{ MTAB_XTD | MTAB_VDV, 0, NULL, "DISCONNECT",
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&ipl_dscln, NULL, NULL },
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{ MTAB_XTD | MTAB_VDV, 1, "DEVNO", "DEVNO",
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&hp_setdev, &hp_showdev, &ipli_dev },
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{ 0 }
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};
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DEVICE ipli_dev = {
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"IPLI", &ipli_unit, ipli_reg, ipl_mod,
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1, 10, 31, 1, 16, 16,
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&tmxr_ex, &tmxr_dep, &ipl_reset,
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&ipl_boot, &ipl_attach, &ipl_detach,
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&ipli_dib, DEV_NET | DEV_DISABLE | DEV_DIS
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};
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/* IPLO data structures
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iplo_dev IPLO device descriptor
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iplo_unit IPLO unit descriptor
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iplo_reg IPLO register list
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*/
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REG iplo_reg[] = {
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{ ORDATA (IBUF, iplo_unit.IBUF, 16) },
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{ ORDATA (OBUF, iplo_unit.OBUF, 16) },
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{ FLDATA (CMD, iplo_dib.cmd, 0) },
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{ FLDATA (CTL, iplo_dib.ctl, 0) },
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{ FLDATA (FLG, iplo_dib.flg, 0) },
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{ FLDATA (FBF, iplo_dib.fbf, 0) },
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{ FLDATA (SRQ, iplo_dib.srq, 0) },
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{ ORDATA (HOLD, ipl_hold[1], 8) },
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{ DRDATA (TIME, ipl_ptime, 24), PV_LEFT },
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{ ORDATA (DEVNO, iplo_dib.devno, 6), REG_HRO },
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{ NULL }
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};
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DEVICE iplo_dev = {
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"IPLO", &iplo_unit, iplo_reg, ipl_mod,
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1, 10, 31, 1, 16, 16,
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&tmxr_ex, &tmxr_dep, &ipl_reset,
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&ipl_boot, &ipl_attach, &ipl_detach,
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&iplo_dib, DEV_NET | DEV_DISABLE | DEV_DIS
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};
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/* I/O instructions */
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int32 ipliio (int32 inst, int32 IR, int32 dat)
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{
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return iplio (&ipli_unit, inst, IR, dat);
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}
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int32 iploio (int32 inst, int32 IR, int32 dat)
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{
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return iplio (&iplo_unit, inst, IR, dat);
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}
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int32 iplio (UNIT *uptr, int32 inst, int32 IR, int32 dat)
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{
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uint32 u, dev, odev;
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int32 sta;
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char msg[2];
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dev = IR & I_DEVMASK; /* get device no */
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switch (inst) { /* case on opcode */
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case ioFLG: /* flag clear/set */
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if ((IR & I_HC) == 0) { setFSR (dev); } /* STF */
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break;
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case ioSFC: /* skip flag clear */
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if (FLG (dev) == 0) PC = (PC + 1) & VAMASK;
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break;
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case ioSFS: /* skip flag set */
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if (FLG (dev) != 0) PC = (PC + 1) & VAMASK;
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break;
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case ioOTX: /* output */
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uptr->OBUF = dat;
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break;
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case ioLIX: /* load */
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dat = uptr->IBUF; /* return val */
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break;
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case ioMIX: /* merge */
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dat = dat | uptr->IBUF; /* get return data */
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break;
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case ioCRS: /* control reset (action unverif) */
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case ioCTL: /* control clear/set */
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if (IR & I_CTL) { /* CLC */
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clrCMD (dev); /* clear ctl, cmd */
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clrCTL (dev);
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}
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else { /* STC */
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setCMD (dev); /* set ctl, cmd */
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setCTL (dev);
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if (uptr->flags & UNIT_ATT) { /* attached? */
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if ((uptr->flags & UNIT_ESTB) == 0) { /* established? */
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if (!ipl_check_conn (uptr)) /* not established? */
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return STOP_NOCONN; /* lose */
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uptr->flags = uptr->flags | UNIT_ESTB;
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}
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msg[0] = (uptr->OBUF >> 8) & 0377;
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msg[1] = uptr->OBUF & 0377;
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sta = sim_write_sock (uptr->DSOCKET, msg, 2);
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if (sta == SOCKET_ERROR) {
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printf ("IPL: socket write error\n");
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return SCPE_IOERR;
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}
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sim_os_sleep (0);
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}
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else if (uptr->flags & UNIT_DIAG) { /* diagnostic mode? */
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u = (uptr - ipl_unit) ^ 1; /* find other device */
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ipl_unit[u].IBUF = uptr->OBUF; /* output to other */
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odev = ipl_dib[u].devno; /* other device no */
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setFSR (odev); /* set other flag */
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}
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else return SCPE_UNATT; /* lose */
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}
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break;
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default:
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break;
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}
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if (IR & I_HC) { clrFSR (dev); } /* H/C option */
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return dat;
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}
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/* Unit service - poll for input */
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t_stat ipl_svc (UNIT *uptr)
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{
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int32 u, nb, dev;
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char msg[2];
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u = uptr - ipl_unit; /* get link number */
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if ((uptr->flags & UNIT_ATT) == 0) return SCPE_OK; /* not attached? */
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sim_activate (uptr, ipl_ptime); /* reactivate */
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if ((uptr->flags & UNIT_ESTB) == 0) { /* not established? */
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if (!ipl_check_conn (uptr)) return SCPE_OK; /* check for conn */
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uptr->flags = uptr->flags | UNIT_ESTB;
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}
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nb = sim_read_sock (uptr->DSOCKET, msg, ((uptr->flags & UNIT_HOLD)? 1: 2));
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if (nb < 0) { /* connection closed? */
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printf ("IPL: socket read error\n");
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return SCPE_IOERR;
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}
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if (nb == 0) return SCPE_OK; /* no data? */
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if (uptr->flags & UNIT_HOLD) { /* holdover byte? */
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uptr->IBUF = (ipl_hold[u] << 8) | (((int32) msg[0]) & 0377);
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uptr->flags = uptr->flags & ~UNIT_HOLD;
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}
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else if (nb == 1) {
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ipl_hold[u] = ((int32) msg[0]) & 0377;
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uptr->flags = uptr->flags | UNIT_HOLD;
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}
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else uptr->IBUF = ((((int32) msg[0]) & 0377) << 8) |
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(((int32) msg[1]) & 0377);
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dev = ipl_dib[u].devno; /* get device number */
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clrCMD (dev); /* clr cmd, set flag */
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setFSR (dev);
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return SCPE_OK;
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}
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t_bool ipl_check_conn (UNIT *uptr)
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{
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SOCKET sock;
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if (uptr->flags & UNIT_ESTB) return TRUE; /* established? */
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if (uptr->flags & UNIT_ACTV) { /* active connect? */
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if (sim_check_conn (uptr->DSOCKET, 0) <= 0) return FALSE;
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}
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else {
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sock = sim_accept_conn (uptr->LSOCKET, NULL); /* poll connect */
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if (sock == INVALID_SOCKET) return FALSE; /* got a live one? */
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uptr->DSOCKET = sock; /* save data socket */
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}
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uptr->flags = uptr->flags | UNIT_ESTB; /* conn established */
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return TRUE;
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}
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/* Reset routine */
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t_stat ipl_reset (DEVICE *dptr)
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{
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DIB *dibp = (DIB *) dptr->ctxt;
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UNIT *uptr = dptr->units;
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hp_enbdis_pair (dptr, /* make pair cons */
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(dptr == &ipli_dev)? &iplo_dev: &ipli_dev);
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dibp->cmd = dibp->ctl = 0; /* clear cmd, ctl */
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dibp->flg = dibp->fbf = dibp->srq = 1; /* set flg, fbf, srq */
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uptr->IBUF = uptr->OBUF = 0; /* clr buffers */
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if (uptr->flags & UNIT_ATT) sim_activate (uptr, ipl_ptime);
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else sim_cancel (uptr); /* deactivate unit */
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uptr->flags = uptr->flags & ~UNIT_HOLD;
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return SCPE_OK;
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}
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/* Attach routine
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attach -l - listen for connection on port
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attach -c - connect to ip address and port
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*/
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t_stat ipl_attach (UNIT *uptr, char *cptr)
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{
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extern int32 sim_switches;
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SOCKET newsock;
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uint32 i, t, ipa, ipp, oldf;
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char *tptr;
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t_stat r;
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r = get_ipaddr (cptr, &ipa, &ipp);
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if ((r != SCPE_OK) || (ipp == 0)) return SCPE_ARG;
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oldf = uptr->flags;
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if (oldf & UNIT_ATT) ipl_detach (uptr);
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if ((sim_switches & SWMASK ('C')) ||
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((sim_switches & SIM_SW_REST) && (oldf & UNIT_ACTV))) {
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if (ipa == 0) ipa = 0x7F000001;
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newsock = sim_connect_sock (ipa, ipp);
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if (newsock == INVALID_SOCKET) return SCPE_IOERR;
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printf ("Connecting to IP address %d.%d.%d.%d, port %d\n",
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(ipa >> 24) & 0xff, (ipa >> 16) & 0xff,
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(ipa >> 8) & 0xff, ipa & 0xff, ipp);
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if (sim_log) fprintf (sim_log,
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"Connecting to IP address %d.%d.%d.%d, port %d\n",
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(ipa >> 24) & 0xff, (ipa >> 16) & 0xff,
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(ipa >> 8) & 0xff, ipa & 0xff, ipp);
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uptr->flags = uptr->flags | UNIT_ACTV;
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uptr->LSOCKET = 0;
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uptr->DSOCKET = newsock;
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}
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else {
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if (ipa != 0) return SCPE_ARG;
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newsock = sim_master_sock (ipp);
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if (newsock == INVALID_SOCKET) return SCPE_IOERR;
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printf ("Listening on port %d\n", ipp);
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if (sim_log) fprintf (sim_log, "Listening on port %d\n", ipp);
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uptr->flags = uptr->flags & ~UNIT_ACTV;
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uptr->LSOCKET = newsock;
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uptr->DSOCKET = 0;
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}
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uptr->IBUF = uptr->OBUF = 0;
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uptr->flags = (uptr->flags | UNIT_ATT) & ~(UNIT_ESTB | UNIT_HOLD);
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tptr = (char *) malloc (strlen (cptr) + 1); /* get string buf */
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if (tptr == NULL) { /* no memory? */
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ipl_detach (uptr); /* close sockets */
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return SCPE_MEM;
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}
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strcpy (tptr, cptr); /* copy ipaddr:port */
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uptr->filename = tptr; /* save */
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sim_activate (uptr, ipl_ptime); /* activate poll */
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if (sim_switches & SWMASK ('W')) { /* wait? */
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for (i = 0; i < 30; i++) { /* check for 30 sec */
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if (t = ipl_check_conn (uptr)) break; /* established? */
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if ((i % 10) == 0) /* status every 10 sec */
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printf ("Waiting for connnection\n");
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sim_os_sleep (1); /* sleep 1 sec */
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}
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if (t) printf ("Connection established\n");
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}
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return SCPE_OK;
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}
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/* Detach routine */
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t_stat ipl_detach (UNIT *uptr)
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{
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if (!(uptr->flags & UNIT_ATT)) return SCPE_OK; /* attached? */
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if (uptr->flags & UNIT_ACTV) sim_close_sock (uptr->DSOCKET, 1);
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else {
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if (uptr->flags & UNIT_ESTB) /* if established, */
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sim_close_sock (uptr->DSOCKET, 0); /* close data socket */
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sim_close_sock (uptr->LSOCKET, 1); /* closen listen socket */
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}
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free (uptr->filename); /* free string */
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uptr->filename = NULL;
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uptr->LSOCKET = 0;
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uptr->DSOCKET = 0;
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uptr->flags = uptr->flags & ~(UNIT_ATT | UNIT_ACTV | UNIT_ESTB);
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sim_cancel (uptr); /* don't poll */
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return SCPE_OK;
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}
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/* Disconnect routine */
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t_stat ipl_dscln (UNIT *uptr, int32 val, char *cptr, void *desc)
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{
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if (cptr) return SCPE_ARG;
|
|
if (((uptr->flags & UNIT_ATT) == 0) || (uptr->flags & UNIT_ACTV) ||
|
|
((uptr->flags & UNIT_ESTB) == 0)) return SCPE_NOFNC;
|
|
sim_close_sock (uptr->DSOCKET, 0);
|
|
uptr->DSOCKET = 0;
|
|
uptr->flags = uptr->flags & ~UNIT_ESTB;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Diagnostic/normal mode routine */
|
|
|
|
t_stat ipl_setdiag (UNIT *uptr, int32 val, char *cptr, void *desc)
|
|
{
|
|
if (val) {
|
|
ipli_unit.flags = ipli_unit.flags | UNIT_DIAG;
|
|
iplo_unit.flags = iplo_unit.flags | UNIT_DIAG;
|
|
}
|
|
else {
|
|
ipli_unit.flags = ipli_unit.flags & ~UNIT_DIAG;
|
|
iplo_unit.flags = iplo_unit.flags & ~UNIT_DIAG;
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Interprocessor link bootstrap routine (HP Access Manual) */
|
|
|
|
#define MAX_BASE 073
|
|
#define IPL_PNTR 074
|
|
#define PTR_PNTR 075
|
|
#define IPL_DEVA 076
|
|
#define PTR_DEVA 077
|
|
|
|
static const uint32 pboot[IBL_LNT] = {
|
|
0163774, /*BBL LDA ICK,I ; IPL sel code */
|
|
0027751, /* JMP CFG ; go configure */
|
|
0107700, /*ST CLC 0,C ; intr off */
|
|
0002702, /* CLA,CCE,SZA ; skip in */
|
|
0063772, /*CN LDA M26 ; feed frame */
|
|
0002307, /*EOC CCE,INA,SZA,RSS ; end of file? */
|
|
0027760, /* JMP EOT ; yes */
|
|
0017736, /* JSB READ ; get #char */
|
|
0007307, /* CMB,CCE,INB,SZB,RSS ; 2's comp; null? */
|
|
0027705, /* JMP EOC ; read next */
|
|
0077770, /* STB WC ; word in rec */
|
|
0017736, /* JSB READ ; get feed frame */
|
|
0017736, /* JSB READ ; get address */
|
|
0074000, /* STB 0 ; init csum */
|
|
0077771, /* STB AD ; save addr */
|
|
0067771, /*CK LDB AD ; check addr */
|
|
0047773, /* ADB MAXAD ; below loader */
|
|
0002040, /* SEZ ; E =0 => OK */
|
|
0102055, /* HLT 55 */
|
|
0017736, /* JSB READ ; get word */
|
|
0040001, /* ADA 1 ; cont checksum */
|
|
0177771, /* STB AD,I ; store word */
|
|
0037771, /* ISZ AD */
|
|
0000040, /* CLE ; force wd read */
|
|
0037770, /* ISZ WC ; block done? */
|
|
0027717, /* JMP CK ; no */
|
|
0017736, /* JSB READ ; get checksum */
|
|
0054000, /* CPB 0 ; ok? */
|
|
0027704, /* JMP CN ; next block */
|
|
0102011, /* HLT 11 ; bad csum */
|
|
0000000, /*RD 0 */
|
|
0006600, /* CLB,CME ; E reg byte ptr */
|
|
0103700, /*IO1 STC RDR,C ; start reader */
|
|
0102300, /*IO2 SFS RDR ; wait */
|
|
0027741, /* JMP *-1 */
|
|
0106400, /*IO3 MIB RDR ; get byte */
|
|
0002041, /* SEZ,RSS ; E set? */
|
|
0127736, /* JMP RD,I ; no, done */
|
|
0005767, /* BLF,CLE,BLF ; shift byte */
|
|
0027740, /* JMP IO1 ; again */
|
|
0163775, /* LDA PTR,I ; get ptr code */
|
|
0043765, /*CFG ADA SFS ; config IO */
|
|
0073741, /* STA IO2 */
|
|
0043766, /* ADA STC */
|
|
0073740, /* STA IO1 */
|
|
0043767, /* ADA MIB */
|
|
0073743, /* STA IO3 */
|
|
0027702, /* JMP ST */
|
|
0063777, /*EOT LDA PSC ; put select codes */
|
|
0067776, /* LDB ISC ; where xloader wants */
|
|
0102077, /* HLT 77 */
|
|
0027702, /* JMP ST */
|
|
0000000, /* NOP */
|
|
0102300, /*SFS SFS 0 */
|
|
0001400, /*STC 1400 */
|
|
0002500, /*MIB 2500 */
|
|
0000000, /*WC 0 */
|
|
0000000, /*AD 0 */
|
|
0177746, /*M26 -26 */
|
|
0000000, /*MAX -BBL */
|
|
0007776, /*ICK ISC */
|
|
0007777, /*PTR IPT */
|
|
0000000, /*ISC 0 */
|
|
0000000 /*IPT 0 */
|
|
};
|
|
|
|
t_stat ipl_boot (int32 unitno, DEVICE *dptr)
|
|
{
|
|
int32 i, devi, devp;
|
|
extern DIB ptr_dib;
|
|
extern UNIT cpu_unit;
|
|
extern uint32 SR;
|
|
extern uint16 *M;
|
|
|
|
devi = ipli_dib.devno; /* get device no */
|
|
devp = ptr_dib.devno;
|
|
PC = ((MEMSIZE - 1) & ~IBL_MASK) & VAMASK; /* start at mem top */
|
|
SR = (devi << IBL_V_DEV) | devp; /* set SR */
|
|
for (i = 0; i < IBL_LNT; i++) M[PC + i] = pboot[i]; /* copy bootstrap */
|
|
M[PC + MAX_BASE] = (~PC + 1) & DMASK; /* fix ups */
|
|
M[PC + IPL_PNTR] = M[PC + IPL_PNTR] | PC;
|
|
M[PC + PTR_PNTR] = M[PC + PTR_PNTR] | PC;
|
|
M[PC + IPL_DEVA] = devi;
|
|
M[PC + PTR_DEVA] = devp;
|
|
return SCPE_OK;
|
|
}
|
|
|