535 lines
27 KiB
C
535 lines
27 KiB
C
/* sel32_defs.h: SEL-32 Concept/32 simulator definitions
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Copyright (c) 2018-2022, James C. Bevier
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Portions provided by Richard Cornwell, Geert Rolf and other SIMH contributers
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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JAMES C. BEVIER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "sim_defs.h" /* simh simulator defns */
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/* Simulator stop codes */
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#define STOP_IONRDY 1 /* I/O dev not ready */
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#define STOP_HALT 2 /* HALT */
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#define STOP_IBKPT 3 /* breakpoint */
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#define STOP_UUO 4 /* invalid opcode */
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#define STOP_INVINS 5 /* invalid instr */
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#define STOP_INVIOP 6 /* invalid I/O op */
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#define STOP_INDLIM 7 /* indirect limit */
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#define STOP_XECLIM 8 /* XEC limit */
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#define STOP_IOCHECK 9 /* IOCHECK */
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#define STOP_MMTRP 10 /* mm in trap */
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#define STOP_TRPINS 11 /* trap inst not BRM */
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#define STOP_RTCINS 12 /* rtc inst not MIN/SKR */
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#define STOP_ILLVEC 13 /* zero vector */
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#define STOP_CCT 14 /* runaway CCT */
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/* I/O equates */
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/* Channel sense bytes set by device */
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#define SNS_BSY 0x80 /* Unit Busy */
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#define SNS_SMS 0x40 /* Status modified */
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#define SNS_CTLEND 0x20 /* Control unit end */
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#define SNS_ATTN 0x10 /* Unit attention */
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#define SNS_CHNEND 0x08 /* Channel end */
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#define SNS_DEVEND 0x04 /* Device end */
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#define SNS_UNITCHK 0x02 /* Unit check */
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#define SNS_UNITEXP 0x01 /* Unit exception */
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/* Command masks */
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#define CCMDMSK 0xff000000 /* Mask for command */
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#define CMD_CHAN 0x00 /* Channel control */
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#define CMD_SENSE 0x04 /* Sense channel command */
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#define CMD_TIC 0x08 /* Transfer in channel */
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#define CMD_RDBWD 0x0c /* Read backward */
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/* operation types */
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#define CMD_TYPE 0x03 /* Type mask */
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#define CMD_WRITE 0x01 /* Write command */
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#define CMD_READ 0x02 /* Read command */
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#define CMD_CTL 0x03 /* Control command */
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/* IOCD word 2 status bits */
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#define STATUS_ECHO 0x8000 /* Halt I/O and Stop I/O function */
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#define STATUS_PCI 0x4000 /* Program controlled interrupt */
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#define STATUS_LENGTH 0x2000 /* Incorrect length */
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#define STATUS_PCHK 0x1000 /* Channel program check */
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#define STATUS_CDATA 0x0800 /* Channel data check */
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#define STATUS_CCNTL 0x0400 /* Channel control check */
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#define STATUS_INTER 0x0200 /* Channel interface check */
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#define STATUS_CHAIN 0x0100 /* Channel chain check */
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#define STATUS_BUSY 0x0080 /* Device busy */
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#define STATUS_MOD 0x0040 /* Status modified */
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#define STATUS_CTLEND 0x0020 /* Controller end */
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#define STATUS_ATTN 0x0010 /* Device raised attention */
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#define STATUS_CEND 0x0008 /* Channel end */
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#define STATUS_DEND 0x0004 /* Device end */
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#define STATUS_CHECK 0x0002 /* Unit check */
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#define STATUS_EXPT 0x0001 /* Unit exception */
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#define STATUS_ERROR 0x3f03 /* bad errors */
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//#define STATUS_ERROR (STATUS_LENGTH|STATUS_PCHK|STATUS_CDATA|STATUS_CCNTL|
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// STATUS_INTER|STATUS_CHAIN|STATUS_CHECK|STATUS_EXPT)
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/* Class F channel bits */
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/* bit 32 - 37 of IOCD word 2 (0-5) */
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/* ccw_flags bit assignment */
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#define FLAG_DC 0x8000 /* Data chain */
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#define FLAG_CC 0x4000 /* Chain command */
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#define FLAG_SLI 0x2000 /* Suppress length indicator */
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#define FLAG_SKIP 0x1000 /* Suppress memory write */
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#define FLAG_PCI 0x0800 /* Program controlled interrupt */
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#define FLAG_RTO 0x0400 /* Real-Time Option */
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/* chan_byte bit assignments */
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#define BUFF_EMPTY 0x00 /* Buffer is empty */
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#define BUFF_BUSY 0x04 /* Channel program busy & empty */
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#define BUFF_NEXT 0x0C /* 0x08|0x04 Continue Channel with next IOCB */
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#define BUFF_CHNEND 0x14 /* 0x10|0x04 Channel end */
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#define BUFF_DONE 0x20 /* 0x20 Channel ready for new command */
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#define BUFF_POST 0x24 /* 0x20|0x04 Waiting for status to be posted */
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/* chan_info bit flags */
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#define INFO_SIOCD 0x01 /* Initial IOCD from SIO if set */
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#define INFO_CEND 0x02 /* Channel End (chan_end) called if set */
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/* bits 0-5 unused */
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#define MAX_CHAN 128 /* max channels that can be defined */
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#define SUB_CHANS 256 /* max sub channels that can be defined */
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#define MAX_DEV (MAX_CHAN * SUB_CHANS) /* max possible */
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/* simulator devices configuration */
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#define NUM_DEVS_IOP 1 /* 1 device IOP channel controller */
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#define NUM_UNITS_IOP 1 /* 1 master IOP channel device */
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#define NUM_DEVS_MFP 1 /* 1 device MFP channel controller */
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#define NUM_UNITS_MFP 1 /* 1 master MFP channel device */
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#define NUM_DEVS_COM 2 /* 8-Line async controller */
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#define NUM_UNITS_COM 16 /* 8-Line async units */
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#define NUM_DEVS_CON 1 /* 1 I/O console controller */
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#define NUM_UNITS_CON 2 /* 2 console input & output */
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#define NUM_DEVS_MT 1 /* 1 mag tape controllers */
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#define NUM_UNITS_MT 4 /* 4 of 8 devices */
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#define NUM_DEVS_HSDP 1 /* 1 hspd disk drive controller */
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//#define NUM_UNITS_HSDP 2 /* 2 disk drive devices */
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#define NUM_UNITS_HSDP 4 /* 4 disk drive devices */
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#define NUM_DEVS_DISK 1 /* 1 dp02 disk drive controller */
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//#define NUM_UNITS_DISK 2 /* 2 disk drive devices */
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#define NUM_UNITS_DISK 4 /* 4 disk drive devices */
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#define NUM_DEVS_SCFI 1 /* 1 scfi (SCSI) disk drive units */
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//#define NUM_UNITS_SCFI 2 /* 1 of 4 disk drive devices */
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#define NUM_UNITS_SCFI 4 /* 1 of 4 disk drive devices */
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#define NUM_DEVS_SCSI 2 /* 2 scsi (MFP SCSI) scsi buss units */
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#define NUM_UNITS_SCSI 2 /* 2 scsi disk drive devices */
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#define NUM_DEVS_RTOM 1 /* 1 IOP RTOM channel */
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#define NUM_UNITS_RTOM 1 /* 1 IOP RTOM device (clock & interval timer) */
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#define NUM_DEVS_LPR 1 /* 1 IOP Line printer */
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#define NUM_UNITS_LPR 1 /* 1 IOP Line printer device */
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#define NUM_DEVS_ETHER 1 /* 1 Ethernet controller */
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#define NUM_UNITS_ETHER 16 /* 16 Ethernet devices */
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extern DEVICE cpu_dev; /* cpu device */
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extern UNIT cpu_unit; /* the cpu unit */
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#ifdef NUM_DEVS_IOP
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extern DEVICE iop_dev; /* IOP channel controller */
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#endif
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#ifdef NUM_DEVS_MFP
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extern DEVICE mfp_dev; /* MFP channel controller */
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#endif
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#ifdef NUM_DEVS_RTOM
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extern DEVICE rtc_dev; /* RTOM rtc */
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extern DEVICE itm_dev; /* RTOM itm */
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#endif
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#ifdef NUM_DEVS_CON
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extern DEVICE con_dev;
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#endif
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#ifdef NUM_DEVS_MT
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extern DEVICE mta_dev;
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#endif
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#if NUM_DEVS_MT > 1
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extern DEVICE mtb_dev;
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#endif
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#ifdef NUM_DEVS_DISK
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extern DEVICE dda_dev;
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#endif
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#if NUM_DEVS_DISK > 1
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extern DEVICE ddb_dev;
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#endif
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#ifdef NUM_DEVS_HSDP
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extern DEVICE dpa_dev;
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#endif
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#if NUM_DEVS_HSDP > 1
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extern DEVICE dpb_dev;
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#endif
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#ifdef NUM_DEVS_SCFI
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extern DEVICE sda_dev;
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#endif
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#if NUM_DEVS_SCFI > 1
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extern DEVICE sdb_dev;
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#endif
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#ifdef NUM_DEVS_SCSI
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extern DEVICE sba_dev;
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#endif
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#if NUM_DEVS_SCSI > 1
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extern DEVICE sbb_dev;
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#endif
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#ifdef NUM_DEVS_COM
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extern DEVICE coml_dev;
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extern DEVICE com_dev;
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#endif
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#ifdef NUM_DEVS_LPR
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extern DEVICE lpr_dev;
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#endif
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#ifdef NUM_DEVS_ETHER
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extern DEVICE ec_dev;
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#endif
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/* Memory */
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#define MAXMEMSIZE ((16*1024*1024)/4) /* max memory size in 32bit words */
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#define MEMSIZE (cpu_unit.capac) /* actual memory size */
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#define MEM_ADDR_OK(x) (((x)) < MEMSIZE)
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/* channel program data for a chan/sub-address */
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typedef struct chp {
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/* channel program values */
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UNIT *unitptr; /* Back pointer to units structure */
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uint32 chan_inch_addr; /* Current channel status dw addr in memory */
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uint32 base_inch_addr; /* Original channel status dw addr in memory */
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uint16 max_inch_addr; /* maximum inch buffer pointer */
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uint32 chan_caw; /* Channel command address word */
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uint32 ccw_addr; /* Channel address */
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#ifdef TEST_FOR_IOCL_CHANGE
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uint32 new_iocla; /* start iocl address */
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uint32 new_iocd1; /* start word 1 of iocd */
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uint32 new_iocd2; /* start word 2 of iocd */
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#endif
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uint32 chan_buf; /* Channel data buffer */
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uint16 ccw_count; /* Channel count */
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uint16 ccw_flags; /* Channel flags */
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uint16 chan_status; /* Channel status */
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uint16 chan_dev; /* Device on channel */
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uint8 ccw_cmd; /* Channel command and flags */
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uint8 chan_byte; /* Current byte, empty/full */
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uint8 chan_int; /* channel interrupt level */
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uint8 chan_info; /* misc flags for channel */
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} CHANP;
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/* Device information block */
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#define FIFO_SIZE 256 /* fifo to hold 128 double words of status */
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extern int32 FIFO_Put(uint16 chsa, uint32 entry);
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extern int32 FIFO_Get(uint16 chsa, uint32 *old);
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extern int32 FIFO_Num(uint16 chsa);
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#define IOCLQ_SIZE 32 /* fifo to hold 32 iocl cmds */
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typedef struct ioclq {
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uint32 ioclq_fifo[IOCLQ_SIZE];
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int16 ioclq_in;
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int16 ioclq_out;
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} IOCLQ;
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extern int32 IOCLQ_Put(IOCLQ *qptr, uint32 entry);
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extern int32 IOCLQ_Get(IOCLQ *qptr, uint32 *old);
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extern int32 IOCLQ_Num(IOCLQ *qptr);
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typedef struct dib {
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/* Pre start I/O operation */
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t_stat (*pre_io)(UNIT *uptr, uint16 chan);
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/* Start a channel command SIO */
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t_stat (*start_cmd)(UNIT *uptr, uint16 chan, uint8 cmd);
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/* Halt I/O HIO */
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t_stat (*halt_io)(UNIT *uptr); /* Halt I/O */
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/* Test I/O STOPIO */
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t_stat (*stop_io)(UNIT *uptr); /* Stop I/O */
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/* Test I/O TESTIO */
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t_stat (*test_io)(UNIT *uptr); /* Test I/O */
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/* Reset Controller RSCTL */
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t_stat (*rsctl_io)(UNIT *uptr); /* Reset Controller */
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/* Reset Controller RSCHNL */
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t_stat (*rschnl_io)(UNIT *uptr); /* Reset Channel */
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/* Post I/O processing */
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t_stat (*iocl_io)(CHANP *chp, int32 tic_ok); /* IOCL processing */
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/* Controller init */
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void (*dev_ini)(UNIT *, t_bool); /* init function */
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UNIT *units; /* Pointer to units structure */
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CHANP *chan_prg; /* Pointer to channel program */
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IOCLQ *ioclq_ptr; /* pointer to array of IOCLQ entries */
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uint8 numunits; /* number of units */
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uint8 mask; /* device mask */
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uint16 chan_addr; /* parent channel address */
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uint32 chan_fifo_in; /* fifo input index */
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uint32 chan_fifo_out; /* fifo output index */
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uint32 chan_fifo[FIFO_SIZE]; /* interrupt status fifo for each channel */
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} DIB;
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extern DIB *dib_unit[MAX_DEV]; /* Pointer to Device info block */
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extern DIB *dib_chan[MAX_CHAN]; /* Pointer to channel mux dib */
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/* defined in upper 16 bits of dptr->flags */
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#define DEV_CHAN (1 << DEV_V_UF) /* Device is channel mux if set */
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#define DEV_V_UF2 (DEV_V_UF+1) /* current usage */
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#define DEV_BUF_NUM(x) (((x) & 07) << DEV_V_UF2)
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#define GET_DEV_BUF(x) (((x) >> DEV_V_UF2) & 07)
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#ifdef NOT_USED_NOW
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//#define DEV_V_ADDR DEV_V_UF /* Pointer to device address (16) */
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//#define DEV_V_DADDR (DEV_V_UF + 8) /* Device address */
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//#define DEV_ADDR_MASK (0x7f << DEV_V_DADDR) /* 24 bits shift */
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//#define DEV_V_UADDR (DEV_V_UF) /* Device address in Unit */
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//#define DEV_UADDR (1 << DEV_V_UADDR)
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//#define GET_DADDR(x) (0x7f & ((x) >> DEV_V_ADDR))
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//#define DEV_ADDR(x) ((x) << DEV_V_ADDR)
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//#define PROTECT_V UNIT_V_UF+15
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//#define PROTECT (1 << PROTECT_V)
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#endif
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/* defined in rightmost 8 bits of upper 16 bits of uptr->flags */
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/* allow 255 type disks */
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#define UNIT_SUBCHAN (1 << (UNIT_V_UF_31))
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#define UNIT_V_TYPE (UNIT_V_UF + 0)
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#define UNIT_TYPE (0xff << UNIT_V_TYPE)
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/* get & set disk types */
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#define GET_TYPE(x) ((UNIT_TYPE & (x)) >> UNIT_V_TYPE)
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#define SET_TYPE(x) (UNIT_TYPE & ((x) << UNIT_V_TYPE))
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/* defined in uptr->u3 upper 16 bits */
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/* DEV 0x7F000000 UNIT 0x00ff0000 */
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#define UNIT_V_ADDR 16
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#define UNIT_ADDR_MASK (0x7fff << UNIT_V_ADDR)
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#define GET_UADDR(x) ((UNIT_ADDR_MASK & x) >> UNIT_V_ADDR)
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#define UNIT_ADDR(x) ((x) << UNIT_V_ADDR)
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/* Debugging controls */
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#define DEBUG_CMD 0x0000001 /* Show device commands */
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#define DEBUG_DATA 0x0000002 /* Show data transfers */
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#define DEBUG_DETAIL 0x0000004 /* Show details */
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#define DEBUG_INFO 0x0000004 /* Show details */
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#define DEBUG_EXP 0x0000008 /* Show error conditions */
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#define DEBUG_INST 0x0000010 /* Show instructions */
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#define DEBUG_XIO 0x0000020 /* Show XIO I/O instructions */
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#define DEBUG_IRQ 0x0000040 /* Show IRQ requests */
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#define DEBUG_TRAP 0x0000080 /* Show TRAP requests */
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extern DEBTAB dev_debug[];
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/* defines for all programs */
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#define RMASK 0x0000FFFF /* right hw 16 bit mask */
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#define LMASK 0xFFFF0000 /* left hw 16 bit mask */
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#define FMASK 0xFFFFFFFF /* 32 bit mask */
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#define DMASK 0xFFFFFFFFFFFFFFFFLL /* 64 bit all bits mask */
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#define D48LMASK 0xFFFFFFFFFFFF0000LL /* 64 bit left 48 bits mask */
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#define D32LMASK 0xFFFFFFFF00000000LL /* 64 bit left 32 bits mask */
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#define D32RMASK 0x00000000FFFFFFFFLL /* 64 bit right 32 bits mask */
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#define MSIGN 0x80000000 /* 32 bit minus sign */
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#define DMSIGN 0x8000000000000000LL /* 64 bit minus sign */
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#define FSIGN 0x80000000 /* 32 bit minus sign */
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/* sign extend 16 bit value to uint32 */
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#define SEXT16(x) (x&0x8000?(uint32)(((uint32)x&RMASK)|LMASK):(uint32)x)
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/* sign extend 16 bit value to uint64 */
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#define DSEXT16(x) (x&0x8000?(l_uint64)(((l_uint64)x&RMASK)|D48LMASK):(t_uint64)x)
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/* sign extend 32 bit value to uint64 */
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#define DSEXT32(x) (x&0x8000?(l_uint64)(((l_uint64)x&D32RMASK)|D32LMASK):(t_uint64)x)
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#define NEGATE32(val) ((~val) + 1) /* negate a value 16/32/64 bits */
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/* defined in rightmost 8 bits of upper 16 bits of uptr->flags */
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#define UNIT_V_MODEL (UNIT_V_UF + 0)
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#define UNIT_MODEL (7 << UNIT_V_MODEL)
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#define MODEL(x) (x << UNIT_V_MODEL)
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#define UNIT_V_MSIZE (UNIT_V_MODEL + 3)
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#define UNIT_MSIZE (0x1F << UNIT_V_MSIZE)
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#define MEMAMOUNT(x) (x << UNIT_V_MSIZE)
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#define CPU_MODEL ((cpu_unit.flags >> UNIT_V_MODEL) & 0x7) /* cpu model 0-7 */
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#define MODEL_55 0 /* 512K Mode Only */
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#define MODEL_75 1 /* Extended */
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#define MODEL_27 2 /* */
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#define MODEL_67 3 /* */
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#define MODEL_87 4 /* */
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#define MODEL_97 5 /* */
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#define MODEL_V6 6 /* V6 CPU */
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#define MODEL_V9 7 /* V9 CPU */
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#define TMR_RTC 1 /* RTC will not work if set to 0!! */
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//#define TMR_RTC 0
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#define HIST_MIN 64
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#define HIST_MAX 10000
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#define HIST_PC 0x80000000
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/* CC defs Held in CC */
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#define CC1BIT 0x40000000 /* CC1 in PSD1 */
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#define CC2BIT 0x20000000 /* CC2 in PSD1 */
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#define CC3BIT 0x10000000 /* CC3 in PSD1 */
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#define CC4BIT 0x08000000 /* CC4 in PSD1 */
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#define MAPMODE 0x40 /* Map mode, PSD 2 bit 0 */
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#define RETMODE 0x20 /* Retain current maps, PSD 2 bit 15 */
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#define RETBLKM 0x10 /* Set retain blocked mode, PSD 2 bit 16 */
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#define BLKMODE 0x08 /* Set blocked mode, PSD 2 bit 17 */
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/* PSD mode bits in PSD words 1&2 variable */
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#define PRIVBIT 0x80000000 /* Privileged mode PSD 1 bit 0 */
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#define EXTDBIT 0x04000000 /* Extended Addressing PSD 1 bit 5 */
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#define BASEBIT 0x02000000 /* Base Mode PSD 1 bit 6 */
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#define AEXPBIT 0x01000000 /* Arithmetic exception PSD 1 bit 7 */
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#define MAPBIT 0x80000000 /* Map mode, PSD 2 bit 0 */
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#define RETMBIT 0x00010000 /* Retain current maps, PSD 2 bit 15 */
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#define RETBBIT 0x00008000 /* Retain current blocking state, PSD 2 bit 16 */
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#define SETBBIT 0x00004000 /* Set blocked mode, PSD 2 bit 17 */
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/* Trap Table Address in memory is pointed to by SPAD 0xF0 */
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#define POWERFAIL_TRAP 0x80 /* Power fail trap */
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#define POWERON_TRAP 0x84 /* Power-On trap */
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#define MEMPARITY_TRAP 0x88 /* Memory Parity Error trap */
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#define NONPRESMEM_TRAP 0x8C /* Non Present Memory trap */
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#define UNDEFINSTR_TRAP 0x90 /* Undefined Instruction Trap */
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#define PRIVVIOL_TRAP 0x94 /* Privlege Violation Trap */
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#define SVCCALL_TRAP 0x98 /* Supervisor Call Trap */
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#define MACHINECHK_TRAP 0x9C /* Machine Check Trap */
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#define SYSTEMCHK_TRAP 0xA0 /* System Check Trap */
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#define MAPFAULT_TRAP 0xA4 /* Map Fault Trap */
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#define IPUUNDEFI_TRAP 0xA8 /* IPU Undefined Instruction Trap */
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#define SIGNALIPU_TRAP 0xAC /* Signal IPU/CPU Trap */
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#define ADDRSPEC_TRAP 0xB0 /* Address Specification Trap */
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#define CONSOLEATN_TRAP 0xB4 /* Console Attention Trap */
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#define PRIVHALT_TRAP 0xB8 /* Privlege Mode Halt Trap */
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#define AEXPCEPT_TRAP 0xBC /* Arithmetic Exception Trap */
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#define CACHEERR_TRAP 0xC0 /* Cache Error Trap (V9 Only) */
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#define DEMANDPG_TRAP 0xC4 /* Demand Page Fault Trap (V6&V9 Only) */
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/* Errors returned from various functions */
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#define ALLOK 0x0000 /* no error, all is OK */
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#define MAPFLT MAPFAULT_TRAP /* map fault error */
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#define NPMEM NONPRESMEM_TRAP /* non present memory */
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#define MPVIOL PRIVVIOL_TRAP /* memory protection violation */
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#define DMDPG DEMANDPG_TRAP /* Demand Page Fault Trap (V6&V9 Only) */
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/* general instruction decode equates */
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#define IND 0x00100000 /* indirect bit in instruction, bit 11 */
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#define F_BIT 0x00080000 /* byte flag addressing bit 11 in instruction */
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#define C_BITS 0x00000003 /* byte number or hw, dw, dw flags bits 30 & 31 */
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#define BIT0 0x80000000 /* general use for bit 0 testing */
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#define BIT1 0x40000000 /* general use for bit 1 testing */
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#define BIT2 0x20000000 /* general use for bit 2 testing */
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#define BIT3 0x10000000 /* general use for bit 3 testing */
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#define BIT4 0x08000000 /* general use for bit 4 testing */
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#define BIT5 0x04000000 /* general use for bit 5 testing */
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#define BIT6 0x02000000 /* general use for bit 6 testing */
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#define BIT7 0x01000000 /* general use for bit 7 testing */
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#define BIT8 0x00800000 /* general use for bit 8 testing */
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#define BIT9 0x00400000 /* general use for bit 9 testing */
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#define BIT10 0x00200000 /* general use for bit 10 testing */
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#define BIT11 0x00100000 /* general use for bit 11 testing */
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#define BIT12 0x00080000 /* general use for bit 12 testing */
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#define BIT13 0x00040000 /* general use for bit 13 testing */
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#define BIT14 0x00020000 /* general use for bit 14 testing */
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#define BIT15 0x00010000 /* general use for bit 15 testing */
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#define BIT16 0x00008000 /* general use for bit 16 testing */
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#define BIT17 0x00004000 /* general use for bit 17 testing */
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#define BIT18 0x00002000 /* general use for bit 18 testing */
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#define BIT19 0x00001000 /* general use for bit 19 testing */
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#define BIT20 0x00000800 /* general use for bit 20 testing */
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#define BIT21 0x00000400 /* general use for bit 21 testing */
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#define BIT22 0x00000200 /* general use for bit 22 testing */
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#define BIT23 0x00000100 /* general use for bit 23 testing */
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#define BIT24 0x00000080 /* general use for bit 24 testing */
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#define BIT25 0x00000040 /* general use for bit 25 testing */
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#define BIT26 0x00000020 /* general use for bit 26 testing */
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#define BIT27 0x00000010 /* general use for bit 27 testing */
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#define BIT28 0x00000008 /* general use for bit 28 testing */
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#define BIT29 0x00000004 /* general use for bit 29 testing */
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#define BIT30 0x00000002 /* general use for bit 30 testing */
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#define BIT31 0x00000001 /* general use for bit 31 testing */
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#define MASK16 0x0000FFFF /* 16 bit address mask */
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#define MASK19 0x0007FFFF /* 19 bit address mask */
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#define MASK20 0x000FFFFF /* 20 bit address mask */
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#define MASK24 0x00FFFFFF /* 24 bit address mask */
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#define MASK32 0xFFFFFFFF /* 32 bit address mask */
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/* SPAD int entry equates, entries accessed by interrupt level number */
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#define SINT_RAML 0x80000000 /* ram loaded (n/u) */
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#define SINT_EWCS 0x40000000 /* Enabled channel WCS executed (XIO) */
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#define SINT_ACT 0x20000000 /* Interrupt active when set (copy is in INTS */
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#define SINT_ENAB 0x10000000 /* Interrupt enabled when set (copy is in INTS */
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#define SINT_EXTL 0x00800000 /* IOP/RTOM ext interrupt if set, I/O if not set (copy in INTS) */
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/* INTS int entry equates, entries accessed by interrupt level number */
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#define INTS_NU1 0x80000000 /* Not used */
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#define INTS_REQ 0x40000000 /* Interrupt is requesting (use bit 1) */
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#define INTS_ACT 0x20000000 /* Interrupt active when set (copy is of SPAD */
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#define INTS_ENAB 0x10000000 /* Interrupt enabled when set (copy is of SPAD */
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#define INTS_EXTL 0x00800000 /* IOP/RTOM ext interrupt if set, I/O if not set (copy of SPAD) */
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/* ReadAddr memory access requested */
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#define MEM_RD 0x0 /* read memory */
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#define MEM_WR 0x1 /* write memory */
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#define MEM_EX 0x2 /* execute memory */
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/* Rename of global PC variable to avoid namespace conflicts on some platforms */
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#define PC PC_Global
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/* memory access macros */
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/* The RMW and WMW macros are used to read/write memory words */
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/* RMW(addr) or WMW(addr, data) where addr is a byte alligned word address */
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#define RMB(a) ((M[(a)>>2]>>(8*(3-(a&3))))&0xff) /* read memory addressed byte */
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#define RMH(a) ((a)&2?(M[(a)>>2]&RMASK):(M[(a)>>2]>>16)&RMASK) /* read memory addressed halfword */
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#define RMW(a) (M[((a)&MASK24)>>2]) /* read memory addressed word */
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#define WMW(a,d) (M[((a)&MASK24)>>2]=d) /* write memory addressed word */
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/* write halfword to memory address */
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#define WMH(a,d) ((a)&2?(M[(a)>>2]=(M[(a)>>2]&LMASK)|((d)&RMASK)):(M[(a)>>2]=(M[(a)>>2]&RMASK)|((d)<<16)))
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/* write byte to memory */
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#define WMB(a,d) (M[(a)>>2]=(((M[(a)>>2])&(~(0xff<<(8*(3-(a&3))))))|((d&0xff)<<(8*(3-(a&3))))))
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/* map register access macros */
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/* The RMR and WMR macros are used to read/write the MAPC cache registers */
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/* RMR(addr) or WMR(addr, data) where addr is a half word alligned address */
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/* read map register halfword from cache address */
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#define RMR(a) ((a)&2?(MAPC[(a)>>2]&RMASK):(MAPC[(a)>>2]>>16)&RMASK)
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/* write halfword map register to MAP cache address */
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#define WMR(a,d) ((a)&2?(MAPC[(a)>>2]=(MAPC[(a)>>2]&LMASK)|((d)&RMASK)):(MAPC[(a)>>2]=(MAPC[(a)>>2]&RMASK)|((d)<<16)))
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/* Definitions for commonly used functions */
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extern t_stat set_dev_addr(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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extern t_stat show_dev_addr(FILE * st, UNIT *uptr, int32 v, CONST void *desc);
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extern void chan_end(uint16 chan, uint16 flags);
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extern int chan_read_byte(uint16 chsa, uint8 *data);
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extern int chan_write_byte(uint16 chsa, uint8 *data);
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extern void set_devattn(uint16 addr, uint16 flags);
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extern void set_devwake(uint16 chsa, uint16 flags);
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extern t_stat chan_boot(uint16 addr, DEVICE *dptr);
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extern int test_write_byte_end(uint16 chsa);
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extern DEVICE *get_dev(UNIT *uptr);
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extern t_stat set_inch(UNIT *uptr, uint32 inch_addr, uint32 num_inch); /* set inch addr */
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extern CHANP *find_chanp_ptr(uint16 chsa); /* find chanp pointer */
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extern uint32 M[]; /* our memory */
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extern uint32 SPAD[]; /* cpu SPAD memory */
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extern uint32 attention_trap;
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extern uint32 RDYQ[]; /* ready queue */
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extern uint32 RDYQIN; /* input index */
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extern uint32 RDYQOUT; /* output index */
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#define RDYQ_SIZE 128
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extern int32 RDYQ_Put(uint32 entry);
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extern int32 RDYQ_Get(uint32 *old);
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extern int32 RDYQ_Num(void);
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extern char *dump_mem(uint32 mp, int cnt);
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extern char *dump_buf(uint8 *mp, int32 off, int cnt);
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#define get_chan(chsa) ((chsa>>8)&0x7f) /* get channel number from ch/sa */
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