53d02f7fa7
1. New Features 1.1 3.7-0 1.1.1 SCP - Added SET THROTTLE and SET NOTHROTTLE commands to regulate simulator execution rate and host resource utilization. - Added idle support (based on work by Mark Pizzolato). - Added -e to control error processing in nested DO commands (from Dave Bryan). 1.1.2 HP2100 - Added Double Integer instructions, 1000-F CPU, and Floating Point Processor (from Dave Bryan). - Added 2114 and 2115 CPUs, 12607B and 12578A DMA controllers, and 21xx binary loader protection (from Dave Bryan). 1.1.3 Interdata - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state. 1.1.4 PDP-11 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (WAIT instruction executed). - Added TA11/TU60 cassette support. 1.1.5 PDP-8 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (keyboard poll loop or jump-to-self). - Added TA8E/TU60 cassette support. 1.1.6 PDP-1 - Added support for 16-channel sequence break system. - Added support for PDP-1D extended features and timesharing clock. - Added support for Type 630 data communications subsystem. 1.1.6 PDP-4/7/9/15 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (keyboard poll loop or jump-to-self). 1.1.7 VAX, VAX780 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (more than 200 cycles at IPL's 0, 1, or 3 in kernel mode). 1.1.8 PDP-10 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (operating system dependent). - Added CD20 (CD11) support. 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h.
633 lines
25 KiB
C
633 lines
25 KiB
C
/* pdp8_sys.c: PDP-8 simulator interface
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Copyright (c) 1993-2006, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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15-Dec-06 RMS Added TA8E support, IOT disambiguation
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30-Oct-06 RMS Added infinite loop stop
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18-Oct-06 RMS Re-ordered device list
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17-Oct-03 RMS Added TSC8-75, TD8E support, DECtape off reel message
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25-Apr-03 RMS Revised for extended file support
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30-Dec-01 RMS Revised for new TTX
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26-Nov-01 RMS Added RL8A support
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17-Sep-01 RMS Removed multiconsole support
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16-Sep-01 RMS Added TSS/8 packed char support, added KL8A support
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27-May-01 RMS Added multiconsole support
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18-Mar-01 RMS Added DF32 support
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14-Mar-01 RMS Added extension detection of RIM binary tapes
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15-Feb-01 RMS Added DECtape support
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30-Oct-00 RMS Added support for examine to file
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27-Oct-98 RMS V2.4 load interface
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10-Apr-98 RMS Added RIM loader support
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17-Feb-97 RMS Fixed bug in handling of bin loader fields
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*/
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#include "pdp8_defs.h"
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#include <ctype.h>
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extern DEVICE cpu_dev;
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extern UNIT cpu_unit;
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extern DEVICE tsc_dev;
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extern DEVICE ptr_dev, ptp_dev;
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extern DEVICE tti_dev, tto_dev;
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extern DEVICE clk_dev, lpt_dev;
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extern DEVICE rk_dev, rl_dev;
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extern DEVICE rx_dev;
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extern DEVICE df_dev, rf_dev;
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extern DEVICE dt_dev, td_dev;
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extern DEVICE mt_dev, ct_dev;
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extern DEVICE ttix_dev, ttox_dev;
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extern REG cpu_reg[];
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extern uint16 M[];
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extern int32 sim_switches;
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/* SCP data structures and interface routines
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sim_name simulator name string
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sim_PC pointer to saved PC register descriptor
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sim_emax maximum number of words for examine/deposit
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sim_devices array of pointers to simulated devices
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sim_consoles array of pointers to consoles (if more than one)
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sim_stop_messages array of pointers to stop messages
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sim_load binary loader
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*/
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char sim_name[] = "PDP-8";
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REG *sim_PC = &cpu_reg[0];
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int32 sim_emax = 4;
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DEVICE *sim_devices[] = {
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&cpu_dev,
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&tsc_dev,
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&clk_dev,
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&ptr_dev,
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&ptp_dev,
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&tti_dev,
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&tto_dev,
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&ttix_dev,
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&ttox_dev,
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&lpt_dev,
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&rk_dev,
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&rl_dev,
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&rx_dev,
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&df_dev,
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&rf_dev,
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&dt_dev,
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&td_dev,
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&mt_dev,
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&ct_dev,
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NULL
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};
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const char *sim_stop_messages[] = {
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"Unknown error",
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"Unimplemented instruction",
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"HALT instruction",
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"Breakpoint",
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"Non-standard device number",
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"DECtape off reel",
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"Infinite loop"
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};
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/* Ambiguous device list - these devices have overlapped IOT codes */
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DEVICE *amb_dev[] = {
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&rl_dev,
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&ct_dev,
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&td_dev,
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NULL
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};
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#define AMB_RL (1 << 12)
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#define AMB_CT (2 << 12)
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#define AMB_TD (3 << 12)
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/* Binary loader
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Two loader formats are supported: RIM loader (-r) and BIN (-b) loader.
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RIM loader format consists of alternating pairs of addresses and 12-bit
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words. It can only operate in field 0 and is not checksummed.
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BIN loader format consists of a string of 12-bit words (made up from
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7-bit characters) between leader and trailer (200). The last word on
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tape is the checksum. A word with the "link" bit set is a new origin;
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a character > 0200 indicates a change of field.
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*/
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t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
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{
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int32 rubout, word, low, high, csum, newf, state, i;
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uint32 origin, field;
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if ((*cptr != 0) || (flag != 0)) return SCPE_ARG;
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rubout = state = field = newf = origin = csum = 0;
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if ((sim_switches & SWMASK ('R')) || /* RIM format? */
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(match_ext (fnam, "RIM") && !(sim_switches & SWMASK ('B')))) {
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while ((i = getc (fileref)) != EOF) {
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switch (state) {
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case 0: /* leader */
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if ((i != 0) && (i < 0200)) state = 1;
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high = i;
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break;
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case 1: /* low byte */
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word = (high << 6) | i; /* form word */
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if (word > 07777) origin = word & 07777;
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else M[origin] = word;
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state = 2;
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break;
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case 2: /* high byte */
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if (i >= 0200) return SCPE_OK; /* end of tape? */
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high = i; /* save high */
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state = 1;
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break;
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} /* end switch */
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} /* end while */
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} /* end if */
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else {
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while ((i = getc (fileref)) != EOF) { /* BIN format */
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if (rubout) {
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rubout = 0;
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continue;
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}
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if (i == 0377) {
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rubout = 1;
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continue;
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}
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if (i > 0200) {
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newf = (i & 070) << 9;
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continue;
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}
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switch (state) {
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case 0: /* leader */
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if ((i != 0) && (i != 0200)) state = 1;
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high = i; /* save as high */
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break;
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case 1: /* low byte */
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low = i;
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state = 2;
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break;
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case 2: /* high with test */
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word = (high << 6) | low;
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if (i == 0200) { /* end of tape? */
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if ((csum - word) & 07777) return SCPE_CSUM;
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return SCPE_OK;
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}
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csum = csum + low + high;
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if (word >= 010000) origin = word & 07777;
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else {
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if ((field | origin) >= MEMSIZE)
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return SCPE_NXM;
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M[field | origin] = word & 07777;
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origin = (origin + 1) & 07777;
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}
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field = newf;
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high = i;
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state = 1;
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break;
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} /* end switch */
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} /* end while */
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} /* end else */
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return SCPE_FMT; /* eof? error */
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}
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/* Symbol tables */
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#define I_V_FL 18 /* flag start */
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#define I_M_FL 07 /* flag mask */
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#define I_V_NPN 0 /* no operand */
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#define I_V_FLD 1 /* field change */
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#define I_V_MRF 2 /* mem ref */
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#define I_V_IOT 3 /* general IOT */
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#define I_V_OP1 4 /* operate 1 */
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#define I_V_OP2 5 /* operate 2 */
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#define I_V_OP3 6 /* operate 3 */
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#define I_V_IOA 7 /* ambiguous IOT */
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#define I_NPN (I_V_NPN << I_V_FL)
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#define I_FLD (I_V_FLD << I_V_FL)
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#define I_MRF (I_V_MRF << I_V_FL)
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#define I_IOT (I_V_IOT << I_V_FL)
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#define I_OP1 (I_V_OP1 << I_V_FL)
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#define I_OP2 (I_V_OP2 << I_V_FL)
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#define I_OP3 (I_V_OP3 << I_V_FL)
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#define I_IOA (I_V_IOA << I_V_FL)
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static const int32 masks[] = {
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07777, 07707, 07000, 07000,
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07416, 07571, 017457, 077777,
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};
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/* Ambiguous device mnemonics must precede default mnemonics */
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static const char *opcode[] = {
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"SKON", "ION", "IOF", "SRQ", /* std IOTs */
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"GTF", "RTF", "SGT", "CAF",
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"RPE", "RSF", "RRB", "RFC", "RFC RRB", /* reader/punch */
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"PCE", "PSF", "PCF", "PPC", "PLS",
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"KCF", "KSF", "KCC", "KRS", "KIE", "KRB", /* console */
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"TLF", "TSF", "TCF", "TPC", "SPI", "TLS",
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"SBE", "SPL", "CAL", /* power fail */
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"CLEI", "CLDI", "CLSC", "CLLE", "CLCL", "CLSK", /* clock */
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"CINT", "RDF", "RIF", "RIB", /* mem mmgt */
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"RMF", "SINT", "CUF", "SUF",
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"RLDC", "RLSD", "RLMA", "RLCA", /* RL - ambiguous */
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"RLCB", "RLSA", "RLWC",
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"RRER", "RRWC", "RRCA", "RRCB",
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"RRSA", "RRSI", "RLSE",
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"KCLR", "KSDR", "KSEN", "KSBF", /* CT - ambiguous */
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"KLSA", "KSAF", "KGOA", "KRSB",
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"SDSS", "SDST", "SDSQ", /* TD - ambiguous */
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"SDLC", "SDLD", "SDRC", "SDRD",
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"ADCL", "ADLM", "ADST", "ADRB", /* A/D */
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"ADSK", "ADSE", "ADLE", "ADRS",
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"DCMA", "DMAR", "DMAW", /* DF/RF */
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"DCIM", "DSAC", "DIML", "DIMA",
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"DCEA", "DEAL", "DEAC",
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"DFSE", "DFSC", "DISK", "DMAC",
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"DCXA", "DXAL", "DXAC",
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"PSKF", "PCLF", "PSKE", /* LPT */
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"PSTB", "PSIE", "PCLF PSTB", "PCIE",
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"LWCR", "CWCR", "LCAR", /* MT */
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"CCAR", "LCMR", "LFGR", "LDBR",
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"RWCR", "CLT", "RCAR",
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"RMSR", "RCMR", "RFSR", "RDBR",
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"SKEF", "SKCB", "SKJD", "SKTR", "CLF",
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"DSKP", "DCLR", "DLAG", /* RK */
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"DLCA", "DRST", "DLDC", "DMAN",
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"LCD", "XDR", "STR", /* RX */
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"SER", "SDN", "INTR", "INIT",
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"DTRA", "DTCA", "DTXA", "DTLA", /* DT */
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"DTSF", "DTRB", "DTLB",
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"ETDS", "ESKP", "ECTF", "ECDF", /* TSC75 */
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"ERTB", "ESME", "ERIOT", "ETEN",
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"CDF", "CIF", "CIF CDF",
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"AND", "TAD", "ISZ", "DCA", "JMS", "JMP", "IOT",
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"NOP", "NOP2", "NOP3", "SWAB", "SWBA",
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"STL", "GLK", "STA", "LAS", "CIA",
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"BSW", "RAL", "RTL", "RAR", "RTR", "RAL RAR", "RTL RTR",
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"SKP", "SNL", "SZL",
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"SZA", "SNA", "SZA SNL", "SNA SZL",
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"SMA", "SPA", "SMA SNL", "SPA SZL",
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"SMA SZA", "SPA SNA", "SMA SZA SNL", "SPA SNA SZL",
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"SCL", "MUY", "DVI", "NMI", "SHL", "ASR", "LSR",
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"SCA", "SCA SCL", "SCA MUY", "SCA DVI",
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"SCA NMI", "SCA SHL", "SCA ASR", "SCA LSR",
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"ACS", "MUY", "DVI", "NMI", "SHL", "ASR", "LSR",
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"SCA", "DAD", "DST", "SWBA",
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"DPSZ", "DPIC", "DCIM", "SAM",
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"CLA", "CLL", "CMA", "CML", "IAC", /* encode only */
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"CLA", "OAS", "HLT",
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"CLA", "MQA", "MQL",
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NULL, NULL, NULL, NULL, /* decode only */
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NULL
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};
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static const int32 opc_val[] = {
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06000+I_NPN, 06001+I_NPN, 06002+I_NPN, 06003+I_NPN,
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06004+I_NPN, 06005+I_NPN, 06006+I_NPN, 06007+I_NPN,
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06010+I_NPN, 06011+I_NPN, 06012+I_NPN, 06014+I_NPN, 06016+I_NPN,
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06020+I_NPN, 06021+I_NPN, 06022+I_NPN, 06024+I_NPN, 06026+I_NPN,
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06030+I_NPN, 06031+I_NPN, 06032+I_NPN, 06034+I_NPN, 06035+I_NPN, 06036+I_NPN,
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06040+I_NPN, 06041+I_NPN, 06042+I_NPN, 06044+I_NPN, 06045+I_NPN, 06046+I_NPN,
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06101+I_NPN, 06102+I_NPN, 06103+I_NPN,
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06131+I_NPN, 06132+I_NPN, 06133+I_NPN, 06135+I_NPN, 06136+I_NPN, 06137+I_NPN,
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06204+I_NPN, 06214+I_NPN, 06224+I_NPN, 06234+I_NPN,
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06244+I_NPN, 06254+I_NPN, 06264+I_NPN, 06274+I_NPN,
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06600+I_IOA+AMB_RL, 06601+I_IOA+AMB_RL, 06602+I_IOA+AMB_RL, 06603+I_IOA+AMB_RL,
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06604+I_IOA+AMB_RL, 06605+I_IOA+AMB_RL, 06607+I_IOA+AMB_RL,
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06610+I_IOA+AMB_RL, 06611+I_IOA+AMB_RL, 06612+I_IOA+AMB_RL, 06613+I_IOA+AMB_RL,
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06614+I_IOA+AMB_RL, 06615+I_IOA+AMB_RL, 06617+I_IOA+AMB_RL,
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06700+I_IOA+AMB_CT, 06701+I_IOA+AMB_CT, 06702+I_IOA+AMB_CT, 06703+I_IOA+AMB_CT,
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06704+I_IOA+AMB_CT, 06705+I_IOA+AMB_CT, 06706+I_IOA+AMB_CT, 06707+I_IOA+AMB_CT,
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06771+I_IOA+AMB_TD, 06772+I_IOA+AMB_TD, 06773+I_IOA+AMB_TD,
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06774+I_IOA+AMB_TD, 06775+I_IOA+AMB_TD, 06776+I_IOA+AMB_TD, 06777+I_IOA+AMB_TD,
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06530+I_NPN, 06531+I_NPN, 06532+I_NPN, 06533+I_NPN, /* AD */
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06534+I_NPN, 06535+I_NPN, 06536+I_NPN, 06537+I_NPN,
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06601+I_NPN, 06603+I_NPN, 06605+I_NPN, /* DF/RF */
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06611+I_NPN, 06612+I_NPN, 06615+I_NPN, 06616+I_NPN,
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06611+I_NPN, 06615+I_NPN, 06616+I_NPN,
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06621+I_NPN, 06622+I_NPN, 06623+I_NPN, 06626+I_NPN,
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06641+I_NPN, 06643+I_NPN, 06645+I_NPN,
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06661+I_NPN, 06662+I_NPN, 06663+I_NPN, /* LPT */
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06664+I_NPN, 06665+I_NPN, 06666+I_NPN, 06667+I_NPN,
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06701+I_NPN, 06702+I_NPN, 06703+I_NPN, /* MT */
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06704+I_NPN, 06705+I_NPN, 06706+I_NPN, 06707+I_NPN,
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06711+I_NPN, 06712+I_NPN, 06713+I_NPN,
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06714+I_NPN, 06715+I_NPN, 06716+I_NPN, 06717+I_NPN,
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06721+I_NPN, 06722+I_NPN, 06723+I_NPN, 06724+I_NPN, 06725+I_NPN,
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06741+I_NPN, 06742+I_NPN, 06743+I_NPN, /* RK */
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06744+I_NPN, 06745+I_NPN, 06746+I_NPN, 06747+I_NPN,
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06751+I_NPN, 06752+I_NPN, 06753+I_NPN, /* RX */
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06754+I_NPN, 06755+I_NPN, 06756+I_NPN, 06757+I_NPN,
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06761+I_NPN, 06762+I_NPN, 06764+I_NPN, 06766+I_NPN, /* DT */
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06771+I_NPN, 06772+I_NPN, 06774+I_NPN,
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06360+I_NPN, 06361+I_NPN, 06362+I_NPN, 06363+I_NPN, /* TSC */
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06364+I_NPN, 06365+I_NPN, 06366+I_NPN, 06367+I_NPN,
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06201+I_FLD, 06202+I_FLD, 06203+I_FLD,
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00000+I_MRF, 01000+I_MRF, 02000+I_MRF, 03000+I_MRF,
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04000+I_MRF, 05000+I_MRF, 06000+I_IOT,
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07000+I_NPN, 07400+I_NPN, 07401+I_NPN, 07431+I_NPN, 07447+I_NPN,
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07120+I_NPN, 07204+I_NPN, 07240+I_NPN, 07604+I_NPN, 07041+I_NPN,
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07002+I_OP1, 07004+I_OP1, 07006+I_OP1,
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07010+I_OP1, 07012+I_OP1, 07014+I_OP1, 07016+I_OP1,
|
|
07410+I_OP2, 07420+I_OP2, 07430+I_OP2,
|
|
07440+I_OP2, 07450+I_OP2, 07460+I_OP2, 07470+I_OP2,
|
|
07500+I_OP2, 07510+I_OP2, 07520+I_OP2, 07530+I_OP2,
|
|
07540+I_OP2, 07550+I_OP2, 07560+I_OP2, 07570+I_OP2,
|
|
07403+I_OP3, 07405+I_OP3, 07407+I_OP3,
|
|
07411+I_OP3, 07413+I_OP3, 07415+I_OP3, 07417+I_OP3,
|
|
07441+I_OP3, 07443+I_OP3, 07445+I_OP3, 07447+I_OP3,
|
|
07451+I_OP3, 07453+I_OP3, 07455+I_OP3, 07457+I_OP3,
|
|
017403+I_OP3, 017405+I_OP3, 0174017+I_OP3,
|
|
017411+I_OP3, 017413+I_OP3, 017415+I_OP3, 017417+I_OP3,
|
|
017441+I_OP3, 017443+I_OP3, 017445+I_OP3, 017447+I_OP3,
|
|
017451+I_OP3, 017453+I_OP3, 017455+I_OP3, 017457+I_OP3,
|
|
07200+I_OP1, 07100+I_OP1, 07040+I_OP1, 07020+I_OP1, 07001+I_OP1,
|
|
07600+I_OP2, 07404+I_OP2, 07402+I_OP2,
|
|
07601+I_OP3, 07501+I_OP3, 07421+I_OP3,
|
|
07000+I_OP1, 07400+I_OP2, 07401+I_OP3, 017401+I_OP3,
|
|
-1
|
|
};
|
|
|
|
/* Operate decode
|
|
|
|
Inputs:
|
|
*of = output stream
|
|
inst = mask bits
|
|
class = instruction class code
|
|
sp = space needed?
|
|
Outputs:
|
|
status = space needed
|
|
*/
|
|
|
|
int32 fprint_opr (FILE *of, int32 inst, int32 class, int32 sp)
|
|
{
|
|
int32 i, j;
|
|
|
|
for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
|
|
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
|
|
if ((j == class) && (opc_val[i] & inst)) { /* same class? */
|
|
inst = inst & ~opc_val[i]; /* mask bit set? */
|
|
fprintf (of, (sp? " %s": "%s"), opcode[i]);
|
|
sp = 1;
|
|
}
|
|
}
|
|
return sp;
|
|
}
|
|
|
|
/* Symbolic decode
|
|
|
|
Inputs:
|
|
*of = output stream
|
|
addr = current PC
|
|
*val = pointer to data
|
|
*uptr = pointer to unit
|
|
sw = switches
|
|
Outputs:
|
|
return = status code
|
|
*/
|
|
|
|
#define FMTASC(x) ((x) < 040)? "<%03o>": "%c", (x)
|
|
#define SIXTOASC(x) (((x) >= 040)? (x): (x) + 0100)
|
|
#define TSSTOASC(x) ((x) + 040)
|
|
|
|
t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
|
|
UNIT *uptr, int32 sw)
|
|
{
|
|
int32 cflag, i, j, sp, inst, disp, opc;
|
|
extern int32 emode;
|
|
|
|
cflag = (uptr == NULL) || (uptr == &cpu_unit);
|
|
inst = val[0];
|
|
if (sw & SWMASK ('A')) { /* ASCII? */
|
|
if (inst > 0377) return SCPE_ARG;
|
|
fprintf (of, FMTASC (inst & 0177));
|
|
return SCPE_OK;
|
|
}
|
|
if (sw & SWMASK ('C')) { /* characters? */
|
|
fprintf (of, "%c", SIXTOASC ((inst >> 6) & 077));
|
|
fprintf (of, "%c", SIXTOASC (inst & 077));
|
|
return SCPE_OK;
|
|
}
|
|
if (sw & SWMASK ('T')) { /* TSS8 packed? */
|
|
fprintf (of, "%c", TSSTOASC ((inst >> 6) & 077));
|
|
fprintf (of, "%c", TSSTOASC (inst & 077));
|
|
return SCPE_OK;
|
|
}
|
|
if (!(sw & SWMASK ('M'))) return SCPE_ARG;
|
|
|
|
/* Instruction decode */
|
|
|
|
opc = (inst >> 9) & 07; /* get major opcode */
|
|
if (opc == 07) /* operate? */
|
|
inst = inst | ((emode & 1) << 12); /* include EAE mode */
|
|
if (opc == 06) { /* IOT? */
|
|
DEVICE *dptr;
|
|
DIB *dibp;
|
|
uint32 dno = (inst >> 3) & 077;
|
|
for (i = 0; (dptr = amb_dev[i]) != NULL; i++) { /* check amb devices */
|
|
if ((dptr->ctxt == NULL) || /* no DIB or */
|
|
(dptr->flags & DEV_DIS)) continue; /* disabled? skip */
|
|
dibp = (DIB *) dptr->ctxt; /* get DIB */
|
|
if ((dno >= dibp->dev) || /* IOT for this dev? */
|
|
(dno < (dibp->dev + dibp->num))) {
|
|
inst = inst | ((i + 1) << 12); /* disambiguate */
|
|
break; /* done */
|
|
}
|
|
}
|
|
}
|
|
|
|
for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
|
|
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
|
|
if ((opc_val[i] & 077777) == (inst & masks[j])) { /* match? */
|
|
|
|
switch (j) { /* case on class */
|
|
|
|
case I_V_NPN: case I_V_IOA: /* no operands */
|
|
fprintf (of, "%s", opcode[i]); /* opcode */
|
|
break;
|
|
|
|
case I_V_FLD: /* field change */
|
|
fprintf (of, "%s %-o", opcode[i], (inst >> 3) & 07);
|
|
break;
|
|
|
|
case I_V_MRF: /* mem ref */
|
|
disp = inst & 0177; /* displacement */
|
|
fprintf (of, "%s%s", opcode[i], ((inst & 00400)? " I ": " "));
|
|
if (inst & 0200) { /* current page? */
|
|
if (cflag) fprintf (of, "%-o", (addr & 07600) | disp);
|
|
else fprintf (of, "C %-o", disp);
|
|
}
|
|
else fprintf (of, "%-o", disp); /* page zero */
|
|
break;
|
|
|
|
case I_V_IOT: /* IOT */
|
|
fprintf (of, "%s %-o", opcode[i], inst & 0777);
|
|
break;
|
|
|
|
case I_V_OP1: /* operate group 1 */
|
|
sp = fprint_opr (of, inst & 0361, j, 0);
|
|
if (opcode[i]) fprintf (of, (sp? " %s": "%s"), opcode[i]);
|
|
break;
|
|
|
|
case I_V_OP2: /* operate group 2 */
|
|
if (opcode[i]) fprintf (of, "%s", opcode[i]); /* skips */
|
|
fprint_opr (of, inst & 0206, j, opcode[i] != NULL);
|
|
break;
|
|
|
|
case I_V_OP3: /* operate group 3 */
|
|
sp = fprint_opr (of, inst & 0320, j, 0);
|
|
if (opcode[i]) fprintf (of, (sp? " %s": "%s"), opcode[i]);
|
|
break;
|
|
} /* end case */
|
|
|
|
return SCPE_OK;
|
|
} /* end if */
|
|
} /* end for */
|
|
return SCPE_ARG;
|
|
}
|
|
|
|
/* Symbolic input
|
|
|
|
Inputs:
|
|
*cptr = pointer to input string
|
|
addr = current PC
|
|
*uptr = pointer to unit
|
|
*val = pointer to output values
|
|
sw = switches
|
|
Outputs:
|
|
status = error status
|
|
*/
|
|
|
|
t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
|
|
{
|
|
int32 cflag, d, i, j, k;
|
|
t_stat r;
|
|
char gbuf[CBUFSIZE];
|
|
|
|
cflag = (uptr == NULL) || (uptr == &cpu_unit);
|
|
while (isspace (*cptr)) cptr++; /* absorb spaces */
|
|
if ((sw & SWMASK ('A')) || ((*cptr == '\'') && cptr++)) { /* ASCII char? */
|
|
if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */
|
|
val[0] = (t_value) cptr[0] | 0200;
|
|
return SCPE_OK;
|
|
}
|
|
if ((sw & SWMASK ('C')) || ((*cptr == '"') && cptr++)) { /* sixbit string? */
|
|
if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */
|
|
val[0] = (((t_value) cptr[0] & 077) << 6) |
|
|
((t_value) cptr[1] & 077);
|
|
return SCPE_OK;
|
|
}
|
|
if ((sw & SWMASK ('T')) || ((*cptr == '"') && cptr++)) { /* TSS8 string? */
|
|
if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */
|
|
val[0] = (((t_value) (cptr[0] - 040) & 077) << 6) |
|
|
((t_value) (cptr[1] - 040) & 077);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Instruction parse */
|
|
|
|
cptr = get_glyph (cptr, gbuf, 0); /* get opcode */
|
|
for (i = 0; (opcode[i] != NULL) && (strcmp (opcode[i], gbuf) != 0) ; i++) ;
|
|
if (opcode[i] == NULL) return SCPE_ARG;
|
|
val[0] = opc_val[i] & 07777; /* get value */
|
|
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
|
|
|
|
switch (j) { /* case on class */
|
|
|
|
case I_V_IOT: /* IOT */
|
|
cptr = get_glyph (cptr, gbuf, 0); /* get dev+pulse */
|
|
d = get_uint (gbuf, 8, 0777, &r);
|
|
if (r != SCPE_OK) return SCPE_ARG;
|
|
val[0] = val[0] | d;
|
|
break;
|
|
|
|
case I_V_FLD: /* field */
|
|
for (cptr = get_glyph (cptr, gbuf, 0); gbuf[0] != 0;
|
|
cptr = get_glyph (cptr, gbuf, 0)) {
|
|
for (i = 0; (opcode[i] != NULL) &&
|
|
(strcmp (opcode[i], gbuf) != 0) ; i++) ;
|
|
if (opcode[i] != NULL) {
|
|
k = (opc_val[i] >> I_V_FL) & I_M_FL;
|
|
if (k != j) return SCPE_ARG;
|
|
val[0] = val[0] | (opc_val[i] & 07777);
|
|
}
|
|
else {
|
|
d = get_uint (gbuf, 8, 07, &r);
|
|
if (r != SCPE_OK) return SCPE_ARG;
|
|
val[0] = val[0] | (d << 3);
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case I_V_MRF: /* mem ref */
|
|
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
|
if (strcmp (gbuf, "I") == 0) { /* indirect? */
|
|
val[0] = val[0] | 0400;
|
|
cptr = get_glyph (cptr, gbuf, 0);
|
|
}
|
|
if ((k = (strcmp (gbuf, "C") == 0)) || (strcmp (gbuf, "Z") == 0)) {
|
|
cptr = get_glyph (cptr, gbuf, 0);
|
|
d = get_uint (gbuf, 8, 0177, &r);
|
|
if (r != SCPE_OK) return SCPE_ARG;
|
|
val[0] = val[0] | d | (k? 0200: 0);
|
|
}
|
|
else {
|
|
d = get_uint (gbuf, 8, 07777, &r);
|
|
if (r != SCPE_OK) return SCPE_ARG;
|
|
if (d <= 0177) val[0] = val[0] | d;
|
|
else if (cflag && (((addr ^ d) & 07600) == 0))
|
|
val[0] = val[0] | (d & 0177) | 0200;
|
|
else return SCPE_ARG;
|
|
}
|
|
break;
|
|
|
|
case I_V_OP1: case I_V_OP2: case I_V_OP3: /* operates */
|
|
case I_V_NPN: case I_V_IOA:
|
|
for (cptr = get_glyph (cptr, gbuf, 0); gbuf[0] != 0;
|
|
cptr = get_glyph (cptr, gbuf, 0)) {
|
|
for (i = 0; (opcode[i] != NULL) &&
|
|
(strcmp (opcode[i], gbuf) != 0) ; i++) ;
|
|
k = opc_val[i] & 07777;
|
|
if ((opcode[i] == NULL) || (((k ^ val[0]) & 07000) != 0))
|
|
return SCPE_ARG;
|
|
val[0] = val[0] | k;
|
|
}
|
|
break;
|
|
} /* end case */
|
|
|
|
if (*cptr != 0) return SCPE_ARG; /* junk at end? */
|
|
return SCPE_OK;
|
|
}
|